SU1287146A1 - Device for processing data - Google Patents

Abstract

The invention relates to computing and can be used in computer processors. The purpose of the invention is to increase the speed when performing a division operation. The goal is achieved in that the device containing the register 1 operand, the main switch 2, the byte switch 3, the main arithmetic logic unit 4, the byte arithmetic logic unit 5, the main register 6, the byte register 7, the shift 9, the shift register 11 , multiplier switch 12, accelerated multiplication unit 14, sign formation unit 15, 16 clock counter, microprogram control unit 19, shifter 10 and private selection unit 13, 3 hp, f-files, 8 dw., 4 tab. 1со to 00 Od

Description

The invention relates to computing and can be used in universal and specialized processors.

The aim of the invention is to improve the speed when performing a division operation.

Fig. 1 is a schematic of the proposed data processing device; in fig. 2 is a block selection diagram of the private; Fig 3 is the same as an accelerated multiplication unit; Fig. 3 is the same as a sign generation unit; in fig. 5 is a boot algorithm diagram; in fig. 6 - the same as the addition algorithm; in fig. 7 is the same as the multiplication algorithm; FIG. 8 is the same as the division algorithm,

The data processing device (FIG. 1) contains the register 1 of the operand, the main switch 2, the byte switch 3, the main arithmetic logic unit 4, the byte arithmetic logic unit 5, the main register 6, the byte register 7, the main switch 8, shifters 9 and 10, shift register 11, switch 12 multiplier, block 13 private selection, block

14 accelerated multiplication, sign generation unit 15, 16 clock counter, device information input 17, output, device 18, device control unit 19, device operation mode input 20, device installation input 21, device operation start input 22, unit 19 clock output 23 firmware control, inputs 24-27 of the condition of the microprogram control unit 19, control outputs 28-43.

The block for selecting the quotient (Fig. 2) contains the dividend register 44, the tabular divider converter 45, the shifters 46 and 47 of the dividend and the divider, the private memory element 48, the private counter 49 and the private register 50.

The accelerated multiplication unit 14 (FIG. 3) contains the spreadsheet converter 51, the shifters 52-54, the switch 55, the arithmetic logic elements 56 and .57,

35

45

50

The sign forming unit 15 of FIG. 4 contains the switch 58, the EXCLUSIVE OR element 59, the character register 60, the arithmetic logic element 61.

Firmware control unit 19 may be implemented. Similarly

five

0

known In block 19, micrographs of the multi-control, the microprograms are encoded according to FIG. 5-8. Used microcommands are given in table. one.

The quotient selection block 13 is intended to select by the five most significant bits of the dividend (remainder) n divisor hexadecimal quotient from the quota private memory element that is equal to or greater than but not more than two units of the true quotient digit, as well as to change when the need for the selected digit quotient per unit on the counter.

 Block 14 accelerated multiplication. designed to multiply the multiplicand mantissa by four bits of the multiplier, as well as multiply the mantissa

fourfold

five

divider on the experienced number of private.

The shifters 9 and 10 shift, respectively, by four bits toward the higher and lower bits.

Shift register 11 is designed to store and shift the quotient and multiplier by four digits, respectively, towards the lower and lower digits when writing the true four-digit digit of the partial and partial products.

The sign generation unit 15 performs an analysis of the signs of the source operands involved; they are in operations, establishing the sign of the result.

The code for fixing the memory element 48 is often presented in Table. 2

The shifters 52-54 respectively shift one, two, and three bits toward the higher bits.

The coding table 51 converter multiplier is presented in Table. 3, which indicates the multiplicity of the multiplicand at the inputs of the switch 55, elements 56 and 57, and the function performed by them.

Encoding tabular converter 45 divider is presented in table. 4, which displays an algorithm for converting a bit divisible and a divider into address bits of a private memory element 48,

The arithmetic humic units 4 and 5 and the arithmetic logic elements 56, 57 and 61 are implemented on the universal arithmetic logic elements of the 155 series.

The data processing apparatus operates as follows.

The operation of the device starts with the launch of the i 9 firmware control unit. On the reset signal at input 21, block 19 is set to its initial state and generates codes at all its outputs that correspond to the original microcommand O. Thereafter, the command code to be executed is input to input 20. When a signal arrives at input 22, micro-commands are formed in block 19 and the necessary micro orders are given to inputs 28-43 taking into account the conditions received at inputs 24-27 At output 23, the corresponding clock signals are generated, which ensures the functioning of the device according to a single-shot principle.

At the end of the execution of the firmware corresponding to the specified command code, the last micro-command sets an unconditional transition to the micro-command о and thus puts the device into the initial state, at which the clock signals are blocked, block 19 switches to the reception of the next command code.

FIG. 5 shows the firmware download algorithm. The load command is executed in two cycles.

In the first cycle (microinstruction 1), the loadable operand is written on the first entry in register 1 of the operand. In the second cycle (microcommand 2), the order, the mantissa and the sign of the operand, respectively, from the outputs of the register 1 of the operand arrive at the first input of switch 3, the first input of switch 2 and the first input of switch 3, the first input of switch 2 and the first input of forming unit 15 sign. .

Switches 2 and 3 are switched to transmit from the first inputs. The mantissa and order come to the first inputs of block 4 and 5, which in this micro-command perform the functions of transmission from the first inputs. From their outputs, the mantissa and order are recorded from the first inputs to registers 6 and 7.

The sign of the operand from the first input of the switch 58 is transmitted to the first input of the element 61 and then to the input, register 60. Recording in registers 6, 7 and 60 is made upon receipt of 64

of the clock signal to the clock inputs of the registers.

FIG. 6 shows the addition algorithm of the firmware. The addition command is executed after the execution of the first operand load command. In microcommand 1, the second operand is written by the first entry in register 1 of the operand. In the next cycle (micro-command G), the order of the second operand through the switch 3 enters the first input of block 5, and the second operand of register 7 receives the order of the first operand. The orders are subtracted and the difference of the orders from the output of block 5 is recorded in a 16 clock counter. As a condition of transition in this

the micro-command uses the sign at input 24 and input 26 of the zero state of the counter 16 cycles. If the order difference is positive and non-zero, go to microinstruction 8, which shifts the mantissa of a smaller number towards the lower order bits and decreases the counter content of 16 clock cycles by one. The microinstruction 8 is repeated until the 16 clock counter is reset. If the order difference obtained in microcode 3 is negative, then microcommand 9 follows, in which the first and second operands are swapped. The first operand from the output of register 6 and 7 and register 60 block

15 is written to register 1 of the operand from the second input, and the contents of register 1 of the operand are written to registers 7, 6 and 60 in the same way as microcommand 2. In microcommand 10, the order of operands is subtracted, and the positive difference is written into the counter

16 ticks and then follows the transition to a microinstruction 8 for shifting the mantissa of the smaller operand. In the zero state of the 16-clock counter, obtained in microcommands 3 or 8, microcommand V4 is executed, in which the signs of operands coming to the second and third inputs of element 59 are analyzed, and the sign of the add operation (0) arriving at the first input, these three signals are added modulo two and depending on the bit of the amount received, there is a transition to microinstruction 5, in which the mantissa of the operands are added, or to microinstruction 6, in which the mantissa are subtracted. Addition and subtraction of mantis are made in block 4. One of

512

the mantissa enters the first input of block 4 from the first input of switch 2, the other mantissa enters the second input of block 4 from the first input of switch 8. The sign of the resulting operand is determined depending on the sign of the difference of the mantissa. This action is performed on the element 61 of block 15 (Fig. 4), at the first input of which, via the second input of the switch 58, the sign from the output of block 4 and the sign contained in the register of the sign. Element 61 performs the function of inverse addition modulo two, the result which is the sum of the operands, is written in the register of symbols 60. The negative sign of the difference of the mantiss determines the need to switch to microcommand 7, in which the resulting difference from the output of register 6 through the first input of the switch 8 is fed to the second input of block 4, and his ne The third input through the third input of the switch 2 is fed to the zero mantissa, previously obtained by clearing the shift register 11. The subtraction function is executed, and thus the result mantissa from the additional code is converted into a direct code and written into register 6.

The order of the operand contained in register 7. is the order of the result

Subtraction command firmware

is performed similarly, with the only difference that, when determining the sign at the output of element 59, its first input is inversely added to the sign of subtraction.

FIG. Figure 7 shows the multiplication algorithm. The multiply command is preceded by the load command of the first operand (multiplier). In microcomputer O, the contents of the main register 6 are rewritten into shift register 11, In microcommand 1, the second operand (multiplicative) is written into the operand register 1 and constants in the counter 16 clock cycles. In the next microcommand 11, from the output of the register 11, the shift of the tetrad multiplier is fed to the first input of the I2 multiplier switch, from the output of which the tetrad multiplier goes to the input of the accelerated multiplication unit 14 and to the input of the multiplier 51 converter. Depending on the incoming code on the first, second and third

5 0 5 0

5 0 5

five

0

466

At the outputs of converter 51, the multipliers are generated in the form of function control codes in accordance with Table. 3. The first and second inputs of the switch 55, respectively, are received once and twice the mantissa of the multiplicand. The first and second inputs of the element 56 are supplied, respectively, fourfold and eightfold mantissa multiplicand.

The product of the multiplier {multiplier per tetrad is formed at the output of element 57 and through the second input of switch 2, the second input of block 4, the shifter 10 is written to register 6.

In the same tact, a shift is made to the tetrad towards the lower bits of the mantissa of the mnsteel contained in the reg ister 11 of the shift, so the next multiplier tetrad is prepared at the output of the lower bits of the shift register 11.

The constant entered into the counter is 16 clocks, in microcommands 11 and 12 it decreases by one. In microcommands 12, the forming products of a multiplier for the next hexadecimal digit multiply with a partial sum of works shifted by a tetrad in the direction of lower-order bits. The partial sum of the products is accumulated in register 6 and is fed to the summation on the second, the input of block 4 through the switch 8. The partial sum is shifted by the shifter 10 when writing to register 6.

The ordering is performed in block 5, the order of the result is recorded in register 7.

The formation of the character is carried out in block 15 on the element 61, which performs the function of addition modulo two. The result of the addition is the sign of the product and is written to register 60.

In microcommand 13, the last partial product is summed and the sum of partial products written to register 6 without being shifted from the first input.

FIG. 8 shows the dividing firmware. The division command is preceded by a command that loads the first operand (the dividend). In microcommand 14, the second operand (divisor) is recorded in register 1 of the operand, and in the 16-clock counter, a constant determining the required number of private tetrads.

712

The divisible mantissa is shifted to the tetrad in the direction of the lower bits by transmitting the mantissa through the switch 8, block 4 and the shifter 10 to the record from the second register input 6. In the next microcom, the upper eight bits of the register 6, pass through the switch 8, block 4 is written to divisible register 44. The recorded bits represent the initial vector of the dividend. From the output of register 1 of the operand, the upper eight bits representing the divider vector are fed to the input of the divider converter 45 and the input to the shifted 47 dividers bodies (Fig. 2). In the divider converter 45, the number of zeros from a comma, conditionally fixed before the high bit, is determined.

BEFORE the first unit, and control is provided to the inputs of the shifters 46 and 47 of the dividend and the divider to shift Ka, the corresponding number of digits to the commanding side, C the outputs of the dividers and dividers, five divisible bits and bits from the second to the fifth the divider is fed to the first and second inputs of the private memory element 48, respectively.

The filling of the private memory element 48 is shown in Table 2. At the corresponding address, the test value of the four-bit private is formed, which does not exceed the true hexadecimal number of the private

From the output of the private tetrade is written to the private counter 49 and enters the first output of the private selection unit 13 and then through the input of the multiplier switch 12 to the input of the accelerated multiplication unit 14, the divisor's mantissa enters the other input 1 of the operand 1, In the accelerated multiplication unit 14 is formed the product of the divider on the tetrade of the chosen digit of the private

To check the digit, the resulting product through the second input of switch 2 is fed as a subtracted to the first input of block 4, to the second input of which divisible register 6 is fed, shifted by shifter 9 towards the higher bits, Block 4 performs the subtraction function. I

If the result of the subtraction is positive, then the selected quotient is true, - A transition follows.

five

71

.5 Oh

P

35

0

468

to microcommand. 17, and the contents of the 16 clock counter are decremented by one.

In micro-command 17, the contents of private counter 49, rewritten into private register 50 from the latter’s output, are written to the lower tetrad of the shift register 11, which performs the FUNCTION of the shift by the tetrad towards the higher bits, The highest eight bits of the resulting balance are written to the divisible register 44,

In the micro-command 17, the operation of the device proceeds as described.

The divider vector is a constant value during the whole process of dividing a pair of numbers, since it is determined only by the higher bits of the divider.

The process described is repeated.

When a negative subtraction is obtained in block 4, a transition to microcommand 18 follows. In this microcommand, a new test is performed, which means that the mantissa of the divider, which comes from the first input of switch 2, is added to the remainder written in register 6. The ALU performs an add function.

If the result of the second dash is positive, then the content of the private register 50, representing the selected private digit value reduced by one, is written to the shift register 11 by shifting towards the higher bits. In the subsequent cycles, the operation proceeds as described by the algorithm. The last digit private is written to shift register 11. Since each entry in shift register 11 is performed. If the information is shifted by the tetrads toward the higher bits, then after the last shift in the shift register 11, the mantissa of the quotient will be formed. The exit from the cycle is carried out on the basis of zeroing the counter of 16 cycles,

In block 5, during the division operation, two actions were performed: subtracting the difference between the orders of the dividend and the divisor and adding to the difference between the orders the unit that compensates the initial shift by the tetrad of the mantissa

91

divisible in the direction of younger bits. The received private order is stored in register 7. Operands with operand signs are similar to those performed by multiplication firmware. In the last microcommand 19, the contents of shift register 11 through the third input of switch 2 and block 5 are rewritten into register 6.

Claims (4)

Invention Formula 1 „Device for data processing containing operand register, two the output of the shift register is connected to the first information input of the switch multiplier and to the third information input of the first main switch, the output of the sign bit of the register of the operand is connected to the first information input of the sign generation unit,: The output of the sign of the main arithmetic logic unit is connected to the second information input of the sign generation unit , the first output of which, the output of the byte register and the output of the main register are connected respectively with the bits of the bits main communicator, byte comm information input register ten the output of the shift register is connected to the first information input of the switch multiplier and to the third information input of the first main switch, the output of the sign bit of the register of the operand is connected to the first information input of the sign generation unit,: The output of the sign of the main arithmetic logic unit is connected to the second information input of the sign generation unit , the first output of which, the output of the byte register and the output of the main register are connected respectively with the bits of the bits tator, basic arithmetic logic unit, byte arithmetic logic unit, main register, byte register, first shifter, shift register, multiplier switch, continuous multiplication unit, clock counter, sign generation unit and microprogram control unit, with the information input of the device connected to the first information input of the operand register, the bit output of the mantissa of which is connected to the first information input of the first main switch, the output of which is connected to the first information input ohm of the main arithmetic logic unit, the output of the result of which is connected to the first information input of the main register, the output of which is connected to the first information input of the second main switch and the input of the first shift body, the output of which is connected to the second information input of the second main switch, the output of which is connected with the second information input of the main arithmetic logic unit, the bit output of the mantissa register of the operand is connected to the input of the multiplicative block of the accelerated multiplication, output One of which is connected to the second information input of the first main switch, the bit output of the order of the operand register is connected to the first information input of the byte switch, the output of which is connected to the first information input of the byte arithmetic logic unit, the result of which is connected to the information one the input of the byte register, the switch output of the multiplier is connected to the input of the multiplier of the accelerated multiplication unit, operand, the input of the operation mode of the device is connected to the address input of the microprogram control unit, the installation and start inputs of which are connected respectively to the installation input and the start of operation of the device, the clock output of the microprogram control unit is connected to the clock input of the sign forming unit, with the clock input of the shift register , with the main register register enable input, with the counting clock counter input, with the first byte register receive enable input and with the register register enable input The conditional inputs of the microprogram control block are connected to the output of the byte-I o arithmetic logic unit, to the output of the main arithmetic-logic block, to the output of the clock counter and to the second output of the sign-forming unit, and to control the outputs of the microprocess control unit connected, respectively, with the first control input of the sign-forming unit, with the second input of the byte register reception permission, with the input of the type of operation of the byte arithmetic unit, with control 1osh, them in house byte switch, a control input operand register vho.dom specifying a shift register mode, to the control input of the main yunschm register, with the input of the type of operation of the main arithmetic logic unit, with the control input of the first main switch, with the control input of the second main switch, with the input of the clock counter mode and with the second information input of the byte switch, characterized in that, in order to When a division operation is performed, it contains a second.shift and a private selection unit, the second information input of the operand register is connected to the output of the device, the output of the byte arithmetic logic unit is connected to the information input of the clock counter, the output of the main arithmetic logic unit about the counting input of the private counter, with C9 connected to the input of the second shifter, the output of which is connected to the second information input of the main register, the output of which is connected to the enable input of the register of the dividend and the clock input of the private selector, the control input and the first, second and third outputs of the first information input of the register 5 are connected respectively with the input j shift, the output of the byte register is to set the mode of the private counter, one with the second information input byte arithmetic logic unit, the output of the result of the main arith20 of the logic unit and the bit output of the register operand mantissa I are connected respectively to the inputs of the divisible and divider private selection block, the clock input and the control input are connected respectively to the clock output and to the thirteenth control output of the microprogram control block, the fourteenth, n The thirteenth and sixteenth control outputs of which are connected respectively to the control input of the multiplier switch with the second and third control inputs of the sign-forming unit; first second 25 thirty with the output of the private memory element, with the output of the private counter and with the output of the private register. 3. The device according to claim 1, wherein the accelerated multiplication unit comprises a spreadsheet multiplier; a body, three shifters, a switch and two arithmetic logic elements, wherein the input of the multiplicand accelerated multiplication unit is connected to the first information input of the switch and to the inputs of the first, the second and third shifters, the output of the first shifter is connected to the second information input of the switch, the outputs of the second and third shifters are connected respectively to the first and second information inputs of the first third in the outputs of the block select private 35 arithmetic logic unit, the outputs of the switch and the first arithmetic logic element are connected respectively to the first and second information inputs of the second arithmetic logic element 40, the output of which is the output of the accelerated multiplication unit whose input of the multiplier is connected to the input of the tabular converter of the multiplier, outputs He is connected respectively to the second and third information inputs of the switch multiplier, with the second in-. formational input of the shift register. 2. The device according to claim 1, which differs in that the private selection block contains a divisible register, a tabular divider converter, dividers and a divider shifters, 45 of which are connected respectively to a private memory element, a private counter and a private register, and the input of the divisible select block private is connected to the information input of the register of the dividend, the output of which is connected to the information input of the shifter of the dividend, the output of which is connected to the first address input of the private memory element, the second address input of which is En with the output of the divider shifter, the input of the magnitude of which is connected to the input of the magnitude of the shift of the dividend and to the output of the table converter inputs for specifying the operation type of the first and second arithmetic logic elements and with the control input of the switch. 50 4. The device according to claim 1, wherein the sign forming unit comprises a switch element EXCLUSIVE OR, a sign register and an arithmetic logic element, with the first and second information inputs of the sign forming unit connected to the first and second information blocks. comm inputs the divider whose input is connected to the information input of the divider shifter and to the input of the divider of the private selection block; the output of the private memory element is connected to the information input of the private counter, the output of which is connected to the information input of the private register, the input resolution of which is connected to  5 of them are connected respectively with the input of the setting of the private meter mode, 20 25 thirty with the output of the private memory element, with the output of the private counter and with the output of the private register. 3. The device according to claim 1, wherein the accelerated multiplication unit comprises a spreadsheet multiplier; a body, three shifters, a switch and two arithmetic logic elements, wherein the input of the multiplicand accelerated multiplication unit is connected to the first information input of the switch and to the inputs of the first, the second and third shifters, the output of the first shifter is connected to the second information input of the switch, the outputs of the second and third shifters are connected respectively to the first and second information inputs of the first 45 connected respectively with inputs for specifying the type of operation for the first and second arithmetic logic elements and with the control input of the switch. 50 4. The device according to claim 1, about t l and In particular, the sign generation unit contains a switch, an EXCLUSIVE OR element, a character register and an arithmetic logic element, with the first and second information inputs of the sign generation unit connected to the first and second information inputs of the communi- The tator whose output and output of the sign register are connected respectively to the first and second information inputs of the arithmetic logic unit, the output of which is connected to the information input of the sign register, whose output and output of the EXCLUSIVE OR element are connected respectively to the first and second outputs of the sign generation unit, clock input, 10 first, second and third control Element 61 Register 7 Register 1 operand Shift register 11 Primary register 6 Element 61 Register 7 Block 5 Switch 3 Register 1 operand Register 11 shift Pei HCTp 6 Counter 16 clock cycles Second Switch Code 3 Element 61 Switch 58 Register 7 Block 5 Switch 3 U614 the inputs of which are connected respectively to the input of the permission of the reception of the character register, to the first input of the EXCLUSIVE OR element, to the input of specifying the operation type of the arithmetic logic element and to the control input of the switch, the output of the register of the sign and the first information input of the switch are connected respectively to the second and third the inputs of the EXCLUSIVE OR element. Table Transfer from input 2 Storage and Record Storage Transfer from input 2 Storage Transfer from entry 1 Transfer from input 2 Entry Record 1 Storage -. „ Record and store constant Transmission from input 1. „. . Record about Transfer from input 1 and 17 lill 2 36 37 42 29 34 35 36 37 42 29 32 34 35 37 38 42 43 29 30 31 32 34 35 36 42 29 30 ten Switch 1 Switch 8 Element 61 Register 7 Register 6 Block 4 Switch 2 Switch 8 Element 61 Register 7 Register 1 operand Register 6 Block-4 Switch 8 Counter 16 cycles Element 61 Switch 58 Register 7 Block 5 Switch 3 Register 1 operand Register 6 Block 4 Switch 2 Element, 61 Register 7 Block 5 1287146.18 Continued-tab. one Transfer from Input 1 II Transfer from input 2 Storage Entry Record 1 Subtraction Transfer from entry 3 Transfer from entry 1 Transfer from input 2 Storage 1 Recording on input 2 Transmission from input 2 Transmission from input 1 Account Transfer from entry 1  h Record Transmission from input 1 Transmission from input 1 Recording by input 2 Recording by input 1 Transfer from input 1 11 Transfer from input 2 Storage Subtraction  21 128714622 Continued table. one 23128714624 Continued table. 1 IP 2 38 Counter 16 clocks Storage 1642 Element 61 Transfer from input 2 29 Register 7 Storage 32Register 1 operand- 33Register 11 shift- 34Register 6A record on input 1 35Block 4Discharge 36Switch 2Transfer from input 2 37Commutator 8 .- 40Counter 49 private record and account 41 Switch 12 multi-transfer from the input 2 residents 38 counter 16 clocks 17. 42Ilement 61. Transfer from Input 2 29 Registrar 7 Storage 32Register 1 operand- 33Register 11 shiftShift by tetrad to senior side 34Register 6 Entry 1 Record 35Block 4Discharge 36Switch 2Transfer from input 2 37The switch 8- 4Q Counter 49 private record and account 41 Switch 12 multi-transfer from the input 2 residents 38 counter 16 clocks 1.8 42Ilement 61Transmission from Input 2 l 29 Registrar 7 Storage 32Register 1 operand- 9 33Register 11 shift 34 Register 6 35Block 4 36 Switch 2 37 Switch 8 40 counter 49 private 38 Counter 16 cycles 42 Element 61 29 Registrar 7 30Block 5 31 Switch 3 34 Register 6 35Block 4 36 Switch 2 39 Second input of switch 3 Entry Record 1 Addition Transmission from input 1 Transmission from input 1 Score Storage Transfer from input 2 Record Addition Transfer from input 2 Entry Record 1 Transfer from entry 1 Transfer from entry 3 Unit table 2 Continued table. 2 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 31 tt tt II II II II II II I II II tl tl II tl 31 tl tl II tl tl tl II tl 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A A B B C C d d HER F F F w o 0) and S with CU and o m o r with - m - 0) to S about 0) about S about. and and X x 11 о ш о к yo and X s 01 X and about p : 00 00 OO00 ra and 14 s one FIG. g srcg.Z Micro-command O Micrommand / Microcommand 2 Microcomdom about Fi9.5 LolojitemnbshSh McCrocomond O MUHpOHOfiCfHdO 1 Microcommand / / Minro "Onanda / z  ost - on entrance 26 McCroconando 1 3 MuKpOf ofia fda o FIG. 7 Zero uxpoKOfiOHda G5 j --- T-