SU1092537A1 - Device for monitoring and displaying information - Google Patents

Abstract

A DEVICE FOR REGISTRATION OF INFORMATION, containing a memory block. (Decipher, sign indicator, second decoder, graphic indicator, first and second counters, frequency divider, one-shot, first phase-shifting unit, first And element, switch, register, outputs of which are connected to inputs sign indicator, the register group inputs are connected to the switch outputs, the inputs of the first group of which are connected to the inputs of the first decoder and the outputs of the memory unit, the inputs of the group of which are the inputs of the device group, the output The first decoder is connected to the inputs of the first group of the graphical indicator, the inputs of the second group of which are connected to the outputs of the second decoder, the inputs of the latter are connected to the outputs of the first counter, the input of which is connected to the output of the first element I, the output of the second counter is connected to the input of the frequency divider, the input of the one-shot and the input register, the input of the second counter is connected to the output of the first phase-shifting unit, the second input of which is connected to the output - frequency divider, the third and fourth inputs of the first phase-shifter block are the first and second inputs of the device, respectively, characterized in that, in order to increase the amount of recorded information, the third and fourth counters, the second phase-shifting block, the second And element, the trigger, the first input of which is connected to the output of the higher bit, are entered into it the first i counter, the second input of the trigger is connected to the output of the third counter, the input of which is connected to the output of the second element And, the second input of the third phase-shifting unit and the first input of the first element And, the second input cat connected to the trigger output, the first input of the second element of the AND is the third input of the device, the second input of the second element And is connected to the output of the one-vibrator, O the input of the memory unit is connected to the first input of the first phase-shifting unit, the output of the second phase-shifting unit and the input the fourth counter, the outputs of which are connected to the inputs of the second group of switch, the output of the frequency divider is connected to the first input of the second phase-shifting unit, the third and fourth inputs of which are respectively the fourth and fifth; inputs.

Description

The invention is intended for use in information and measurement technology and can be used to visually examine the form of single and periodic signals and to measure their garameters.

A device for digital recording is known comprising an analog-to-diffraction converter, a memory unit, a decoder, and a matrix panel d E.

The disadvantage of this device is the low accuracy of the amplitude and time parameters of the signals under study, since the measurements are carried out directly on the screen of the matrix panel, and the subjective factors peculiar to the operator affect the measurement results.

The closest in technical essence is a digital recorder containing a memory block, a first decoder, a character indicator, a second decoder, a graphical indicator, first and second counters, a frequency divider, a single vibrator, the first phase-shifting unit, the first And element, a switch, a register, the outputs of which are connected to the inputs of the indicator indicator, the inputs of the register group are connected to the outputs of the switch, the inputs of the first group of which are connected to the inputs of the first decoder and the outputs of the memory unit, the inputs of the group are input The device group's outputs, the outputs of the first decoder, are connected to the inputs of the first group of the graphic indicator, the inputs of the second group of which are connected to the outputs of the second decoder, whose inputs are connected to the outputs of the first counter, the input of which is connected to the output (First element I, first input of the first phase-shifting unit and in the memory unit code, the output of the second counter is connected to the input of the frequency divider, the register input and the one-shot input, the second counter input is connected to the output of the first phase-shifting unit, the second input D which is connected to the output of the frequency divider, the third and fourth inputs of the first phase-shifting unit are the first and second inputs of the device, respectively, the second input of the first element I is the fourth input of the device 23.

The disadvantages of this digital recorder are the low informational capacity and accuracy of estimating the temporal characteristics of the process being studied, limited by the information capability of the matrix panel, since reading the digital amplitude and temporal characteristics is possible only within the information capacity of the matrix panel 3 and the memory capacity is limited.

The purpose of the invention is to increase the amount of recorded information and improve the accuracy of measurements of the temporal parameters of the studied processes.

The goal is achieved by the fact that a digital recorder containing a memory block, the first decoder, the sign indicator, the second decoder, the graphic indicator, the first and second counters, the frequency divider, the one-shot, the first phase-shifting unit, the first And element, the switch, the register, the outputs which are connected to the inputs of the indicator indicator; the inputs of the register group are connected to the outputs of the switch, the inputs of the first group of which are connected to the inputs of the first decoder and the outputs of the memory unit whose inputs of the group are inputs and device groups, the outputs of the first decoder are connected to the inputs of the first group of the graphic indicator, the inputs of the second group of which are connected to the outputs of the second decoder, the inputs of the last are connected to the outputs of the first counter, the input of which is connected to the output of the first element And, the output of the second counter is connected to the input frequency divider, one-shot input and register input, the second counter input is connected to the output of the first phase-shifting unit, the second input of which is connected to the output of the frequency splitter, the third and the fourth The first inputs of the first phase-shifting unit are the first and second inputs of the device, the third and quarter counters are additionally added, the second phase-shifting unit, the second And element, the trigger, the first input of which is connected to the senior output of the first counter, the second input of the trigger is connected to the output of the third counter, the input of which is connected to the output of the second element Hj. the second input of the second phase-shifting unit and the first input of the first element I, the second input of which is connected to the output of the trigger; the first input of the second element I is the third input of the device; the second input of the second element I is connected to the output of the one-vibrator; the input of the memory unit is connected to the first input of the first phase-shifting unit, the output of the second phase-shifting unit and the input of the fourth counter, the outputs of which are connected to the inputs of the second switch group, the output of the frequency divider is connected to the first input of the second phase-shifting The unit, the third and fourth inputs of which are the fourth and fifth inputs of the device, respectively.

The drawing shows a block diagram of a device for recording information.

The device contains the character indicator 1, memory block 2, the first decoder 3, the graphic indicator 4, the first counter 5, the second decoder 6, the fourth counter 7, the second counter 8, the third counter 9, the first element 10 And, the trigger 11, the second phase-shifting unit 12, the frequency divider 13, the first phase-shifting unit 14, the one-shot 15, the second element 16 And, the switch 17, the register 18.

The device works as follows. .

The codes of the instantaneous values of the input signal with the sampling rate specified by the operator are transferred to memory block 2. At the end of the recording, when the memory capacity of the memory block 2 is filled with the codes of the instantaneous values of the signal under study, the codes with a speed determined by the speed of the graphic indicator 4 (when using the gas discharge display panel, the speed is 5000 samples / s) are fed through the first decoder 3 to the graphic indicator 4, thereby connecting the corresponding horizontal bus of the graphic indicator 4 to one pole of the power source. The image is scanned horizontally on the screen of the graphic indicator 4 using the first counter 5 and the second decoder 6, which connect successively vertical busbars of the graphic indicator 4, corresponding to

sample number, at the same rate of 5000 samples / s (f 5 kHz). As a result, on the screen of the graphic indicator 4, the light point formed at the crosshairs of the horizontal and vertical tires moves across the screen of the graphic indicator 4 in accordance with the shape of the input signal.

Improving the accuracy of measuring the temporal characteristics and information capacity of the device is achieved by increasing the memory capacity of memory block 2 as compared to the information capability of the graphic indicator 4. In this case, the measurement error of the abscissa determined by the discreteness of the graphic indicator 4 is determined

100

(S - Yu g

where f is the memory capacity of block 2 of memory, bits.

The abscissa code corresponding to the signal point is generated at the output of the fourth counter 7. Thus, each position of the signal point corresponds to the ordinate code at the output of memory block 2 (Y) and the abscissa code at the output of the fourth counter 7 (X).

To measure the coordinates of any point of the signal being studied, a marker point of increased luminance is formed on the screen of the graphic indicator 4, which is formed due to the fact that the sweep stops for several periods of the frequency fo. The second counter 8, the third counter 9, the fourth counter 7 and the first counter | 5 switch synchronously and in-phase with the frequency, however, since the capacity of the first counter 5 (equal to (i.e. the number of vertical tires of the graphic indicator 4) is less than the capacity of the counters 7.8 9 (their capacity is the same and equal to N), then after N periods of frequency fg the input of the first counter 5 is blocked using the first element 10 and trigger 11. Consequently, only a part of the information recorded in memory block 2. In order for the operator and I was able to set the marker at the desired point of the signal under investigation, recorded in memory block 2, the image must be offset so that any part of the signal recorded in memory block 2 could be displayed on the graphic indicator 4. This offset is achieved using the second phase-shifting unit 12, while the operation of the first counter 5 and the third counter 9 is misaligned with respect to the second counter and the fourth counter 7. When a right signal and a pulse from the output of the 13-hour divider output to the second phase-shifting block 12 These second phase shifting units 12 do not pass one frequency period to the second counter 8 (through the first phase shifting unit 14), the fourth counter 7, and block 2 of the memory. Thus, the state of the first counter 5 and the third counter 9 is ahead of the state of the second counter 8 and the fourth counter 7 by one unit and the image on the screen of the graphical indicator 4, as well as the marker are shifted one coordinate to the right. When a left signal arrives at the second phase shifting unit 12 and a pulse from the output of the frequency divider 13, the second phase shifting unit 12 adds one pulse to the sequence of the second counter 8, fourth counter 7, and memory 2, pulsed at the frequency, causing the image to shift and a marker one coordinate to the left on the screen of the graphic indicator 4. The frequency divider 13 serves to reduce the speed of the image and the marker. The capacity of the second counter 8 is equal to the capacity of the third counter 9 and the fourth counter 7, as well as KocTfl of the memory block 2, which makes it possible to measure the signal under study 376 recorded in the memory block 2. A marker is formed with noMouj; b: o the second counter 8 and the one-shot 15. At the output of the second counter 8, a pulse is formed corresponding to one of its states, for example zero. This pulse triggers a one-shot 15, which produces a pulse that locks the second element AND 16 for several periods of frequency tj,. If the second phase shifting unit 12 shifts the image along with the marker, the first phase shifting unit 14 shifts only the marker. Due to the fact that the capacity of memory block 2 exceeds the capacity of the first counter 5, the marker may disappear from the screen of the graphic indicator 4. In this case, the location of the marker on the signal under investigation is carried by the sign indicator 1, indicating the coordinate of the marker. Depending on the signal Y or X, which is fed to the control inputs of the switch 17, the inputs of the group of register 18 receive a sequence of codes corresponding to the ordinate or the abscissa of the process. The marker pulse, having wound up at the output of the second counter 8, allows the code to be written to the register 18. Thus, on the sign indicator 1, one of the coordinates of the marker is always displayed. Thus, the advantages of this device are the possibility of a significant increase in the information capacity of the device and a significant increase in the accuracy of measuring time parameters.

Claims (1)

INFORMATION RECORDING DEVICE, comprising a memory unit,. ^ Decoder, sign indicator, second decoder, graphic indicator, first and second counters, frequency divider, one-shot, first phase shifting unit, first AND element, switch, register, the outputs of which are connected to the inputs of the sign indicator, the inputs of the register group are connected to the outputs of the switch, the inputs of the first group of which are connected to the inputs of the first decoder and the outputs of the memory block, the inputs of the group of which are inputs of the device group, the outputs of the first of the decoder are connected to the inputs of the first group of the graphic indicator, the inputs of the second group are connected to the outputs of the second decoder, the inputs of the latter are connected to the outputs of the first counter, the input of which is connected to the output of the first element And, the output of the second counter is connected to the input of the frequency divider, the input of the one-shot and the input register, the input of the second · counter is connected to the output of the first phase-shifting unit, the second input of which is connected to the output of the frequency divider, the third and fourth inputs of the first phase-shifting unit are respectively the first and second inputs of the device, characterized in that, in order to increase the amount of recorded information, the third and fourth counters, the second phase-shifting unit, the second AND element, a trigger, the first input of which is connected to the high-order output of the first counter, are introduced into it, the second trigger input is connected to the output of the third counter, the input of which is connected to the output of the second element And, the second input of the second phase-shifting unit and the first input of the first element And, the second input of which is connected to the output trigger, the first input of the second element And is the third input of the device, the second input of the second element And is connected to the output of the one-shot, the input of the memory unit is connected to the first input of the first phase-shifting unit, the output of the second phase-shifting unit and the input of the fourth counter, the inputs of which are connected to the inputs of the second group of the switch , the output of the frequency divider is connected to the first input of the second phase-shifting unit, the third and fourth inputs of which are the fourth and fifth 7 inputs of the device, respectively.