SU1040491A1 - Fft processor addressing device - Google Patents

Abstract

1. A DEVICE FOR ADDRESSING A QUICK FURIER TRANSFORMER PROCESSOR, containing (m + k) -discharge; the address register, the outputs of which are outputs and devices, the address generation unit, the first group of inputs of which are connected to the information outputs of the k-bit counter ,. and the second group of inputs of the address shaping unit is connected to the output of the k-bit shift register, the outputs of which are connected to the information inputs of the k-bit counter, the control input of the address register, the first control input of the shift register and the control input the address generation unit are connected respectively with the first, second and third outputs of the synchronization unit, characterized in that, in order to expand its functionality by processing the dimensional processes and simplifying the circuit, t-bit is entered into it second counter having an input coupled to the third output of the synchronization unit, and information outputs m-bit. the counter is connected to the first group of inputs of the address register, the second group of inputs of which is connected to the output of the shaping-address block, the output of the n-th bit is connected to the control input x of the k-bit counter whose control output is connected to the control input k-pa8 " an equal shift register, and the output; the k-ro bit of the shift register is connected to the input of the synchronization unit. 2. The device according to claim 1, wherein the synchronization unit contains the first and second triggers, the generator of a single pulse, the element And, the delay element, the generator of clock pulses, the output of which is connected to the first input of the element And, the output of which is connected to the first the input element And, the output of which is connected to the input of the delay element and is the first output of the synchronization unit, the input setting to zero of the first trigger and the installation input to the unit of the second trigger are connected to the output of the generator CO. A single pulse, the output of which is the second output of the synchronization unit, the output of the delay element is connected to the counting input of the first trigger, the output of which is the third output of the synchronization unit, the input setting to zero of the second trigger is connected to the input of the synchronization unit, and the output of the second trigger is connected to the second the input element I. 3. The device according to claim 1, which is based on the fact that the k-bit d4;: ai counter contains k pairs of elements And, k elements OR and k flip-flops, the output of the first element And group in i- oh couple

Description

The input of the k-ro element OR group, the second input of which is connected to the output of the second element AND the k-th group pair, and the output of the k-ro element OR group is the controlling output of the k-bit counter, the second inputs of the AND elements of the group are information inputs of a k-bit counter, with the second input of the first, And element in all pairs of a group being the inverse input of a k-bit counter, and the first inputs of the And elements of the first pair of group are connected to the control input of a k-bit counter.

4. The device according to claim 1, characterized in that the address generation unit comprises a group of AND elements and a group of OR elements consisting of k elements each; the outputs of each AND element of the group are connected to the first inputs of the corresponding OR elements of the group whose outputs are outputs the address generation unit, the second inputs of the elements OR groups are the first group of inputs of the address generation unit, the first inputs of the elements AND groups form the second group of inputs of the address formation unit, and the second inputs of the elements AND groups are connected to ravl yuschim input address generating unit.

The invention relates to specialized computer aids and can be applied in digital signal processing systems, in information measurement systems, in devices for generating and analyzing random processes. A device is known for addressing a fast Fourier transform processor containing a counter reconfiguration unit whose output is connected to the control input of the counter, b, the address output terminal, the first information input of which is connected to the output of the counter, and the output to the output of the device. the input of the reconfiguration block of the counter, the first and second, the counting inputs of the counter and the first control input of the issuing block of addresses are connected respectively to the first, second, third and fourth inputs of the block, the output of the counter is connected to the information register input and the first input of the group of elements OR, the output of the register and the output of the group of elements OR are connected respectively to the second and third information inputs of the output unit, the second and third control inputs of which, the control input of the register and the second input of the group of circuits OR are connected respectively the fifth, sixth, seventh, and first inputs of the Cl block. The disadvantage of this device is the complexity of construction and the impossibility of using in a processor with parallel processing of dimensional vector processes. The closest in technical essence to the present invention is a device for resolving the fast Fourier transform processor comprising an address issuing unit, the input of which is connected to the output of the adder and through the information issuing unit to the output of the counter, which is a binary counter with a logic circuit that allows dividing it into two parts, in which the adder is connected to the output of the information input unit in the adder, the output of the counter separation unit is connected to the control inputs of the counter and the information input unit in the adder The information input of which is connected to the output of the counter and the output of the information output unit. The operation of the entire device is synchronized by a block of control pulses and potentials 2. A disadvantage of the known device is the construction complexity: the presence of an adder and a binary counter with a special logic circuit that allows dividing it into two parts, as well as the impossibility of addressing operands when processing n-dimensional vector processes, in addition, the complexity of the readjustment of the device to implement another kind of fast Fourier transform algorithm, for example, decimation in time with an inverse or direct stop Very output data, i.e., small degree of unification of the device. Thus, the main disadvantages of the known devices for addressing the fast Fourier transform processor are the small functionality it is impossible to use the device in the processor for processing n-dimensional vector (processes), the complexity of the structural implementation; small degree of unification.

The purpose of the invention is the expansion of functionality due to the processing of m-migric processes and the simplification of the structure of the device.

The goal is achieved in that the device for addressing the Furbe fast transformation processor containing (m + k) -bit address register, the outputs of which are the outputs of the device, the address generation unit, the first group of inputs of which is connected to the information outputs k-bit one. counter, and the second group of inputs of the shaping unit. The address is connected to the output of the k-bit register. shift, the outputs of which are connected to the information inputs of the k-bit counter, the control input of the register, the first control input of the shift register and the control input of the forming unit. addresses are connected respectively to the first, second and third outputs of the synchronization unit, a t-bit counter is inputted, the input of which is connected to the third output of the synchronization unit, and the information outputs of the t-bit counter are connected to the first g The group of inputs of the address register, the second group of inputs of which is connected to the output of the breathing digit shaping unit, is connected to the control input of the k-bit counter, the control output of which is connected to the second control in the course of the k-bit shift register, and The output k-ro of the SDByga register is connected to the input of the synchronization unit.

Moreover, the synchronization unit contains the first and second triggers, the single pulse generator, the And element, the delay element, the generator of such pulses, the output of which is connected to the first input of the And element, the output of which is connected to the input of the delay element and is. Perwell the output of the synchronization unit, the input setting to zero of the first trigger and the installation input to the unit of the second trigger are connected to the output of the generator of a single pulse, the output | 1. which is the second output., the synchronization unit, the output of the terminal link is connected to the counting input of the first trigger, the output of which is the third output of the synchronization block, the input setting to the zero of the second trigger is connected to the input of the synchronization tree, and the output of the second trigger is connected to the second input element I. f

When etsm k-bit counter contains k pairs of elements AND, k elements OR n k triggers, the output of the first element And group in the 1st pair 1 «« 2, k) is connected to the first input

(il) -ro of the OR element of the group, the second input of which is connected to the output of the second element AND in (1-13th pair of group, and the output (il) -ro of the element T OR is connected to the counting input of the i-th group trigger, output ( i -1) -th group trigger is connected to the first inputs of the And elements in the i-ft pair of the group, the output of the first And element in the first pair of the group is connected

0 by the counting input of the first trigger, and the output of the k-ro trigger of the group is connected to the first input of the k-ro element OR of the group, the second input of which is connected to the output of the second element AND

The 5th k-th group pair and the output of the k-ro element OR group are the control output of the k-bit counter, the second inputs of the AND elements of the group are the information inputs of the k discharge counter, the second

0, the input of the first element AND in all pairs of the group is the inverse input of the k-bit counter, and the first inputs of the elements AND of the first pair of group are connected to the control input k-times5 of the regular counter, the address generation unit contains the group of elements AND and the group OR elements, consisting of k elements each, the outputs of each element AND group are connected to the first inputs of the corresponding OR elements, the outputs of which are the outputs of the address generation unit, the second inputs of the OR elements are the first

5 by a group of inputs of the address generation unit, the first inputs of the AND elements of the group form the second group of inputs of the address generation unit, and the second inputs of the AND elements of the co group

0 are united with the control input of the address generation unit.

FIG. 1 shows a block diagram of an apparatus for addressing a fast Fourier transform processor; in fig. 2 is a block diagram of the synchronization unit; in fig. 3 times a diagram, explaining the principle of operation of the synchronization unit, fig. The 4th is a functional k-bit diagram of the first first counter; on

0 fig. 5 is a functional block diagram of the formation of an address.

The addressing device of the fast Fourier transform processor contains () -address register 1 of ad5, block 2 of the formation of the address, k-bit counter 3, k-bit register 4 of the shift, block 5 of synchronization, a wide-counter counter of 6.

Sync block 5 is intended

0 to generate the necessary sequences of control signals, ensuring the operation of all; device addressing processor fast Fourier transform. The block synchronization (Fig. 2) contains z

5 clock 7 clock pulses, AND element 8, delay element Sf, first trigger 10, second trigger 41, generator 12 of a single pulse. The K-bit first counter 3 with a control transfer chain is intended to prepare the base of the transceiver. Its width is defined as follows: k log2N,. where N-2 is the number of elements in the component X of the input vector, .... xD n is the dimension of the vector process; T is the sign of transportation of the vector, matrix. The K-bit first counter 3 contains (FIG. 4) a group of elements AND 13 of k pairs of elements AND, a group of elements OR 14 of k elements of IL and a group of triggers 15 of k trigger Second second t-bit counter 6 is not circumvented to form address database when processing n-dimensional vector processes, the size m of which is determined according to the expression m EntdogAn) +1. The second m-bit counter B is a binary summing counter with a conversion factor equal to the dimension n of the processed vector process. The address forming unit 2 is assigned to form the addresses of the elements of the processed array in the corresponding basic operations of the fast Fourier transform algorithm, taking into account the bases received in the k-bit first counter 3 and in the shift register 4. The address generation unit 2 (Fig. 5) contains a group of elements AND 16 and a group of elements OR 17 consisting of k elements .-. The address register 1 is designed to fix the address of the elements of the processed vector process in accordance with the basic operations of the fast Fourier transform algorithm. It is a (in + k) -digit information storage register, the k-bit shift register 4 is used for controlling the transfer chains of the k-bit first counter 3. It is a k-bit shift register for one bit, in which there are also chains for storing a specific code into the bits. The fast Fourier transform processor addressing device operates as follows. The signal from the output 2 of the synchronization block in the shift register 4 is entered into code 100 ... 0. This unit, by the signal from the control output of the K-bit first counter 3, is shifted to the right (towards the lower bits) by one after each execution iterations in the fast Fourier transform algorithm. Consequently, at one of the outputs of the k-bit register of the 4th shift, there will be a potential of a unit, which will allow the transfer from (1-1) -th bit to (1 + 1) -th and prohibit the transfer to the t-th bit of k- bit of the first counter 3, i.e. the unit at the 1st output of the k-razp dn; o shift register 4 arrives at the 1st pair of AND elements of the k 13-bit group of the first first counter 3 and prohibits the passage of the transfer unit from (Jl) -ro bit through (1-1 ) -th element OR of group 14 into the 1st digit of the given counter, on the other hand, the potential of the unit at the 1st output of the K-bit register 4 shift allows the passage of this transfer unit through the 1st element OR of group 14 into (+1 ) the th bit of the fc bit of the first counter 3. - It should be noted that the bit of the given counter will be at zero and during the execution of the 1st itera tion not izmenits its state. Here, the number of the 1st bit corresponds to fk - (-1) the iteration number in the fast Fourier transform algorithm. This code in shift register 4 on the k - (-1) -th iteration & execution of the fast Fourier transform algorithm is involved in the formation of the addresses of the operands of the basic operations computed on this iteration: the corresponding components of the vector process. According to the fast Fourier transform algorithm, at each iteration, the basic operations of all components of the x vector (Xv, i.e., the addressing device of the fast Fourier transformation processor must determine: addresses of the operands of the basic operations of the component), ii, H of the X vector, then Xjd are processed; ... X (1). For this block. 5 synchronization produces all sequences of signals TI1 and TIZ (Fig. 2 and 3) on the first and third outputs, respectively. The TIZ signals are formed by halving the frequency of the delayed TI1 signals. This is done with the help of the delay element 9 and the second trigger 11 Time i, and the frequency of the TI cifths is determined based on

The calculation of the baseline operation by the operating automaton of the Fast Fourier Transform Process. According to the FFT algorithm, at each iteration, the addresses of the operands of the base operation Xj of the vector X are determined first, then the coefficients. Xj, .. ,, Chr. Therefore, by the first signal of the TI1 sequence from the first output of synchronization unit 5, the contents of the t-bit counter 6 are recorded in the first m most significant bits of address register 1, and the contents of the k-bit counter 3 are transmitted through the group of elements OR 17 of the address generation unit 2 in the next k bits (m + k) -digit address register. It also determines the address of the first element X of the X component of the vector X in the basic operation. Then, the first TIZ sequence signal is generated from the third output of the synchronization unit 5 to the control input of the address generation unit 2 and allows the transfer of the AND 16 group of elements and the OR 17 group of elements to the k lower informational inputs of the address 1 register k-times. 3 and register 1 and 4 shift. Further, according to algorithm5 (synchronization unit 5 operation (Fig. I 3). A second signal of the TI1 sequence is received from the first output of synchronization unit 5 to up1) avd qvidy input of the address register 1, g at which, the contents of the t-bit counter b, k- bit counter 3 and shift register 4 is recorded. The (m + k) -bit address register. At the same time, as noted above, in the J-th register bit of the 1 address on, Qk - (1-1) -th iteration will write one, so KJK in this bit of the k-bit of the current counter 3 on the daily iteration is always zero. The obtained address in address register 1 defines the second element X, (2 components. X of the vector X in the basic operation hey. On the falling edge of the given signal-5 on the PHIL sequence, a unit will be added to the t-bit counter.

Then, following the next pair of signals from the sequence TI1 to the signal from the V sequence of the SIZ, as described above, the addresses of the elements of the K.2 component of the X sector are formed. Again, the content of the t-bit counter 6 is added one-. tsa on the falling edge of the TIZ sequence signal. Then, the addresses of the elements Xj2 of the X component, the base operation vector, etc. are determined in a similar way. And finally, the addresses of the elements X, and Xo2 are sent.

basic

X components of the vector

operations. On the trailing edge of the TIZ sequence signal, from the third output of synchronization unit 5, one is added to the contents of the t-bit counter 6, the counter overflows because it contains the code

11 4. 1

 at n log22 and on signal

P -

0

overflow of the t-bit counter. a unit is added to the contents of the k-bit counter, (the process then proceeds as described above and is determined

5 addresses of the elements of the components X ,,, X ,, ..., Xp of the vector X of the following butterflies on fk - (E-1) -th iteration.

The overflow signal of the k-bit counter 3 indicates the end of this iteration. It enters the control input of register 4 and shifts the unit stored in it by one bit to the right (in the direction of the least significant bits). Next, the formation of addresses on the next one (k-l) begins in the same way as described above. After the formation of the addresses of the last kth iteration of the overflow signal from the control output

0 k-bit counter 3 shifts the contents, register 4, by a signal from which the unit is pushed out of the register, arrives at the input of the synchronization unit 5 and sets the first trigger 11 to zero,

5 that will provide zero potential at the input of the element And 8, and this will prohibit the formation of sequences of signals TI1 and TIZ. This ends one cycle of operation of the device for transmitting the fast Fourier transform processor, and the device is ready for operation with new initial data, with the new xJ vector.

five

i

Thus, using this approach to implement the addressing device of the Fast Fourier Transform Processor, it is possible to carry out the processing of n-dimensional

0 vector processes, which is especially important when constructing digital control systems for spatial-multidimensional random vibrations, and it is possible to construct matrix processors for processing n-dimensional vector processes.

In addition, the device is distinguished by the simplicity of its technical implementation (the absence of an adder, a counter with a special separation scheme).

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Claims (4)

1. DEVICE FOR ADDRESSING A FOURIER FAST TRANSFORMING PROCESSOR, containing (m + k) -bit _; an address register, the outputs of which are device outputs, an address generation unit, the first group of inputs of which is connected to the information outputs of the k-bit counter, and the second group of inputs of the address generation unit is connected to the output of the k-bit shift register, the outputs of which are connected to information inputs k -digit counter, controlling the input of the hell register; Resa, the first control input register. the shift pa and the control input of the address generation unit are connected respectively to the first, second and third outputs of the synchronization unit, characterized in ^; that, in order to expand its functionality by processing η dimensional processes and simplifying the circuit, an m-bit counter is introduced into it, the input of which is connected to the third output of the synchronization block, and the information outputs of the m-bit counter are connected to the first group of inputs of the address register, the second group of inputs of which is connected to the outputs of the address generation unit, the output of the mth discharge is connected to the control input of the k-bit counter, the control output of which is connected to the second control input of the k-bit pa shift, and the output of the kth shift register ^{with an} input coupled to the discharge sync block. 2. The device according to π. 1, on t l ichayuscheesya _in that the synchronization unit comprises first and second flip-flops, the generator single pulse, AND gate, a delay element, a clock generator, whose output is connected to a first input AND gate whose output is connected to a first input of AND, the output of which is connected to the input of the delay element and is the first output of the synchronization unit, the input of the zero setting of the first trigger and the installation input of the second trigger unit are connected to the output of the single pulse generator, the output of which is second output synchronization unit delay element output coupled to an input of a first counting trigger, the output of which is the third output of the synchronization block, zero setting input of the second flip-flop is connected to an input of the synchronization unit and the output of the second flip-flop coupled to a second input of the I. 3. The device pop. 1, characterized in that the k-bit counter contains k pairs of AND elements, k OR elements, and triggers, the output of the first AND element in the i-th pair (i = 2, k) is connected to the first input (il) -ro of the element OR group, the second input of which is connected to the output of the second AND element in the (il) -oft group pair, and the output of (il) -ro of the OR group element is connected to the counting input of the i-ro group trigger, the output of (il) -ro group trigger connected to the first inputs of AND elements in the i-th pair of the group, the output of the first AND element in the first pair of the group is connected to the counting input of the first trigger, and the output o trigger group connected to lane SU, 1040491 by the input of the kth OR element of the group, the second input of which is connected to the output of the second AND element of the kth pair of the group, and the output of the kth OR element of the group is the control output of the k-row counter, the second inputs of the AND elements are information inputs of a k-bit counter, with the second input of the first. The AND element in all pairs of the group is the inverse input of the k-bit counter, and the first inputs of the AND elements of the first pair of the group are connected to the control input of the k-bit counter. 4. The device according to π. 1, characterized in that the address forming unit comprises a group of AND elements and a group of OR elements consisting of k elements each, the outputs of each AND element are connected to the first inputs of the corresponding OR elements of the group, the outputs of which are outputs of the address forming unit, the second input elements OR groups are the first group of inputs of the address generation unit, the first inputs of AND elements form the second group of inputs of the address generation unit, and the second inputs of AND elements are connected to the control input m block address formation.