SU1023325A1 - Pseudorandom sequence generator - Google Patents

Abstract

.GENERATOR OF PSEUDICAL EMERGING SEQUENCES, containing a clock pulse generator, the output of which is connected to the first inputs of the first and second elements. The BAN and with the third input of the second element BANCH, the shift register, the inverse outputs of all bits of which, except ne: rvogo and the last, are connected to the corresponding inputs of the decoder, and the direct outputs of all the bits of the shift register are connected respectively to the first inputs of the AND elements of the group, the second inputs of which are a group of inputs of the generator, and the outputs of the elements AND of the group are connected to the corresponding inputs of the modulator two, characterized in that, in order to simplify the generator It contains the element Л, the element OR, the display unit and the generator of a single pulse, the output of which is connected to the first input of the element OR, the second input of which is connected to the output of the first element BAN, and the output of the element OR The one is connected to the input of the displacement of the registrar, the information input of which is connected to the output of the element I, the first input of which is combined with the input of the display unit and connected to the output of the counter, the output of the modulator is connected to the second input of the house The element And is the output | generator. .. fj

Description

The invention relates to computational (tion engineering and can be used as a device for determining the topology of bonding multi-input adder of modulo two, the output of which are formed shifted copies of the pseudorandom sequences. The use of shifted copies of the pseudorandom posledovateljnoctey allows to construct economical pseudorandom number generators, and to organize autonomous devices for simulating random processes with specified characteristics. Iz. a pseudo-random generator is known. The village contains a shift register with an absolute modulo two in the feedback circuit 11. A disadvantage of this device is the impossibility of obtaining a COPY pseudo-random sequence of shifted more than by L-cycles, where Yn is a shift of the shift register .-.. Known a parallel pseudo-random number generator, which allows you to get copies of a pseudo-random sequence shifted by much more than a number of cycles 2. However, this device allows you to get accumulated pseudo-random sequence only once l for the particular case when the feedback circuit. The register of the shift is from only one half-adder. The closest to the proposed invention is a device for generating shifted copies of a pseudo-random signal, consisting of a clock generator, a first BAN element, a shift register with feedback, a decoder, a second BAN element, a counter, bgame memory, modulators two and indicators / Sz. The use of a device for generating shifted copies of a pseudo-random signal allows to determine the modularity of the VYI-RUNNING SUMMIN connection topology, at the output of which a copy of the original pseudo-random m-sequence is obtained, shifted by an arbitrary number. cycles. Moreover, in this device, this problem is solved for the general case. for the case when the multiple-modulo two-parameter adder is included in the feedback circuit of the shift register. The disadvantage of this device is the complexity of instrumentation, which is mainly determined by the presence of 4w-О (-l) f i l L-5ni КН, memory elements. Even for a relatively small value of 20, the additional number of memory elements will be 171 elements, which is almost 7 times more, and the equipment costs going to other units of the device. In addition, the presence of memory blocks reduces the speed of the device as a whole. This is due to the fact that in this case, time is needed for writing and reading information on the memory block. The purpose of the invention is to reduce hardware costs H-- building a device for obtaining shifted pseudo-random sequence sequences, i.e. generator simplification. The goal is achieved by the fact that a pseudo-random sequence generator containing a clock pulse generator whose output is connected to the first inputs of the first and second BAN elements, a decoder, the output of which is connected to the second input of the second BANNER element, the output of which is connected to the counter input, the output of which is connected with the second input of the first element BANGE and with the third input of the second element BANGE, the shift register, the inverse outputs of all bits of which, except the first and last, are connected to the corresponding The first inputs of the decoder, and the direct outputs of all the bits of the shift register are connected to the first inputs of the corresponding AND elements of the group, the second inputs of which form a group of inputs of the generator, and the outputs of the group of elements AND are connected to the corresponding inputs of the modulo two, the element I, an OR element, a display unit and a single pulse generator whose output is connected to the first input of the OR element, the second input of which is connected to the output of the first BAN element, and the output of the OR element is connected to the input Shift register A shift whose information input is connected to the output of the element I, the first input of which is combined with the input of the display unit and connected to the output of the counter, the output of the modulo-two is connected to the second input of the element AND and is the generator output. FIG. 1 shows a block diagram of the generator j in FIG. 2 is a generator diagram for case U 5; FIG. 3 diagram, explaining his work. The pseudo-random sequence generator consists of a generator of 1 clock pulses, the first element BANKS 2, a shift register 3 with modulo two in the feedback circuit, 2-input elements AND, a decoder 4, B 5 non-input element, counter b, a two-input element and, a two-input element OR B, a generator of 9 single pulses and an indication element 10. The clock generator, pulses 1, the second element PROHIBIT 5, 1 sensor 6 and the first element BANNER 2 are connected in series to the second inputs of the first and second elements BAN 2 and the outputs of the clock pulse generator 1 and counter b, respectively, are connected to the third input of the EAPRET element 5, the output of the decoder 4 is connected, to the inputs of which the unit output of the first bit and zero outputs of the remaining bits of the shift register 3 are connected, to the BTFM inputs - t-two-input elements And feedback registers of the 3 shift register are connected to single outputs and bits of the 3 shift register, and second coefficients are supplied with constant coefficients, outputs w of two-amp & ampy elements AND feedback registers of the 3 shift connected to the inputs of the W-input adder, two feedback circuits of the 3-shift register, whose output and the output of the counter 6 are connected to the inputs of the two input element I 7, whose output is connected to the information zx at the first digit of the 3-shift / a register The generator 9 of the single pulse and the first BANCH element are connected to the inputs of the two-input element OR..8, the output of which is connected to the synchronous bits of the shift register 3, and the output of C4eT4Kka b is connected to the input of the display element 10. The element BANGE2, like block 7, is a two-input element. And (Fig. 2). The clock pulse generator 1 is designed according to a negative feedback circuit (Current coupling. De-4 and two-input element OR 8 are standard m-input element AND and two-input element CLI (FIG. 2), additionally, the ch-input modulo adder The two and 1-two-input elements And in the circuit, the feedback of register 3 (Fig. 2) are also standard elements of computing technology. The second element, BAN 5 (Fig. 2), consists of Y-trigger of the two-input element And and the inverter which are also typical elements, block 10 An element is an ILI-NOT with an indicator, a light bulb (Fig. 2), the values of the coefficients 4 in O, 1 j, i 1, n, are determined by the HPA of the known tables. So, for the case of vn 4, they can in particular cases take The following values i 1, 11 1, oi4 0, 1. The device operates as follows: From the generator 1, the clock pulse through the element BANGE 2 and block 8 goes to the synchronous inputs of the shift and 3 shift, which generates a pseudo-random sequence. At the moment when the combination 100 ... O is stored in the shift register cells 3, i.e. the first trigger is in the single state, and all the others are in the zero state, the decoder 4 generates an enable signal for the second block BANCH 5. This is achieved by the decoder 4 representing the flue of the ' input element I, the first input of which is connected the output of the first bit of the register is 3 shift, and to the remaining (vn-l) inputs, the inverse outputs of the ostashvihs of the bits of the shift register. After the BAN 5 is triggered, the clock pulses; Oscillator 1 is fed to the input of counter B, to which the code of the number -.6 is set before starting, where is the width of the shift register 3, and 8 is the number of cycles to receive the shifted sequence. At the time when counter 6 stores the code, i.e. after 8-1 clocks, the output of the counter b generates a signal prohibiting the passage of counting pulses through element 5 and element 2. At the same time, the same output signal blocks the passage of information, for the first discharge of shift register 3 through the two-input element And 7 and the element 10 indications. Upon ignition of the display unit label, the operator concludes that the information stored on the shift register is the value of the tH-sequence symbols in 8-1 cycles. After that, the output of the device, i.e. at the output of the modulo two adder feedback circuit of the shift register 3, the double digit value 1 (0) 1o, 1 is fixed to t (0) (C-1) OL C), where Qi (e-iy is the contents of the G-th the bit of the shift register is 6-1 clock cycles, and the sign of TL means the modulo-sum operation. Determining the value of the symbol: b (0), the contents of the shift register is shifted by one bit by closing the contact of the generator 9 clock pulses, from the output of which a single pulse through the element OR 8 goes to the input of the shift register 3. At the same time, for the first register bit and the value zero is written. After the information stored in the register is shifted by one bit, the value of the digit t (l) is equal to t (i) "a, ()) a, (e ;. (2), After the next contact of the generator of 9 single pulses, the value of b (2) has the form ССЧ «QI () f, H) ai (, (1) оЛе). (3 and in the general case for the j-th siaMJhani contact of the generator of single pulses 9 we obtain at the output of the modulo two adder, included in the feedback circuit of the shift register 3, the value of b (j), defined according to {), where Sv io, wl} is the number of pulses generated by generator 9; a (i) 6 0.1J - the contents of the first bit of register 3 shift. Ci) -. | .Oi, -Oi..j (ci) "a, () ®io, (4) a, (during the first (vn-l) device operation cycles. Value of coefficients сГ; (b) 6 0 , 1, Vi 1, VM, defining topoes (Modulo two modulus of multi-input adder, are a solution to the following system of equations a, e) a, io) 5i (e; ®aa (o) 6; j, te ) ® ... ®a “co) 5;, (e); a, ten) -ai (i) bde) ® a Do) yg (e) ® - ©. (o; b, „(.ai (e + rti-H))) ® ...) 5m (e; 4 (5). Under the initial conditions 0 (0) 1 and 0 (0) O, i 2, the mind, which correspond to the initial conditions of operation of the proposed device, the system of logical equations (5) will take the following form a, se) bde ), adena) a 0) di (e e6ate), ae vyi-i) - Q (vn-i) 5i (e) © - Fa (o) bp, (e), (b) | The solution of system (6) is expression (7)) a, (, (") a (e -i-yi). N) The value of b (j) is equal to the value b;,. / ((C), which follows from the identity of equations C) and (7). Thus, by sequentially processing the contacts of the generator 9 single pulses at the output of the adder modulo two, included in the feedback circuit of the shift register 3, the values of Coefficients cCi (6) are determined, which determine the topology of the modulo adder two, by the output of which is obtained by a sequence shifted by e clock cycles. Example. FIG. 2 shows a functional diagram of the proposed device with g 5 for the case when et l, (jL 1, c 1,. About Ol5 1. Suppose it is required to determine the topology of the connections of a multi-input adder, the output of which is shifted by C 9 clock cycles of the original Y - sequence. Preliminarily, the code number 2-9 23 is written to the binary counter B. Shift pulses from block 1 are fed to the trigger inputs of register 3 triggers through the AND 2 element and the OR 8 element. At the time when the 10000 combination decoder is stored in the shift register 3 cells 4 produces single th enabling signal, which sets the trigger of ELEMENT 5 in one state and, thus, allows the pulses from the generator 1 of clock pulses to pass through the element AND ELEMENT 5 to the input of counter 6. After eight subsequent cycles of operation of the device as a whole on the counter 6, the code of the number 31 is stored, i.e. all the trigger of the counter b are in the zero state. The signal generated at the output of the counter b prohibits the passage of the contact pulses through the ELEMENT 5 and the ELEMENT 2. At the same time, the same signal is blocked. information is transmitted to the nep-i bit of the shift register 3 through i the two-input element And 7 and the indication lamp of the block 10 is turned on. At the moment, the binary code of 11001 is fixed on the shift resistor 3. the shift register 3, the value of the first coefficient & 1 (9) 1 is formed. After the value of Gb (9) is fixed, the contents of the shift register are shifted by one bit by e-pulse of the generator 9 single pulse output, from which a single pulse through the element t OR 8 is fed to the shift register sync inputs. As a result, code 01100 is stored on shift register i and, accordingly, at the output of the modulo-two adder, C; j. (9) "0. After the second shift in the shift register, we have code 00110 and at the output of an adder modulo two (9) 1. After the third and fourth shift at the register, we have 00011 and 00001 and at the output of the adder according to the-module two, respectively 64 (9), 0 ( E) 1. Thus, the coefficients that determine the topology of the connections of the multi-input adder modulo two, the output of which is shifted by 9Tacts. The vn-follower-Partition has a striking appearance (J (9) li

a (9) 0.04 (9) 1.64 (9) 1,% (9) 1. In FIG. Figure 3 shows the temporal direction 4ma of the sequences at the output of the modulator two modulator; the topology of the connections is determined by the coefficients ((9) and INITIAL t-sequential).

As can be seen from FIG. 3, the source and the transmitted sequences are shifted by nine cycles.

The advantages of the proposed pseudo-random pseudo-random sequence generator in the order / VM

Pre:: The pseudo random cyoecTBeHHO pseudo-random generator reduces hardware costs, and the absence of memory elements. So for P) - 20, you would need to use -171 memory elements, which is

No. "one

seven times the cost of equipment going to other units of the device. Optional equipment is a very small amount. For any w, it consists of one two-input element AND, one two-input element OR, one single-input element OR, one single-input element ILINE, three resistances, capacitance and indicator light. The application of the proposed generator 3: pseudo case sequences, characterized by reduced hardware costs, allows you to build highly reliable, stable and high-quality pseudo-frequency generators, and thereby increase the accuracy and accuracy of problem solving using the Monte Carlo method.

Claims (1)

Pseudo-random sequence generator, comprising a clock pulse generator, the output of which is connected to the first inputs of the first and second elements FORBID, a decoder, the output of which is connected to the second input of the second element and a FORBID, the output of which is connected to the input of the counter, the output of which is connected to the second input of the first element FORBID and with the third input of the second, the second element is FORBID, the shift register, the inverse outputs of all bits of which, except the first and last, are connected to the corresponding input. the decoder, and the direct outputs of all bits of the shift register are connected respectively to the first inputs of the elements AND groups, the second inputs of which are a group of inputs of the generator, and the outputs of the elements and groups are connected to the corresponding inputs of the adder modulo two, characterized in that, in order to simplify the generator , it contains an element L, an OR element, an indication unit and a single pulse generator, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the first element BAN, and the output element OR connected to the input shift registers of shift ra, an information input of which is connected to the output of AND gate, a first input of which is combined with the input display unit and connected to the output of the counter at modulyu'dva adder output is connected to the second input of the AND output is the 'generator Fi »/