SG115429A1 - Stackable semiconductor package and wafer level fabrication method - Google Patents

Stackable semiconductor package and wafer level fabrication method

Info

Publication number
SG115429A1
SG115429A1 SG200107175A SG200107175A SG115429A1 SG 115429 A1 SG115429 A1 SG 115429A1 SG 200107175 A SG200107175 A SG 200107175A SG 200107175 A SG200107175 A SG 200107175A SG 115429 A1 SG115429 A1 SG 115429A1
Authority
SG
Singapore
Prior art keywords
semiconductor package
fabrication method
wafer level
stackable semiconductor
level fabrication
Prior art date
Application number
SG200107175A
Inventor
Yong Poo Chia
Suan Jeung Boon
Siu Waf Low
Min Yu Chan
Yong Loo Neo
Swee Kwang Chua
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to SG200107175A priority Critical patent/SG115429A1/en
Publication of SG115429A1 publication Critical patent/SG115429A1/en

Links

SG200107175A 2001-11-16 2001-11-16 Stackable semiconductor package and wafer level fabrication method SG115429A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG200107175A SG115429A1 (en) 2001-11-16 2001-11-16 Stackable semiconductor package and wafer level fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200107175A SG115429A1 (en) 2001-11-16 2001-11-16 Stackable semiconductor package and wafer level fabrication method

Publications (1)

Publication Number Publication Date
SG115429A1 true SG115429A1 (en) 2005-10-28

Family

ID=35453597

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200107175A SG115429A1 (en) 2001-11-16 2001-11-16 Stackable semiconductor package and wafer level fabrication method

Country Status (1)

Country Link
SG (1) SG115429A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6271060B1 (en) * 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6271060B1 (en) * 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device

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