SG11201805489YA - Memory device, and data processing method based on multi-layer rram crossbar array - Google Patents

Memory device, and data processing method based on multi-layer rram crossbar array

Info

Publication number
SG11201805489YA
SG11201805489YA SG11201805489YA SG11201805489YA SG11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA
Authority
SG
Singapore
Prior art keywords
crossbar array
memory device
rram crossbar
data processing
processing method
Prior art date
Application number
SG11201805489YA
Inventor
Hao Yu
Yuhao Wang
Junfeng Zhao
Wei Yang
Shihai Xiao
Leibin Ni
Original Assignee
Huawei Tech Co Ltd
Univ Nanyang Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Tech Co Ltd, Univ Nanyang Tech filed Critical Huawei Tech Co Ltd
Publication of SG11201805489YA publication Critical patent/SG11201805489YA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

MEMORY DEVICE, AND DATA PROCESSING METHOD BASED ON MULTI-LAYER RRAM CROSSBAR ARRAY Embodiments of the present invention provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of 5 resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a Boolean value 1 or 0. Based on the foregoing setting, a Boolean operation is implemented by using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved. Fig. 5 10
SG11201805489YA 2016-01-18 2016-01-18 Memory device, and data processing method based on multi-layer rram crossbar array SG11201805489YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/071254 WO2017124237A1 (en) 2016-01-18 2016-01-18 Memory device and data-processing method based on multi-layer rram crossbar array

Publications (1)

Publication Number Publication Date
SG11201805489YA true SG11201805489YA (en) 2018-07-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201805489YA SG11201805489YA (en) 2016-01-18 2016-01-18 Memory device, and data processing method based on multi-layer rram crossbar array

Country Status (6)

Country Link
US (1) US10459724B2 (en)
EP (1) EP3389051B1 (en)
JP (1) JP6702596B2 (en)
CN (1) CN108475522B (en)
SG (1) SG11201805489YA (en)
WO (1) WO2017124237A1 (en)

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Publication number Publication date
CN108475522A (en) 2018-08-31
EP3389051B1 (en) 2020-09-09
WO2017124237A1 (en) 2017-07-27
CN108475522B (en) 2020-12-15
JP6702596B2 (en) 2020-06-03
EP3389051A1 (en) 2018-10-17
JP2019502225A (en) 2019-01-24
EP3389051A4 (en) 2019-01-09
US10459724B2 (en) 2019-10-29
US20180321942A1 (en) 2018-11-08

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