RU92275U1 - DATA TRANSMISSION DEVICE - Google Patents

Abstract

A device for transmitting data, characterized in that it is a connection of logic elements or contact relay circuits of logic elements for encoding binary information and its transmission, and contains two channels of signal transmission identical in design, one of which is made with input and output for transmission a signal equal to a logical “0”, and the other with an input and an output for transmitting a signal equal to a logical “1”, at least one logical element or contact-relay circuit of a logic element, performed by passing a signal equal to a logical “0” or “1”, with the possibility of transmitting a control signal to the input of an adjacent channel or to the output of an adjacent channel to block the signal from passing through this adjacent channel until the signal is in another channel and unlock this adjacent channel in the absence of a signal in another channel.

Description

The utility model relates to the field of computer technology and can be used as equipment for switching systems for transmitting digital data in communication networks.

Known devices for the temporary integration and separation of digital signals (Levin L.S. Plotkin M.A. Digital transmission systems. M. Radio and communications, 1982; Inose X. Integrated digital communications networks. Introduction to theory and practice. M. Radio and communications , 1982).

It is also known a device for asynchronous sealing of communication channels using time separation of signals (SU No. 479138), containing at the transmitting station a recording allocator, m recording memory cells, a phase comparator, command generator, m read cells, an OR circuit, a group synchronization transmitter, a change unit recording sequences and a Staffing time position allocation unit, and at the receiving station m recording cells, m reading cells, a reading distributor, an OR circuit, a phase locked loop, eshifrator commands, group synchronization receiver unit changing the sequence of reading and time slot allocation unit stuffing.

Known devices for the temporary combining and separation of digital signals have a constant structure of the transmission cycle, a fixed sequence of channel intervals with character or group combining. The hierarchy of speeds of the combined digital signals is also fixed and each clock interval of the transmission cycle is rigidly assigned to the corresponding channel interval.

When transmitting digital signals whose speeds differ from the speeds of digital channels, the efficiency of using a group digital path is significantly reduced. This is due to the fact that it is necessary to use additional interface devices that ensure the combination of incoming digital signals, if their speed is less than the speed of digital channels, or the combination of digital channels, if the speed of incoming signals is greater than the transmission speed provided by these channels. In known devices, as a rule, multistage combining (separation) of digital signals with different speeds is used.

Also known is a digital signal multiplexer / concentrator device (US No. 3959595), selected as a prototype, in which matching blocks for the number of digital channels are included between the group digital signal generator and the terminal devices, each of which consists of two identical parts A and B containing shift register (drive), a counter of the number of information signals (pulses) received from the source during the group signal transmission cycle, a decoder, an overhead information transmitter, a value reduction register in, AND and OR elements, operating under the influence of a control device common to all coordination units.

The information symbols of the source signal are recorded during the transmission cycle T _c (i), for example, into zone A, and during the same cycle, information symbols from zone B are read that were recorded there during the previous cycle TC (i-1) . Simultaneously with the recording of information symbols in the shift register, the counter of the number of information symbols calculates them. The calculation result is encoded in binary code and transmitted in the area of service codograms of the transmission cycle.

The described device (prototype) provides a single-step combination of digital signals with arbitrary transmission rates when the condition F _o F _{n is} fulfilled for all F _n at any moment in time, where F _{n is the} number of information bits of the nth source signal arriving for the group signal transmission cycle; F _{0 the} number of clock intervals (bits) of the transmission cycle, which are allocated for the organization of digital channels.

The disadvantages of this device are the fixed structure of the transmission cycle, i.e. a constant number of organized channel intervals, as well as the presence of service codograms in each transmission cycle of the zone, which leads to a decrease in the efficiency of using a group digital path and a decrease in noise immunity. In addition, the system is a complex structure and does not allow its modernization and expansion when changing the schedule or tasks.

The proposed utility model is aimed at achieving a technical result, which consists in simplifying the design of the digital data transmission unit while expanding the functionality expressed in expandability and performing the function of a multiplexer in digital hierarchy networks with a linear, ring, star-shaped and mixed structure.

The specified technical result is achieved in that the device for transmitting data is characterized by the fact that it is a combination of logic elements or contact relay circuits of logic elements for encoding binary information and its transmission, and contains two channels of signal transmission identical in design, one of which is made with an input and an output for transmitting a voltage signal equal to a logical “0”, and another with an input and output for transmitting a voltage signal equal to a logical “1”, while each channel, at least one logic element or contact-relay circuit of the logic element is made when the voltage signal is equal to a logical "0" or "1" with the possibility of transmission to the input of an adjacent channel or to the output of an adjacent channel of the control signal to block this adjacent channel until a voltage signal is present in another channel and this adjacent channel is unlocked in the absence of a voltage signal in another channel.

These features are significant and are interconnected with the formation of a stable set of essential features sufficient to obtain the desired technical result.

Figure 1 presents a diagram of a data transmission unit indicating inputs and outputs;

figure 2 - data transmission unit in a state of readiness to receive a bit;

figure 3 - data transmission unit in the state of the signal (voltage) from the "device 1" to input A;

4 is a data transmission unit in a state of fixation of a signal, sending it further to contact C of "device 2" and sending acknowledgment of receipt to contact B of "device 1".

5 is a data transmission unit in a state of stopping the transmission of a signal after sending a confirmation to B, "device 1" stops the transmission (option "a")

6 - data transmission unit: the contact D from the "device 2" receives confirmation of the receipt of a signal from C, (option "b") ;.

Fig.7 - data transmission unit: after sending a confirmation to B, "device 1" stops the transmission of the signal to A. At the same time, contact D from "device 2" receives confirmation of the signal from C.

Fig. 8 shows a data transmission unit in a state of termination of transmission at contacts B and C (in the case when confirmation has arrived at contact D from a “2 m device”);

Fig.9 is an example of execution of a data transmission unit on logical elements;

figure 10 presents an example of the execution of the data transmission unit on the relay;

11 is a data transmission unit in the initial state (for an example of execution on a relay);

Fig.12 is the same as in Fig.11, the first state;

Fig.13 is the same as in Fig.11, the second state;

Fig.14 is the same as in Fig.11, the third state;

Fig - the same as in Fig.11, the fourth state;

Fig.16 is the same as in Fig.11, the fifth state;

Fig.17 is the same as in Fig.11, the sixth state;

Fig. 18 is the same as in Fig. 11, the seventh state;

Fig.19 is the same as in Fig.11, the eighth state;

Fig.20 is the same as in Fig.11, the ninth state;

Fig.21 is the same as in Fig.11, the tenth state;

Fig - block data transfer in the initial state (for an example of execution on logical elements);

Fig.23 is the same as in Fig.22, the first state;

Fig.24 is the same as in Fig.22, the second state;

Fig.25 is the same as in Fig.22, the third state;

Fig.26 is the same as in Fig.22, the fourth state;

Fig.27 is the same as in Fig.22, the fifth state;

Fig.28 is the same as in Fig.22, the sixth state;

Fig.29 is the same as in Fig.22, the seventh state;

Fig.30 is the same as in Fig.22, the eighth state;

Fig.31 - the same as in Fig.22, the ninth state

Fig - the same as in Fig.22, the tenth state;

Fig.33 is the same as in Fig.22, the eleventh state.

According to the present utility model, the design of the device 1 for transmitting data (digital) in switching systems is considered. The data transmission device in such a device is based on the effect of natural delays in the operation of switching elements (transistors, optocouplers, relays, etc.). Device 1 is a separate module having two inputs (input A 2 and input B 3) and two outputs (output C 4 and output D 5).

There are various physical methods for encoding binary information, but most often a unit is encoded with a higher voltage level than zero (or vice versa). To represent two logical states “1” and “0” in the valves, the corresponding input and output signals have one of two set voltage levels. For example, +5 volts and 0 volts. In the framework of the claimed utility model, the principle of not generating a voltage level is realized, but a change in the voltage transmission channel, perceived as a signal, and the choice of this signal in relation to “1” or “0” is determined by the voltage transmission channel.

The claimed device 1 implements the transmission of "1" or "0" according to the following algorithm.

When the voltage arrives at input A, the signal means the input is "0", and the voltage input at pin B is received - "1". Accordingly, “0” exits the output contact C, and “1” exits the output contact D.

The scheme itself determines the maximum possible data transfer rate, due to this internal delays of executable elements.

The device diagram is symmetrical, which means that when processing "0" the exact same scheme is used as when processing "1".

Device 1 has 4 states when transmitting "0" and 4 states when transmitting "1"

In the figures. Figure 3-8 shows an example of signal transmission "0" (for signal "1" everything functions the same, only signals come in instead of channel (A-B) on channel (C-D).

0) Device 1 is in a ready state to receive a bit from device 6 and transmit it to device 7 (Fig. 2). Devices 1, 6 and 7 can be made identical in design, the description of which is given in relation to the circuits shown in Fig.9 and 10.

1) The signal (voltage) from device 6 is fed to input A of device 1 (Fig. 3).

2) Device 1 captures the signal, sends it further to the output contact C of device 7 and sends a confirmation of receipt of input B of device 1 to the contact (Fig. 4).

3) Option a: After sending a confirmation to the input to the device 1 stops the transmission of the signal (figure 5).

Option b: On the contact of the output D from the device 7 comes a confirmation of the receipt of a signal from the output C (Fig.6).

Option c: After sending a confirmation to input B, device 1 stops transmitting a signal to input A. At the same time, confirmation of receipt of a signal from output C comes to the output terminal D from device 7 (Fig. 7).

4) After that, the circuit stops the transmission of the contacts of input B and output C (in the case when confirmation came to the contact of output D from device 7) (Fig. 8).

After the device 7 disconnects the signal on the contact of the output D, the device goes into the zero state and is ready to accept the next bit "0" or "1" (figure 2).

Thus, a device for transmitting data according to a utility model is a combination of logic elements or contact relay circuits of logic elements for encoding binary information and its transmission, and contains two channels of signal transmission identical in design, one of which is made with input and output for transmission a voltage signal equal to a logical “0”, and the other with an input and output for transmitting a voltage signal equal to a logical “1”, with at least m one logical element or contact-relay circuit of the logical element, performed when the voltage signal is equal to logical “0” or “1” with the possibility of transmitting the control signal to the input of the adjacent channel or to the output of the adjacent channel to block the passage of the voltage signal through this adjacent channel to the moment of the presence of a voltage signal in another channel and the unlocking of this adjacent channel in the absence of a voltage signal in another channel.

This principle of implementing binary codes “1” and “2” can be implemented on logic or relay construction of circuits described below.

Figure 9 presents a diagram of a device 1 for transmitting data, performed on the logical elements of the type AND, OR, NOT, AND-NOT, OR-NOT.

The device of FIG. 9 is made with two channels A-C and B-D identical in design. Channel A-C consists of input A 2, to which the first logical element AND (AND-NOT) 8 is connected with the first input, the first logical element is NOT 9, the output of which is connected to the first input of the second AND gate (AND-NOT) 10, the output of which connected to the first input of the first logical element OR (OR-NOT) 11.

the output of which is connected to the second input of the second AND element (AND-NOT) 10. The second logical element OR (OR-NOT) 12 by the first input is connected to the output of the first logical element AND (AND-NOT) 8, and the second input is connected to output В 4 and the second input of the first logical element OR (OR-NOT) 11. The second logical element NOT 13 is connected by its input to the input А 2, and by the output to the input of the third logical element AND (AND-NOT) 14. whose output is connected to the input of the first logical element 9. Channel BD is similar to channel A-C, where instead of input A there is input B, and instead of output C, output D. Between the channels there are the following connections. The second input of the logical element OR (OR-NOT) 12 through a diode is connected to input B. With output C and with the output of the second element AND (NAND) 10. Other communications determine the operability of the circuit of device 1.

Figure 10 presents a diagram of a device 1 for transmitting data made on a relay (solid state relays, optocouplers and all other types of relays). Logic elements are replaced by contact-relay circuits of logic elements, the operation algorithm of which with normally closed contacts is as follows: in the absence of electric current through the relay winding, the relay contacts are closed, and when sufficient current flows through the relay winding, the relay contacts are open.

In channel A-C, input A 2 is connected to the contacts of the first relay 15 and the winding of the second relay 16, the contacts of which are connected to the output D. The contacts of the first relay 15 are connected via diodes to the winding of the third relay 17, which is also connected to the winding of a similar relay in the channel Bd. The contacts of the second relay 16 are connected to the winding of the fourth relay 18, which is also connected to the winding of a similar relay in channel B-D. Output C 4 is connected to the contacts of the fourth relay 18, the winding of the third relay 17 and input B 3. The windings of the same channel relays are interconnected.

Below is an example of the operation of a data transmission device (figure 10), built on a relay.

1. The device expects a signal (voltage level sufficient for the relay to operate) at inputs A 1 ("zero") or B 3 ("unit") (Fig. 11).

2. At the input A 1 received a signal ("zero") (Fig.12). Normally open relay 15, when a signal passes through it, a delay occurs (with the exception of mechanical relays), relay 15 performs the function of blocking the signal from entering the memory group (relays 17 and 18), in this case relay 15 is open. Relay 16 is switched to block the signal flow (in advance) from output D.

3. Next, the first element of the memory group (relays 17 and 18) of the relay 17 is turned on (Fig.13). The part of the circuit that is responsible for transmitting the “unit” using relay 19 of the B-D channel is blocked. Relay 17 of channel A-C and relay 20 of channel B-D in this circuit are needed only to amplify the signal.

4. The signal passes through the relay 18 (Fig.14)

5. After triggering a memory group (relays 17 and 18), the amplified signal goes to input B and output C (Fig. 15). A signal to input B is necessary to confirm receipt of "zero". The signal to exit C is necessary to transmit further than "zero". Relay 16 is closed. The operation of the relay 21 does not matter at all when processing "zero".

6. At the input A, the signal ceases to be received, because the device that sent the signal to A received a return confirmation signal from input B (Fig. 16). A confirmation signal is input to input D from the device to which “zero” was sent to output C. Relay 16 opens due to the lack of a signal at input A, so the signal from output D is prepared to go to the memory group (relays 17 and 18) for reset.

7. Relay 18 is turned on, thereby resetting the memory group (relays 17 and 18) (Fig. 17).

8. From input B and output C, the signal ceases to go (Fig. 18). For the previous device, this means that the circuit of the device 1 is ready to receive the next signal "zero" (input A) or "unit" (input B). For later, this means that the signal is delivered. Relay 19 opens, prepares to receive a “unit” (if it arrives at input B), relay 17 closes.

9. From the output D, the signal ceases to arrive (Fig. 19). This means that the next device is ready to receive the next signal ("zero" or "unit").

10. The relay 18 is reset, thereby completing the reset of the memory group (relay 17 and 16) (Fig.20).

11. The device circuit has been reset and is ready to receive the next signal "zero" (at input A) or "unit" at (at input B) (Fig. 21).

The following is an example of the operation of a data transmission unit built on logic elements.

1. The waiting state. At all inputs of the logic elements there is no voltage equal to 0 (Fig.22). The device circuit is waiting for input A or B to receive voltage sufficient for the logic elements (e1, e6, e7, e4) to work as a logical unit. If the signal (logical unit) arrives at input A, then it will be considered that “zero” has arrived. If the signal (logical unit) arrives at input B, then it will be considered that a "unit" has arrived.

2. The signal was received at input A (Fig.23). This means that rides "zero". e1 and e6 entered a transition state. After a natural delay, e1 and e6 will work, e1 serves to receive or cut off the signal for memorization by a group of elements (e5, e9, e13). Together, e6 and e10 serve to block the signal from output D.

3. After the operation of e1, the signal (logical unit) is supplied to e13 and e2 (Fig.24). E13 acts as a combiner. After operation, the signal is remembered.

4. e9 after operation will loop the signal (e9, e13), thereby remembering it (Fig.25). After operation, e2 closes the signal through e4 from input B to the storage part (“units”) of the circuit (e8, e12, e14).

5. The signal from e9 goes to outputs C and B (Fig. 26) and to e4, which will not pass the signal further, because e4 was previously blocked by a logic zero. After that, the operation of e7 and e11 does not matter what.

6. The signal that went to B, to the device from which the signal came to A (T1) (Fig.27). This device received a signal from input B and turned off the voltage to input A, thereby confirming the fact of transmission of "zero". In turn, the operation of e1 will disable the signal to the memory group (e5, e9, e13).

7. The device to which "zero" was sent via output C, in confirmation that it received it, responded to input D (Fig. 28). After triggering e6, e10 opens to reset the memory group (e5, e9, e13).

8. After e10, the signal arrives at e5 to reset the memory group "zero" (e5, e9, e13) (Fig.29).

9. After e5, the logical zero overlaps e9 (Fig.30).

10. After e9, the signal stops at C and B (Fig.31).

11. e2 unlocks the "single" part of the circuit (e4) (Fig. 32).

12. The circuit is ready to receive the next signal “zero” to input A or “unit” to input B.

To send a “unit”, the above description is also true, but instead of:

e1-e4, e5-e8, e9-e12, e13-e14, e2-e3, e6-e7, e10-e11. The circuit is symmetrical (Fig. 33).

This utility model is industrially applicable, can be implemented on the basis of logic elements or contact-relay type elements, which are widely produced by the electronics industry. The utility model allows to implement a new principle of computer construction with an unlimitedly wide architecture of construction.

Claims (1)

A device for transmitting data, characterized in that it is a connection of logic elements or contact relay circuits of logic elements for encoding binary information and its transmission, and contains two channels of signal transmission identical in design, one of which is made with input and output for transmission a signal equal to a logical “0”, and the other with an input and an output for transmitting a signal equal to a logical “1”, at least one logical element or contact-relay circuit of a logic element, performed by passing a signal equal to a logical “0” or “1”, with the possibility of transmitting a control signal to the input of an adjacent channel or to the output of an adjacent channel to block the signal from passing through this adjacent channel until the signal is in another channel and unlock this adjacent channel in the absence of a signal in another channel.