RU6252U1 - GENERATOR OF SEQUENCES OF DIGITAL NUMBERS - Google Patents

Abstract

A generator of sequences of weights of bits of redundant numbers with arbitrary initial conditions, containing r + p sequentially connected at the information inputs of registers from the first to (r + p) th, the adder of the weights of the basic sequence, a switch, a ban element, a trigger with a counting input, an OR element, element And, a synchronization and control unit, wherein the first information input of the first register is an input for setting the initial conditions of the generator, the output of the first register is connected to the first information input of the adder weight in the basic sequence, and the adder output is connected to the second information input of the first register, the synchronization input of which is combined with the synchronization input of the remaining registers and connected to the first output of the synchronization and control unit, the input of which is connected to the "Start" input of the generator, the outputs of the registers from the second to ( r - 1) th and the output of the (r + p) th register are connected to the corresponding inputs of the group of information inputs of the switch, the second synchronization input of which is connected to the second output of the synchronization and control unit, t the output of which is connected to the first synchronization input of the switch, the information output of which is connected to the second information input of the adder of the base sequence weights, the third synchronization input of the switch is combined with the first input of the OR element and connected to the output of the inhibit element, the direct input of which is connected to the second output of the synchronization unit and control, the inverse input of the inhibit element is combined with the direct output of the trigger with a counting input, the counting input of which is connected to the output of the And element, the first input

Description

Theoretical research relates to computer technology and can be used to obtain series of multivalued numbers ordered by value, used to scan zones of vibration intensity during the on-line diagnostics of turbine units.It is necessary to generate sequences of multivalued numbers when approximating non-linear distribution laws for studying physical quantities (n. For example, the levels of vibration dampers of rotor harmonics of turbomachines), as well as in the construction of specialized th devices, I work with larger (more than two) bases 13,

Known generator / 2 / sequences of numbers., Contained sh-P + 1 series-connected registers on which the formation of p-numbers. The disadvantage of such a generator of sequences of numbers is limited functionality.

The closest to the proposed / technical solution in terms of technical nature and the achievable eODect is a sequence generator of numbers, containing rn series-connected via the information inputs of the registers of the first by (r + r) -and., Adder veow basic sequence, .tator, element prohibition, a trigger with a counting input, an ILZ-element, an AND element, a synchronization and control unit, the first information input of the first regiotra being the input of the task initial; conditions of the generator, the output of the first register is connected to the first information input of the adder of the basic sequence weights, and the adder is connected to the second information input of the first regiotra, the synchronization input of which is combined with the synchronization input of the remaining registers and connected to the nepBOfviy output of the synchronization and control unit., whose input connected to the start input of the generator, the outputs of the registers from the second to the (r-1) -th and the output of the (r + p) -th register are connected to the corresponding inputs of the group of information inputs of the switch, the second the synchronization input of which is connected to the second output of the synchronization and control unit, the third output of which is connected to the first synchronization input of the switch, the information output of which is connected to the second information / input of the adder of the base sequence weights, the third synchronization input of the switch is combined with the nepBfcUvi input of the Il / Dl and is connected to the output of the inhibit element, the direct VCR of which is connected to the second output of the synchronization and control unit, the inverted input of the inhibit element is combined with the direct output with a countable trigger input, which podkolochen counting input to the output element. And, the first input of which is combined with the fourth synchronization and control unit, the second input of the And element is connected to the second input of the IZH element and connected to the output of the information tracking signal of the switch, the IZ element output is connected to the synchronization input of the adder of the base sequence weights, the trigger reset input with the counting input connected to the input of the synchronization and control unit / 3 /.

The use for these purposes of well-known generators of sequences of numbers C E, 3 allows you to get the weight of the digits that correspond only to two-digit numerical systems.

The technical result achieved using the proposed technical solution is the expansion of the functional capabilities of known devices due to the possibility of generating sequences of multi-digit numbers.

The technical result is achieved by the fact that the generator of sequences of numbers containing g-r sequentially connected through the information inputs of the registers from the first to (g + p) -th, a dryer for the weights of the basic sequence, a switch, a prohibition element, a trigger with a counting input, an IL element, an element And, the synchronization and control unit, and the first inform.ational p1, the input of the first register is the input of the job of the initial conditions of the generator, the output of the first

the register is connected to the first information input of the ummators veow base sequence, and the output of the ummator is connected to the second information input of the first register, the synchronization input of which is combined with the synchronization input of the other registers and connected to the first synchronization and control unit, the input of which is connected to the generator start input, the outputs of the registers from the second to the (r-1) -th and vkod (r + r) -th registers are connected to the corresponding inputs of the group of information inputs of the switch, the second synchronization input of which connected to the second / output of the synchronization and control unit, the third output of which is connected to the first synchronization input of the switch, the information input of which is connected to the second information / input of the supervisor of the scales of the basic sequence, the third synchronization input of the comptator is combined about the first input of the IL element and connected to the output of the i.zlret element, the direct input of which is connected to the second output by the synchronization and control unit, the inverse input of the inhibit element is combined with the direct output of the trigger with the counting input, counting whose input is connected to the input of the AND element, the first input of which is combined with the fourth part of the output of the synchronization and control unit, the second input of the AND element is connected to the second input of the element. The IL is connected to the output of the signal for tracking information of the switch, the output of the IL element is connected to the synchronization input of the cyMiviaTopa base sequence balance, the trigger reset input with the counting input is connected to the input of the synchronization and control unit, it additionally contains a shift shift register, subtracting the counter, a logical increased, two delay elements, a zero decoder and an accumulating adder, npi - the information input of the subtracting counter is the input of setting the binary code of number d, and the information input of the ring reg tra shift is the input job dvotshno-encoded representation of a repeating multi-valued bits dr, Riley dq-number control input circular shift register connected to the fifth output and synchronization upr.avleniya, circular shift register output myaadshego discharge unit connected to the control

the input of the logical node, the information input of which is combined about the output of the first register, the output of the logic module is connected to the second information input of the glowing adder, the output of which is the output of the sequence generator of the weights dr, p- and dq numbers and combined through the successively switched on first delay element about the first information / input the accumulating ommator, the first control input of the subtracting counter, is connected to the eighth output of the synchronization and control unit, and the second control input is connected to the output of the second delay element and the input Resets the accumulating adder, the control input of which is connected to the seventh output of the synchronization and control unit, the output of the subtracting counter is combined with the input of the zero decoder, the output of which is the output of the sign of readiness of the current result and connected through the second delay element with the input Reset accumulating adder, the control input of the logical device is connected to the sixth output of the block synchronization and control.

| The essence of the proposed technical solution is as follows. When processing vibrodiagnostic information based on the method of representation numbers g 1 s, two numerical systems are used. The basis of the first of them is made up of redundant (r, p) codes that allow you to generate a sequence of (r, p) numbers with arbitrary initial conditions and defined by the following 1111 recurrence relation:

Bg, pC1) br, p (S) ... br, p (p) Ko;

br.p (P + l) SS br, pCp-) 2 .... br, p () S;

br. pCm) br, pCm-l) + ... + br, p (in-r) -b br, p (m-r-p);

where: XG - an arbitrary initial trick;

g - the maximum number of units in adjacent binary digits (g, p) - numbers;

p is the maximum number of zeros in addition to the allowed group units.

The second numerical system is based on the recurrence relation (I), which allows you to generate excess n - numbers with arbitrary initial conditions in the following way:

bad) Xo, bci (S) gbcc (l). ..., bq (q) SbqCq-l);

bq (m) 2bq (), ba (m + l)) + bcjCm-l), bcjCm + S) gbci (Tn + l),. . . , B3 (+ a-1) Sbci (m + q);

P P I 4 GG gz -i- n 1 Yag: -h 1

  f J J - j 3 1. f41; - „. , i J., M-

Formula (II) corresponds to redundant q-number systems with a mixed base equal to 1.5 and I.O.

Examples of (g, p) - and q - sequences are given in 31.

Since the entire q - sequence is divided into groups, each of which consists of q binary digits, it can be interpreted as a dg - sequence (d .3,4, ..) with an enlarged base, equal to three (1.5 3) for q, that is, when one, for example, a four-digit dq-bit is encoded by two binary q-bits / 1 /.

In the general case, the base of a d - sequence with a multi-valued representation of each of its members is defined as

Q Q-2

Sda S - 2 (III)

(Ii)

24, ....

However, for other practical purposes, the most interesting are numerical systems with a fractional base, the value of which varies in the range from 1 to.

To expand the fractional base of the numerical system (I) per. range 2.0, it is proposed to determine any w-bit (g, p) -number in the form of a polynomial:

Nr, p S g CE (s () g, p Sr, p 3. (IY)

where: KE (yyy) g, p is the quantitative equivalent of the binary (g, p) -symbol and, written at its position;

Sr, p 1 i rn bg, p () / br, p (w) J is the base (gr) - cgp - ™ of the left system, and the weight of the nth discharge (r, p) -sequence

defined as: hv. ) KB (ff., A Sv. Ch. I, g Y.

- l J i ..1 .., .. -f-jij, j, j j., -, -, j i t 1 j. ,

The expressions (IY) and (Y) do not contradict the generally accepted view of ordinary (multiple powers of two) binary codes for which SE (1) 1 and CE (n) о, since Formula (IY) is converted to the standard form:

Yo E ("2 2)

At the same time, with this approach, (r, p) chiol systems are strictly positional and, therefore, 1 there is the possibility of enlarging the fractional base of the Sr, r b.azovsgo (g, p) -code by raising it to the power d S, 3 , 4, .... (by analogy with the transition from the standard binary PS to the number systems, the base of which is a multiple of two degrees: the 8th or 15th SS),

With that said, dr, p is a numerical system defined as follows:

m-l

. i -.- r- l i i GL

1,, .. v,. i i, .- L. J

1

s5-r, p 1 i 1L bd-r, DCi + l) / bd-r, p (i) 3 Sr, p

1 -IT 00 -j -i about Q. 9 O

one - . 1-,,, j, ja- J., -. ,,:. . ,

  - - -1 f i - -1 T rH4- i 1-1 -А-Н + h

- ". -i -. / -.T J., X. i A, i-r ,. , V -1-J- ./ f-lT -J,. . . J

where: bd-r, p is the weight of the discharge d, p-sequence;

62 - the value of O RSC 1, located at the z-th position of the base (g, p) -sequence.

For d 1, the expression (YI) corresponds to (g, p) -numeric systems, and for d 1, dr p -numbers J are obtained, each of which is encoded by the corresponding Cr, p) -combinations of d binary digits.

The general structure of the i-ro discharge of the dr .p number is shown in Table 1.

Thus, the introduction of the concept of a quantitative equivalent, a specific number allows, on the basis of calcareous binary redundant (r, p} -number systems, to construct the corresponding multi-valued dr, p-number systems

When designing specialized computing devices, I work 1SCH1x in dr, p-code, and., Where there is no need to translate numbers from the dr-, p-number system into the usual noble representation, it is important to have a device. The generation of lean weights is subject to handling dr, p-discharges.

From the formula CYI) it follows that the weight of the i-ro dr, p-discharge can be calculated on the basis of the base (g, p) code in the following way:

| H br, nCz) 63

i, -3-v- -,

-L-i i

bones of the scales of the river Ezryad at d a, g S, p 1 and the initial CONDITION

To 1.

It should be noted that the flattering equivalents of the basic (r5p) -sequence are defined in the form of repeating groups of symbols 1 1 О ... 1 1 П and the resulting dr, p-sequence 6 6 6 6 coincides from.

Indeed, for the basic () -sequence, we have (see the CYI formula):

3G, 9S7 / 504 s, 1.839;

(iOr.p at 9S7 / 1.839 1D394 5

LtQ П -i Н Nr, p 1Д394 1.839 + a for dr-, pSd-r, pinpH 1.8393.

In the case under consideration, the basic d-equidistant (r, p) combination 1 1 О is encoded by dr p-symbol 5. The appearance of this symbol can be arbitrary, it is only important that its quantitative equivalent is determined by the formula (YI) as follows : 1D394 1.839 + 1, + 1, 839 + 1, 839 + 1,, 839 1704.108, bone follower (see forge / lu (1U)) we get 1 ,, -1,, 839 +

The structure of the 1st discharge is dr, p is the number Pr1her of the formation of the weights of the discharges at, Table S. d-, p-sequences Ho 1 tape dr, p-follower carry M- -. .. Г J; i

and, therefore, for the same decimal number, the corresponding to it (r, p) - and dr, p followers coincide.

Based on the foregoing, the technical result - the expansion of functional capabilities, is completed by constructing a device that generates a sequence of multipoint numbers in accordance with expressions (I), (II) and (YII) at the output.

Figure 1 shows the structural diagram of the proposed device.

The generator of sequences of multi-digit numbers contains block 1 of synchronization and control, r + p of sequentially connected registers 2-1, 2-2, 2-3, switch 3, adder 4 weights of the basic sequence: carry 5 ban element 5, element 6 OR, trigger 7 with by counting input 7-1 and reset input 7-S, element 8 AND, ring shift register 9, subtracting counter 10, logic node 11, zero decoder 12, first 13 and second 14 delay elements and accumulators

Information input of the subtracting counter. 10 is the input for setting the binary code of the number a (d-parameter), and the information input of the annular shift register 9 serves as the input for setting the binary-coded representation of one and the same multiple-valued bits dr, p-number (d-bit code). The initial conditions of the Ho generator are set by ps to the first information input of register 2-1.

The information output of the previous register is connected to the information input of the subsequent register.

The output of register 2-1 is connected to the first information / input of the adder 4 of the basic sequence weight, and the output of adder 4 is connected to the second information input 2-1, the synchronization input of which is combined with the synchronization input of the other registers Q48R-Jire - in 44hfiT rfi - I EDRR-A-B 2 4- - ji 1 h i - tJ- - 5. j 5.9466L 6.22 ° 1703.99, are calculated according to the formula (P):

gth, S-y and is connected to the first output 1-1 of the syncronizing and control unit 1, the input of which is wired to the input of the generator. The outputs of the registers from the second (regcotr 2-2) by (r-1) and output (g + p) of the register (register -3) are connected to the corresponding inputs 3-4, 3-5 of the group of information inputs of the switch 3, the first synchronization input of which 3-2 is connected to BTopow output 1-2 of the synchronization and control unit i, the third output of which 1-3 is connected to the second synchronization input 3-1 of switch 3, the information output of which 3-5 is connected to the second information input of the adder 4 weights of the basic sequence, the third input of synchronization 3-3 of switch 3 is combined with the first input of electronic element 6 IZH and connected to the output of the inhibit element 5, the direct input of which 5-1 is connected to the second output of the 1-2 synchronization and control unit 1, the inverse input 5-2 of the inhibit element 5 is combined with the direct output of the trigger 7 with a counting input, counting input which 7-1 is connected to the output of element 8 AND, the first input of which is combined with the fourth quarter &: one of 1-4 synchronization and control units 1, the second input of element 8 AND is connected to the second input of element 6 of the RC and connected to the output of 3-7 tracking signal information of the switch 3, the output of the element 6 OR is connected to ode sinhronizschiii sumkshtora weights 4 base sequence, the reset input of latch 7-2 with a countable 7 input is connected with the input unit 1 and the synchronization upr.avleniya.

The control input of the ring shift register 9 is connected to the fifth output 1-5 of the synchronization and control unit 1, the low-order output of the ring shift register 9 is connected to the control input 11-S of the logger node 11, the information input of which 11-1 is combined with the output of register -1 . The output of the logical node 11 is connected to the second information input 15-2 of the accumulating adder 15, the output of which is the output of the sequence generator of the weights dr, p- and dq-numbers and combined through the series-connected first element of the delay 14 with the first information input of the accumulating adder 15 First the control input 10-1 of the subtracting counter 10 is connected to the eighth output 1-8 of the synchronization and control unit 1, and the second control input IQ-g is connected to the output of the second delay element 13 and to the input Reset of the accumulating sum RA 15, the control input of which is connected to the seventh output 1-7 of the synchronization and control unit 1. The output of the subtracting counter 10 is connected to the input of the zero decoder 12, the output of which is the input of the sign that the current result is ready and connected through the second element of the delay 13 connected to the input Reset the accumulating adder 15, the control input of the lap device 11. is connected to the output 1-6 of the synchronization and control unit 1

The generator operates in three modes:

1st mode - the formation of a sequence of weights of digits of unique (g) numbers;

S-th mode - the formation of a sequence of weights of digits of unique q-numbers;

3rd mode - the formation of sequences of weights of discharges of multivalued dr, p- and dq-numbers

Blocks 1,..., J8 support generation in accordance with formulas (1) and (II) of the weights of the digits of the base Cg, p) - or q-sequentially consisting of binary bits of the same type 111, ...,. The generation of these bones at the output of the S-1 register for the first half-cycles of the multi-cycle cycle of the generator is carried out according to formula (II) by summing l-ro, g-rOj. . . , th and g-th numbers on the adder 4/3 /. The choice of a specific operating mode is ensured by setting in the synchronization and control unit 1 the values of the parameters g and p (mode 1) or q (mode S).

The first | pack / and the second corresponds to the value of pairs. and the code dr, p - or dr-discharge., equal to one. Before starting work, these quantities are recorded respectively in the subtracting counter 10 and d, the l-bit ring shift register 9, which is equivalent in these modes to the exclusion of register 9 from re-examination, since a logical unit () signal will be constantly on it. Logic node 11 provides a code to be transmitted to its output at the information input 11-1, if at the control input 11 the signal of the unit is assigned. Since in the considered modes, the code of the current weight of double-digit (m, p) - or q-sequences will be in each the second half-cycle to enter the information input 15-2 of the adder 15 to be summed up with the result of the previous action. applied to the first information input 15-1 through the gate element 14, necessary for the temporary coordination of the operation of the successor.

In the second half-cycle of each clock cycle of the generator, the synchronization and control device 1 generates control clock pulses, which force the logic node 11, and the PI pulses arriving at the first control input 10-1 of the subtracting counter 10 and allowing the unit to be subtracted from its contents. Since in the considered mode the value of the d-parameter is equal to one, in the second half-cycle the contents of counter 10 become equal to zero and at the output of decoder 1 there is a sign - formation of the result, which is obtained in adder 15 under the influence of the control signal received at the input 15th. The result should be from the output of the generator for a time, the duration of which is determined about the moment of the input from the output 1-7 of the unit 1 of the signal US for the time of the delay of the element 13. After this time, the adder 15 is set to zero

Thus, in the considered modes, in every second half-cycle of the generator’s operation, in the adder 15 the previous previous result is summed up and the weight of the base (g) - or q- succession of the note formed in the known manner 3 1 in the first half-act of each measure at the output of the register d-1 and, consequently, at the output of the generator, getting 2 fl is corresponding to the sequence of weights of the digits (r, p) - or q-numbers.

and the original sequence consists of identical characters encoded as 110 (with possible coding of bits in the original dr, p-sequence).

Before starting work, the constant XQ is written into the S-1 register, the binary image 1 1 is written about the repeating d p-digit j into the register 9, and the value of the parameter d 3 is entered into the counter 10.

The cycle of generating the weight of one dr, p-discharge is carried out per clock cycle, each of which consists of two half-cycles. In each first half-cycle of the generator operation, at the output of register 2-1, the binary equivalent of the current discharge of the basic binary (rjp) sequence is formed in a known manner 3 J. In the first half-cycle of the first measure it is 1, in the second - Sj in the third - 4 and so on (see Table 2, line h-.p (z)) In the first half-cycle under consideration, the information input 11-1 of the logical Uela 11 receives the binary equivalent of the weight of the least significant bit of the base (r, p-sequence, equal to 1. When the atom at the control input of the 11-S node contains the value of the least (first) bit ej (, .... d) of the binary-encoded representation 110 dr , p-symbol. At the moment, this value is zero, that is, e.1 0. The signal Y at the output of the logical node 11 is formed according to the following form yle: Y bg, p () & Et and, therefore, zero operands are in the second half-cycle of the first clock on the information inputs 15-1 and 15-2 of the accumulating adder 15. At the end of the second half-clock of the first clock, the synchronization and control unit 1 provides a unit subtraction from counter 11 with simultaneous amplification of the operands present at the inputs of the 15-1 and 15th adder 15, as well as an annular shift towards the lowest digit contained a register 9. In the cut to; the beginning of the second clock, the contents of the main nodes of the device will be as follows:

g prutd (-; rn-g; P - 1} - 1 n g

h l, - l -, - „- i„ I 5

(register 9) - 1 1 Оо (the least significant digit is on the left, its value

(adder 15) - p.

In the first half-cycle of the second measure (see table.), At the output of the register -1 is formed according to Formula (II) 3, the weight of the second row of the base (g, p) -sequence is equal to E since the control input is 11-2 lap-where node 11 in the considered beat of the signal signal 1. Then the adder 15 performs the operation of the previous action (it is equal to zero) and the weight bg, p (th) th Next, the contents of register 9 are annularly shifted and the unit is subtracted from the contents of count 10 By the beginning of the third measure, the contents of the main components of the device will change as follows azom:

(register S-1) - 2-10,

(register 9) - 1 О 1-2 (the least significant digit is on the left, its value

(counter 10) - IIQ,

(adder 15) - 2in

in the third clock cycle (, see, Table 2), at the information input 11-1 of the logical node 11, the weight of the third bit of the basic (r, p) -sequence Lg, p (3) 4-1o is formed, which is received, since e. i to the input of the adder 15 After summing with the result of the previous action equal to b, p (2) 2io, the contents of the adder will change to + 4 .6-1 p. At the end of the third clock cycle, a ring shift is made in register 9 and the unit is subtracted in the counter 10. At the same time, the contents of the counter become equal to zero, which is a sign of the formation in the adder 15 of the current weight dr, p-sequence bd-r, p (1) 6. After a time determined by the delay element 13 (sufficient to read the contents of the adder 15), the installation of the adder to the original zero TATUS and restore the contents of the counter 10 and on exercise, ulation input 10-2. So, by the way, by the beginning of the next cycle of work, the main nodes of the device will be in the following state:

- 15 p -1 J.,. J

(counter 10) - Zu, (adder 15) - Oy. Further, the device operation is repeated, and every d 3 cycles (or one cycle) at the output of decoder 13, a sign of readiness of the result is formed, and the current weight of the di-, p-sequence (unified the digits of which 6 are encoded with a (g, p) -code as 110) - will form the following series of numbers at the output of adder 15: 37io (in the second cycle) j ЕЗОю (in the third cycle). 143110 (with the fourth cycle). .... etc (ohm.tab.E)

If the p-sequence is selected as the base sequence, then the blocks, ..., 8 of the device. work.a1} t in accordance with formula (II), while the current value of the jp-number is generated at the output of register i-1. The operation of blocks 9, ..., 15 is carried out similarly to the case of dr, p-sequence described above. However, here, the SIQ constant should be written to the counter 10 as initial data. since the basic n-sequence has 3 values of the parameter q, and in register 9 one of the possible encoding options for repeated d is written; -bit sequence. For example, when encoding a dq-discharge in the form

The generator’s operation cycle consists of two clock cycles and at the end of each of the cycles at the output of the ommatsra 15 the following values of the weights of the dq-digit bits are sequentially formed: 3, 10, 30, 90,, .., etc. taking into account the basic q-sequence given in 3 3.

Thus, the introduction of new blocks and relationships allows, compared ®) on the prototype, to generate sequences of multivalued numbers in a wide range of representations of IK bases (IjO, ..., IjBlS, ... 2, Dj ...); which significantly expands the functionality and scope of use of these devices. By expanding the range of numbers, it seems possible to generate new approximating psilinomas for scanning the vibration intensity zones of turbines of a wide class of use.

Sources of information taken into account when preparing the application:

1.Zbrodov N.A. et al. The method of representation numbers in the diagnosis of turbine units /./ Diagnostics of equipment and pipelines, M.; IRC GAZPROMD995.N3,0.6-12.

2. The author's certificate of the USSR N 1104493, M class. Z About F 1 / Oh. Publ. 23 ..

3. The author's certificate of the USSR N, M C. b 06 F 1/02. Publ. 05/05/86 (prototype)

Claims (1)

A generator of sequences of weights of bits of excess numbers with arbitrary initial conditions, containing r + p sequentially connected at the information inputs of the registers from the first to (r + p) th, the adder of the weights of the basic sequence, a switch, a ban element, a trigger with a counting input, an OR element, element And, a synchronization and control unit, wherein the first information input of the first register is an input for setting the initial conditions of the generator, the output of the first register is connected to the first information input of the adder weight in the basic sequence, and the adder output is connected to the second information input of the first register, the synchronization input of which is combined with the synchronization input of the remaining registers and connected to the first output of the synchronization and control unit, the input of which is connected to the "Start" input of the generator, the outputs of the registers from the second to ( r - 1) th and the output of the (r + p) th register are connected to the corresponding inputs of the group of information inputs of the switch, the second synchronization input of which is connected to the second output of the synchronization and control unit, t the output of which is connected to the first input of the synchronization switch, the information output of which is connected to the second information input of the adder of the base sequence weights, the third synchronization input of the switch is combined with the first input of the OR element and connected to the output of the inhibit element, the direct input of which is connected to the second output of the synchronization unit and control, the inverse input of the inhibit element is combined with the direct output of the trigger with a counting input, the counting input of which is connected to the output of the And element, the first input which is combined with the fourth output of the synchronization and control unit, the second input of the AND element is connected to the second input of the OR element and connected to the output of the signal information of the switch, the output of the OR element is connected to the synchronization input of the adder of the base sequence weights, the trigger reset input with the counting input is connected to the input synchronization and control unit, characterized in that, in order to expand the scope due to the possibility of generating sequences of discharge weights values of d _{r , p} - and d _q -number, a shift ring register is introduced into it, a subtracting counter, a logical node, two delay elements, a zero decoder and an accumulating adder, the information input of the subtracting counter being the input of setting the binary code of the number d _q , and the information input of the circular shift register is the input of the binary-encoded representation of one of the repeated multivalued digits of d _{r , p} or d _{q q} numbers, the control input of the circular shift register is connected to the fifth output of the synchronization and control unit , the low-order output of the ring shift register is connected to the control input of the logical node, the information input of which is combined with the output of the first register, the output of the logical node is connected to the second information input of the accumulating adder, the output of which is the output of the sequence generator of the weights d _{r , p} - and d _q - numbers and combined through a series-connected first delay element with the first information input of the accumulating adder, the first control input of the subtracting counter is connected to the eighth the output of the synchronization and control unit, and the second control input is connected to the output of the second delay element and the input "Reset" of the accumulating adder, the control input of which is connected to the seventh output of the synchronization and control unit, the output of the subtracting counter is combined with the input of the zero decoder, the output of which is the output of the sign the readiness of the current result and is connected through a series-connected second delay element with the input "Reset" of the accumulating adder, the control input of the logical device is connected n with the sixth output of the synchronization and control.