RU2855120C1 - Method for phase synchronisation of clock pulses - Google Patents

Abstract

FIELD: pulse technology.

SUBSTANCE: invention can be used when it is necessary to synchronise asynchronous digital devices in many fields, for example, in medical research when it is necessary to synchronise encephalographs, electrocardiographs, devices for video recording of the patient's condition, in radar, in precision pulse generators. In the method of phase synchronisation of clock pulses, the current position of the clock pulse front propagating sequentially in the first and second multi-tap delay lines with maximum delay and delay exceeding the delay of one section of the first multi-tap delay line, respectively, is stored at the moment of arrival of the external synchronisation pulse. Triggers of the first and second groups are set to the initial state by the external synchronisation pulse and the delayed external synchronisation pulse, change their state once during dynamic synchronisation of the trigger from the corresponding output of the multi-tap delay line and are switched to the storage mode when the state of at least one trigger of the group changes before the arrival of the next external synchronisation pulse.

EFFECT: increased synchronisation accuracy with low hardware costs.

1 cl, 2 dwg

Description

The invention relates to the field of pulse technology and can be used when it is necessary to synchronize asynchronous digital devices in many areas, for example, in medical research when it is necessary to synchronize encephalographs, electrocardiographs, devices for video recording of a patient's condition, in radar, in precision pulse generators.

In precision pulse generators designed to generate pulse trains with specified timing parameters—duration, time delay, and repetition period—the task of synchronizing the generated pulse train with an external synchronization pulse arises in external trigger mode. In this mode, the time intervals of the generated pulse train are counted from the external synchronization pulse.

Precision pulse generators are typically built as digital devices and have their own precise clock source. If the built-in clock source is selected as the synchronization signal source, the timing parameters of the generated pulses are multiples of the clock period, and the error in their setting is determined primarily by the error in the clock period. However, when synchronizing with an external pulse that is not tied to the generator's own clock, the error in locking to the external synchronization pulse can vary within a single clock period.

To eliminate this variability, the position of the clock pulse relative to the external synchronization pulse must be the same, that is, the delay of the front (or fall) of the clock pulse must be constant relative to the front (fall) of the external synchronization pulse.

This problem is solved by the method [1. EAPO 039506 B1. Method for synchronizing clock pulses with an external pulse. November 30, 2020].

The method consists of storing an m -bit binary code, representing the set of logical signal levels at the input and m- 1 initial taps of a multi-tap delay line during the propagation of clock pulses in it, in a memory register at the moment of the appearance of an external synchronization pulse (its rising or falling edge), and subsequently comparing this code with the current code of the multi-tap delay line at the last m -taps of its ( k + m ) taps, while the clock pulses are generated at the output of the coincidence (code comparison) circuit at the moment of code coincidence. The position of the clock pulses is fixed relative to the external synchronization pulse with an error not exceeding the delay of one element of the multi-tap delay line.

The disadvantage of this solution is that the error value determined by the delay of one element of the multi-tap delay line is limited by the speed of the match circuit, which may not have time to compare the codes at its inputs in a time equal to the delay of one element, since a change in the code at the terminals of the delay element will occur.

This drawback is eliminated when using the synchronization method [2. RU 2693595 C2. Method for phase-locking a generated pulse sequence to an external trigger pulse. 15.03.2018], which consists of isolating clock pulses from a tap of a multi-tap delay line, on which the clock pulse propagating along it is delayed by a minimum time interval with respect to the external synchronization pulse, due to the simultaneous triggering of identical synchronous frequency dividers, each clocked from its own tap of the multi-tap delay line, the output signals of which are summed by a logical addition circuit. The front of the synchronized clock pulse is formed by the synchronous divider that wins the competition (the first to trigger after the external synchronization pulse).

A disadvantage of this method is the need to use a higher clock frequency, as the output clock frequency is lower than the input frequency. Therefore, high-frequency counting triggers are required, with at least two of them in each divider. Furthermore, at high frequencies, it is more difficult to ensure high stability of quartz crystal oscillators. Frequency multiplication of precision quartz oscillators leads to increased phase noise, which increases jitter in the synchronized clock pulses.

A common drawback of the considered synchronization methods is the proportional increase in equipment volume as the synchronization error decreases.

The requirements for the speed of the element base and the volume of equipment can be reduced by using a method adopted as a prototype [3. RU 2822445 C1. Method of phase synchronization of clock pulses by an external pulse. 01/24/2024]. The method consists in switching clock pulses from one of the terminals of the first multi-tap delay line, on which the clock pulse propagating along it is delayed by a minimum time interval with respect to the external synchronization pulse, to the corresponding input of the first switch, from the output of which phase-synchronized clock pulses are removed, wherein the position of the front of the clock pulse relative to the external synchronization pulse is preserved along this front in the triggers of the first group during the time interval determined by the duration of the pulse generated from the external synchronization pulse, which enables the preservation of the position of the front of the clock pulse, and the trigger of the first group that has changed its state determines the terminal of the first multi-tap delay line, on which the front of the clock pulse lags by an interval exceeding the switching time of the trigger, wherein the clock pulse from the output of the first switch is fed to the input of the second multi-tap delay line with a total delay of not less than the delay of one section of the first multi-tap delay line, and the synchronization of the clock pulses is carried out with respect to the second pulse, which enables the preservation of the position of the front of the clock pulse generated from an external synchronization pulse, delayed by a precisely fixed time interval, by maintaining the position of the front of the second group trigger, which controls the second switch, to the output of which a clock pulse is fed from the terminal of the second multi-tap delay line, on which its front lags by an interval exceeding the trigger switching time, while the possibility of changing the state of all triggers is excluded until the next external synchronization pulse, the reset pulse generated from which sets the triggers to the initial state.

The disadvantage of this method is the limitation on the maximum operating frequency and synchronization accuracy due to the need to use a pulse former that allows the preservation of the position of the front of the clock pulse with a fixed duration that exceeds the larger of two values, one of which is equal to the sum of the presetting and holding times of the signals at the information inputs (for example, J, K) of the triggers relative to the clock pulse that carries out their dynamic synchronization, and the second is equal to the sum of the delay of one section of the first delay line and the holding time of the signals at the information inputs of the triggers relative to the clock pulse, while the fulfillment of this condition must be guaranteed under operating conditions, which leads to the need to increase the duration of the pulse that allows the preservation of the position of the front of the clock pulse.

The technical problem that the proposed method is aimed at solving is increasing the operating frequency and synchronization accuracy while saving hardware resources.

The solution is achieved by storing the clock pulse edge position, propagating in the first multi-tap delay line with a delay approximately equal to the clock pulse repetition period, in the first group of flip-flops. The first flip-flop to change state controls the first switch, which commutates the clock pulse from one of the subsequent terminals of the first multi-tap delay line to the output of the first switch. The flip-flops of the first group are set to the same initial state by the level of the external synchronization pulse. When its level changes, they are switched to synchronous mode, and the first edge of the propagating clock pulse changes the state of one of the flip-flops in the first group of flip-flops.

From the output of the first switch, a clock pulse arrives at the input of the second multi-tap delay line, which has a delay exceeding the delay of one section of the first multi-tap delay line. Propagating along the delay line, its edge changes the state of one of the second group of flip-flops, which is set to the initial state by the pulse level received from the external synchronization pulse, extending it by a fixed interval no less than the maximum clock pulse delay time at the output of the first switch relative to the completion of the external synchronization pulse. Any flip-flop in the second group of flip-flops that has changed its state switches the clock pulse from one of the subsequent terminals of the second multi-tap delay line to the output of the second switch, and also blocks the possibility of changing the state of the flip-flops of the first and second groups of flip-flops by placing them in hold mode until the next external synchronization pulse. The delay from the moment of the first triggers in the first and second groups of triggers to the appearance of the blocking signal can lead to a change in the state of several triggers, but the position of the clock pulse edges at the output of the second switch will be determined only by the first triggers in the chains of the first and second groups of triggers that have changed their state.

The proposed solution is explained by: Fig. 1 - functional diagram of a device implementing a method of phase-locking clock pulses to an external pulse; Fig. 2 - timing diagram.

The method is implemented by a device variant shown in Figure 1 and consisting of: the first 1 and the second 6 multi-tap delay lines; synchronized by the front of two groups of triggers 2 and 7 - type with asynchronous setting to the initial state; first and second switches 3 and 8 from two-input and multi-input logical elements "AND-NOT"; delay element 4 logical element "AND" 5 and logical element "NAND-NOT" 9.

The clock pulses "CLK" are fed to the input of the first multi-tap delay line 1. The terminals of the first multi-tap delay line 1 are connected to the corresponding synchronization inputs C of the first group of triggers 2 and the signal inputs of the first switch 3 (the second inputs of the two-input logical elements "NAND-NOT") with a shift in relation to the control inputs of the first switch 3, to which the corresponding inverse outputs of the first group of triggers 2 (the first inputs of the logical circuits "NAND-NOT") are connected. The combined inputs of the setup the first group of triggers 2, the input of the delay element 4 and the first input of the logical element "AND" 5 form the input of the external pulse "SYNC", the output of the delay element 4 is connected to the second input of the logical element "AND" 5, and its output is connected to the combined inputs of the installation the second group of triggers 7. The direct outputs Q of the second group of triggers 7 are connected to the inputs of the AND-NOT logical element 9, and its output is connected to the combined inputs the first and second groups of triggers, to the combined J inputs of which a low voltage level (logical zero) is supplied.

The output of the first switch 3 is connected to the input of the second multi-tap delay line 6, the taps of which are connected to the synchronization inputs C of the second group of triggers 7 and with a shift to the signal inputs of the switch 8 (here the shift corresponds to two delay sections ), while the inverse outputs of the second group of triggers 7 are connected to the corresponding control inputs of the second switch 8. Phase-synchronized clock pulses "SCLK2" are removed from the output of the second switch 8.

The device operates as follows. Clock pulses "CLK" are fed to the input of the first multi-tap delay line 1. The edge of the next clock pulse appears alternately at its second pin 1.WITH2,then on the third - 1WITH3, etc. With the arrival of the external trigger pulse “SYNC”, all triggers of the first 2 and second 7 (with a minimum delay on the logical element “AND” 5) groups of triggers at the input of the installationare set to the initial state (at the direct outputs of the triggers there is a high logical level, and at the inverse outputs there is a low logical level). The low logical level from their inverse outputs goes to the control inputs of the first 3 and second switches 8 (the first inputs of the two-input logical elements "NAND-NOT"), blocking the passage of clock pulses to their outputs, and from the direct outputs of the triggers of the second group of triggers 7, the high logical level goes to the inputs of the logical element "NAND-NOT" 9, the output signal of the low logical level "BLK" sets at the inputsThe first 2 and second 7 groups of triggers use a combination of logical signals 00, corresponding to the synchronous reset mode. When the external trigger pulse "SYNC" goes high (edge), synchronous reset of the triggers becomes possible. The first edge of the clock pulses propagating in the first multi-tap delay line 1 resets the dynamic synchronization inputs.Cthe corresponding trigger of the first group of triggers 2, while the high logical level of the control signal from its inverse output allows the passage of clock pulses of the signal to the output of switch 3. Clock pulses from the output of switch 3 "SCLK1" are distributed in the multi-tap delay line 6, and the appearance of a high logical level at the inputs the second group of triggers 7 (at the moment of completion of the external synchronization pulse delayed by the delay element 4 and the logical element "AND" 5) enables the synchronous reset of the triggers at the dynamic synchronization inputs by the front of the clock pulse propagating in the second multi-tap delay line 6, which leads to the permission for the control signals of the clock pulse to pass to the output of the second switch 8. The first reset trigger by the low-level output signal from the direct outputQsets a high level of the “BLK” signal at the output of the “AND-NOT” logic element 9, switching all triggers of the first 2 and second 7 groups to storage mode (prohibition of changing the state at the dynamic synchronization input)WITH).

All subsequent clock pulses will pass through the same channels of the first and second switches 3 and 8 until the next external synchronization pulse arrives, and the position of the front will be determined by the first triggers in the chains of triggers that have changed their state of the first 2 and second groups of 7 triggers.

For the functional diagram of the device shown in Fig. 1, it is assumed that the delay of the control signal 1 C 1 at the output of the trigger, triggered when the front of the clock pulse from terminal 1 C 1 of the first multi-tap delay line 1 is received at its dynamic synchronization input C , is less than the delay of one of its sections, therefore, by the time the front of the clock pulse appears at terminal 1 C 2, the corresponding channel of the first switch 3 will be open. When the last trigger in the first group of triggers 2 is reset by the front of the clock pulse from the last terminal 1 C 6 of the first multi-tap delay line 1, the channel of the first switch 2 is opened for the clock pulse from the first terminal of the multi-tap delay line 1 C 1.

The delay of one section of the second multi-tap delay line 6 is less than the delay of a section of the first multi-tap delay line 1, so the clock pulse is applied to the open channel after being delayed by several sections (in Fig. 1, the delay is achieved by two sections). Since the maximum delay of the second multi-tap delay line 6 is significantly less than the clock pulse period, cyclic signal ordering is not feasible for it. This necessitates the introduction of additional delay line sections (in Fig. 1, there are two sections).

Without taking into account the additional sections, the maximum delay of the second multi-tap delay line 6 must exceed the delay of one section of the multi-tap delay line 1. The delay of the delay element 4 is selected so that the delay t _З5 of the front of the signal "SYNC1" at the output of the logical element "AND" 5 in relation to the front of the signal "SYNC" is not less than the maximum delay time of the clock pulse at the output of the switch 3 in relation to the external synchronization pulse:

where t _П is the data presetting time relative to the pulse front at the trigger synchronization input, Δ t ₁ is the delay of one section of the first multi-tap delay line 1, k is the number of delay sections of the first multi-tap delay line 1, delaying the clock pulse at the input of the open channel of switch 3 (in Fig. 1 k = 1), t _{ЗК1МАКС} is the maximum delay of the first switch.

On the other hand, the maximum delay at the output of the AND gate 5 must not exceed the total value of the minimum clock pulse delay and the total delay of the second multi-tap delay line:

where t _ЗК1МИН is the minimum delay of the first switch 3, t _ЛЗ2 is the delay of the second multi-drop line.

This choice ensures that at the moment the front of the “SYNC1” signal appears at the output of the “AND” logic element 5, the front of the “SCLK1” clock pulse will propagate in the second multi-tap delay line 6.

This solution reduces the equipment footprint. For example, achieving a 1% phase synchronization error using a single delay line would require a 100-pin delay line, 100 flip-flops, and a 100-channel switch. The proposed solution requires two multi-tap delay lines with 10 and 12 pins, respectively, 20 flip-flops, two 10-channel switches, and a 10-input NAND gate.

The timing diagram of the device (Fig. 2) illustrates the phase locking method. In the diagram: 1C1 … 1C6, 2C1 … 2C8 are the output signals of the same terminals of multi-tap delay lines 1 and 6, respectively; 1C1 … 1C6, 2×1 …2C6 are the output signals of the same outputs of the first 2 and second 7 groups of triggers, respectively; SYNC is the external synchronization pulse; SYNC1 is the extended external synchronization pulse; CLK are the clock pulses; SCLK1 are the synchronized clock pulses at the output of the first switch 3; SCLK2 are the synchronized clock pulses at the output of the second switch 8; T is the period of the clock pulses; Δt ₁ is the delay of one section of the first multi-tap line 1; Δt ₂ is the delay of one section of the second multi-tap line 6. The relationship of events in Fig. 2 is shown by arrows directed from the cause event to the effect event.

Before the external synchronization pulse SYNC arrives, the clock pulses SCLK1 and SCLK2, synchronized with an error of Δt1 and Δt2, are present at the outputs of switches 3 and 8, respectively, therefore the state of these signals at the moment of arrival of the next external synchronization pulse SYNC is uncertain (shown by dashed lines). The external synchronization pulse SYNC sets all triggers of the first group of triggers 2 to the initial state (the falling edge of the SYNC signal leads to the formation of a low level at outputs 1-4, as well as at all other inverse outputs of the first group of triggers 2), and the SYNC1 signal similarly sets the triggers of the second group of triggers 7 (Fig. 2 displays the signals only at outputs 2C5-2C7). In this case, the first 3 and second 8 switches do not pass clock pulses, i.e. at their outputs SCLK1 and SCLK2 a logical 0 is set. At the edge of the external synchronization signal SYNC, the triggers of the first group 2 switch from the asynchronous initial setup mode to the synchronous reset mode, since their inputs J are grounded, and at the inputs There is a low-level BLK signal from the output of the NAND logic element caused by the presence of all high levels at its inputs from the direct outputs of the second group of triggers 7. The very first edge of the clock pulse propagating along the first multi-tap delay line 1 from pin 1C4 resets the trigger of the first group of triggers 2 and a high level is established at its inverse output 1C4, permitting the signal from pin 1C5 to pass to the output of the first switch 3. In this case, the signal at its output SCLK1 appears with some delay. During the low level of the BLK signal, the signals from pins 1C5 and 1C6 of the first multi-tap delay line 1 also have time to reset the corresponding triggers (their output signals are not shown in the diagram). This leads to an increase in the duration of the high level of the clock signal SCLK1 by the amount of the delay _of two sections 2Δt1 .

This clock pulse propagates in the second multi-tap delay line 7, and after a time interval t _З5 , the SYNC1 signal goes high and switches the second group of flip-flops 7 to the synchronous reset mode. The edges of the clock pulse from the terminals of the second multi-tap delay line 2C5-2C6 reset the corresponding flip-flops, and the high levels from their terminals 2C5-2C6 control the switch and pass the clock pulses from terminals 2C7 and 2C8 of the second multi-tap delay line 6 to the output. In this case, the edge of the output clock pulse SCLK2 is tied to the edge of the external synchronization pulse SYNC with an error of Δ t ₂ . When the first trigger of the second group of flip-flops 7 is reset, the low-level output signal 2Q5, arriving at the input of the NAND logic element 9, causes a high level to appear at its BLK terminal and switches all flip-flops to the storage mode.

Thus, the proposed method of phase synchronization of clock pulses ensures high synchronization accuracy with low hardware costs.

Claims (1)

A method for phase synchronization of clock pulses, which consists in that the position of the front of a clock pulse, propagating sequentially in first and second multi-tap delay lines with a delay approximately equal to the period of the clock pulses, and a delay exceeding the delay of one section of the first multi-tap delay line, respectively, is stored in the first and second groups of triggers, wherein the first trigger that has changed its state in each group controls the corresponding first and second switch, which switches the clock pulse from one of the subsequent terminals of the corresponding multi-tap delay lines to the output of the first and second switches, the clock pulses from the output of the first switch are fed to the input of the second multi-tap delay line, and synchronized clock pulses are removed from the output of the second switch, characterized in that the triggers of the first and second groups are transferred and held in the initial identical state by the level of the external synchronization pulse and the level formed from it by increasing the pulse duration, respectively, the preservation of the position of the front of the clock pulse propagating in the first and second multi-tap delay lines is carried out output signals from their terminals connected to the dynamic synchronization inputs of the first and second groups of triggers, upon completion of the external synchronization pulse and the pulse duration formed from it by an increase in the value that guarantees that its end falls within the propagation interval of the clock pulse front in the second multi-tap delay line, respectively, and the possibility of a subsequent change in the state of the triggers of the first and second groups of triggers is blocked until the next external synchronization pulse when the state of one or more triggers of the second group changes compared to the initial state, transferring them to storage mode.