RU2849160C1 - Multiple-threshold device for decoding gold sequences based on selection of valid sections and majority processing of calculated combinations - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to devices for decoding discrete information and is intended for the transmission of discrete (digital) information with high reliability over communication channels. The technical result is achieved through the use of an additional mechanism that analyses all elements of the code word to make the most complete use of its potential redundancy and reduce the probability of errors. For this purpose, the decoding device additionally contains a counter connected to a threshold at z logical "1", a logical adder, a converter performing a logarithmic operation in GF(2 ^k ), a converter performing an antilogarithmic operation in GF(2 ^k ), a GF(2 ^k ) inverse element converter, a GF(2 ^k ) field convolution calculator, a sixth key, a random-access memory (RAM), and a majority element.

EFFECT: improved accuracy of decoding a code word on a discrete symmetric communication channel with single independent errors.

1 cl, 2 dwg

Description

Field of technology

The invention relates to radio engineering, namely to devices for decoding discrete information, and is intended for transmitting discrete (digital) information with high reliability over communication channels.

In the field of discrete (digital) information transmission, encoding devices that change the phase of pseudo-random sequences have an undeniable advantage in protecting information from interference. The task of further increasing the encoding speed and noise immunity of information encoding devices based on the use of linear recurrent sequence (LRS) segments as code words is associated with the implementation of the principles of soft LRS processing, one of which is threshold decoding [Zolotarev V.V. Coding for Digital Communications. Handbook / Ed. by Corresponding Member of the Russian Academy of Sciences Yu.B. Zubov. - Moscow: Goryachaya Liniya - Telecom, 2022. pp. 51-55].

The success of threshold decoding of pseudo-random sequences depends on the correct frame synchronization (FS) of the decoder, which determines the phase of the pseudo-random sequence being processed. The process of detecting the pseudo-random sequence and FS synchronization in the receiving (decoding) device is based on the method of identifying the valid segment (IS).

Majority decoding in code combination processing is a decoding in which a decision is made based on a majority of identical values of the determined characteristic or parameter. This decision-making rule can be considered maximum-likelihood decoding [Kognovitsky O.S. Theory, Methods, and Algorithms for Solving Problems in Telecommunications Based on a Dual Basis and Recurrent Sequences: Doctor of Engineering Sciences Dissertation: 05.12.13. - SPbSUT, 2011. - 427 p., p. 154].

State of the art

The invention "Device for divergent decoding of segments of a linear recurrent sequence" is known under the patent RU No. 2820053, H03M 13/03, published on 05/28/2024, comprising a connected first key, a first single-channel delay line (SLD) for k bits (symbols), a second key, a counter with a threshold for m consecutively arriving logical "1"s, first and second accompanying matrices, a second SLD for k bits (symbols), a comparison unit, a SLD for N bits (symbols), a calculator, a third key, a d-channel delay line for N bits (symbols), a frequency generation unit, a fourth key, a logical adder and a logical inverter. The disadvantage of this analogue is the need to use only symbolic pseudo-random M-sequences as code words, which have additional error detection features before their decoding. With a large number of errors in a pseudo-random sequence, a large number of possible error correction options arise, the additional decoding of which generally reduces the speed of the error-correcting code.

The invention "Synchronization device based on matrix processing and decimation of a recurrent sequence" is known under the patent RU No. 2820337, H04L 7/02, published on 03.06.2024, comprising a connected logical adder module, a frequency generation unit, Q groups of delay modules for h cycles, each of which includes q=1...Q delay modules for h cycles, Q groups of RP analysis modules, each of which includes q=1...Q RP analysis modules for decimation with the corresponding index q=1...Q, each of which consists of a first key, a first OLZ for k bits (symbols), a second key, a decoder, a counter with a threshold of m consecutively arriving "1", a first accompanying matrix, a second accompanying matrix, a second OLZ for k bits (symbols) and a comparison unit. This analog can be used for decoding the received codeword using the "sliding window" method (selection of the SOT). To achieve this, the decoder must be supplemented with a self-opening key that generates an information word upon reception based on the frame synchronization signal. However, the disadvantages of using this analog in decoding include the relatively low speed of the error-correcting code, the impossibility of autonomous use in an asynchronous data transmission system, and the inability to use composite pseudo-random sequences as code words.

The closest to the invention is the “Device for threshold decoding of the Gold sequence” according to the patent RU No. 2832456, H03M 13/03, published on 24.12.2024, containing connected OLZ for 2k bits (symbols), first and second transforming matrices, a “Rest” state analyzer, first, second, third, fourth and fifth keys, first and second accompanying matrices, first, second and third OLZ for k bits (symbols), a counter with a threshold for m consecutively incoming logical “1”, a comparison unit, a signal decoder.

The operating principle of the prototype device is as follows. Initially, the decoding device operates in serial-parallel mode. The output of the first switch receives the signal from its first data input, the output of the third switch receives the signal from its first data input, the signal from the input of the second switch is sent to its first output, and the fourth and fifth switches are open. The input signal (a combination of binary single symbols) at the current clock cycle of the decoding device (t) is fed to the input of a 2k-bit (symbol) OLZ and written to its registers. The values from the 2k registers of the 2k-bit (symbol) OLZ are then fed to the input of the first transformation matrix and the input of the second transformation matrix, where the corresponding values of the Galois field elements are calculated. Next, through the first key, the values calculated in the first transformation matrix are fed from its output to the first information input of the comparison block and to the input of the first accompanying matrix, where the value of the Galois field element is calculated for the next (t + 1) clock cycle of the device. This value is then fed to the input of the first k-bit (symbol) OLZ, where it is stored for one clock cycle. Through the third key, the values calculated in the second transformation matrix are fed from its output to the input of the second accompanying matrix, where the value of the Galois field element is calculated for the next (t + 1) clock cycle of the device, which is then fed to the input of the second k-bit (symbol) OLZ, where it is stored for one clock cycle. On the next clock cycle of the device (t+1), digital symbols from the 2k-bit (symbol) OLZ registers will arrive at the second data input of the comparison unit via the first conversion matrix and the first switch, as well as via the second switch from the output of the first k-bit (symbol) OLZ, previously stored there for one clock cycle. These symbols will match if the input signal is error-free. If the input signals match, a logical signal "1" will appear at the output of the comparison unit. This signal is fed to the input of a counter with a threshold of m consecutive incoming logical "1"s. If m consecutive logical "1"s accumulate, this signal connects the output of the first switch to its second data input, the output of the third switch to its second data input, the input of the second switch to its second output, and closes the fourth switch. Thus, the device switches to the parallel-parallel operating mode, namely, the digital symbols from the registers of the first k-bit (symbol) OLZ are fed through the second switch to the first switch, from the output of which they are fed to the first accompanying matrix, where the states of the registers of the first k-bit (symbol) OLZ are calculated at the next operating cycle of the device and written to the registers of the first k-bit (symbol) OLZ. Digital symbols from the registers of the second k-bit (symbol) OLZ are fed through the fourth switch to the input of the signal decoder and to the third switch, from the output of which they are fed to the second accompanying matrix, where the states of the registers of the second k-bit (symbol) OLZ are calculated at the next operating cycle of the device and written to the registers of the second k-bit (symbol) OLZ. In addition, digital symbols from the registers of the first k-bit (symbol) OLZ are constantly fed to the input of the fifth switch. In the event of a coincidence of the code combination received at the input of the signal decoder with its combination, a cyclic synchronization signal is selected that closes the fifth key, after which the code combination located in the registers of the first OLZ on k bits (symbols) in phase through the fifth key in parallel code is sent to the input of the third OLZ on k bits (symbols) and is written into its registers, which is the result of the device operation. In addition, the cyclic synchronization signal resets the device (switches on the output of the first switch with its first information input, the output of the third switch with its first information input, the input of the second switch with its first output, and opens the fourth switch. The fifth switch opens automatically after the end of the cyclic synchronization signal. If a zero combination is received from the 2k-bit (symbol) OLZ output at the "Idle" state analyzer input, a counter reset signal is sent from the "Idle" state analyzer output to the input of the counter with a threshold of m consecutive logical "1"s at any clock cycle of the device.

A significant drawback of the prototype device is the relatively low probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors due to the lack of an additional mechanism to reduce the probability of errors.

The technical problem is the low probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors due to the lack of an additional mechanism to reduce the probability of errors.

The technical result is an increase in the probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors due to the use of an additional mechanism that analyzes all elements of the code word to most fully utilize its potential redundancy and reduce the probability of errors occurring.

The technical problem is solved by introducing a counter with a threshold of z logical "1", a logical adder, a converter performing the logarithm operation in GF(2 ^k ), a converter performing the antilogarithm operation in GF(2 ^k ), a converter of the inverse elements of GF(2 ^k ), a field convolution calculator in GF(2 ^k ), a sixth key, a random access memory (RAM), a majority element, connecting the output of the first key to the first information input of the field convolution calculator in GF(2 ^k ), the output of the comparison unit to the input of the counter with a threshold of z logical "1" and to the control input of the sixth key, the output of the counter with a threshold of z logical "1" with the third control input of the third key and the third control input of the fourth key, the output of the third OLZ on k bits (symbols) with the first input of the logical adder, the output of the majority element with the second input of the logical adder, the output of the second converting matrices with an input of a converter performing a logarithm operation in GF(2 ^k ), an output of a signal decoder with a control input of a majority element, an output of a converter performing a logarithm operation in GF(2 ^k ) with an input of a converter performing an antilogarithm operation in GF(2 ^k ), an output of a converter performing an antilogarithm operation in GF(2 ^k ) with an input of a converter of inverse elements of GF(2 ^k ), an output of a converter of inverse elements of GF(2 ^k ) with a second information input of a field convolution calculator in GF(2 ^k ), an output of a field convolution calculator in GF(2 ^k ) with an information input of the sixth key, an output of the sixth key with an input of RAM, an output of RAM with an information input of the majority element.

Disclosure of invention

The objective of the invention is to create a device for multi-threshold decoding of Gold sequences based on the allocation of valid sections and majority processing of the calculated combinations, which makes it possible to increase the probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors.

This problem is solved in that the "Gold sequence threshold decoding device" containing connected OLZs of 2k bits (symbols), a "Rest" state analyzer, a first transform matrix, a first key, a first accompanying matrix, a first OLZ of k bits (symbols), a second key, a counter with a threshold of m consecutively arriving logical "1"s, a comparison unit, a fifth key, a third OLZ of k bits (symbols), a second transform matrix, a third key, a second accompanying matrix, a second OLZ of k bits (symbols), a fourth key, a signal decoder supplemented by the introduction of a counter with a threshold of z logical "1"s, a logical adder, a converter performing the logarithm operation in GF(2 ^k ), a converter performing the antilogarithm operation in GF(2 ^k ), a converter of the inverse elements of GF(2 ^k ), a field convolution calculator in GF(2 ^k ), a sixth key, RAM, a majority element, connecting the output of the first key to the first information input of the field convolution calculator in GF(2 ^k ), the output of the comparison unit to the input of the counter with a threshold of z logical "1"s and to the control input of the sixth key, the output of the counter with a threshold of z logical "1"s with the third control input of the third key and the third control input of the fourth key, the output of the third k-bit (symbol) OLZ to the first input of the logical adder, the output of the majority element to the second input of the logical adder, the output of the second conversion matrix to the input of the converter performing the logarithm operation in GF(2 ^k ), the output of the signal decoder to the control input of the majority element, the output of the converter performing the logarithm operation in GF(2 ^k ) to the input of the converter performing the antilogarithm operation in GF(2 ^k ), the output of the converter performing the antilogarithm operation in GF(2 ^k ) with the input of the inverse element converter GF(2 ^k ), the output of the inverse element converter GF(2 ^k ) with the second information input of the field convolution calculator in GF(2 ^k ), the output of the field convolution calculator in GF(2 ^k ) with the information input of the sixth key, the output of the sixth key with the input of the RAM, the output of the RAM with the information input of the majority element.

The 2k-bit (symbol) integrated circuit is implemented on universal shift registers with serial input with serial or parallel writing and serial or parallel reading output, the first digit of which is a JK trigger, and the remaining digits are built on D triggers, equal to the time of passage of 2k bits with a clock frequency of ¹ ( ¹ Digital and analog integrated circuits: reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564IR9).

The "Rest" state analyzer is a two-input logical element implementing the "AND-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LA7).

The first and second transforming matrices are a set of two-input addition circuits mod 2 ¹ ( ¹ Digital and analog integrated circuits: reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LP2) in accordance with the calculated roots of the given characteristic polynomial.

The first, second, third and fourth keys are k two-input bidirectional keys made on p-type MOS transistors, controlled by signals arriving at input C of key ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564KTZ).

The first and second accompanying matrices are a set of two-input addition circuits mod 2 ¹ ( ¹ Digital and analog integrated circuits: reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LP2) in accordance with the feedback of a given characteristic polynomial.

The first, second and third OLZ for k bits (symbols) are implemented on universal shift registers with serial input with serial or parallel writing and serial or parallel reading output, the first digit of which is a JK trigger, and the remaining digits are built on D triggers equal to the passage time of k bits with a clock frequency of ¹ ( ¹ Digital and analog integrated circuits: reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564IR9).

A counter with a threshold for m consecutive incoming logical "1"s and a counter with a threshold for z logical "1"s are two-input logical elements that implement the "OR-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i Svyaz, 1990. 496 p.: ill.) (IC type: 564LE5), two-input logical elements that implement the "NAND-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i Svyaz, 1990. 496 s.: ill.) (IC type: 564LA7) and a four-digit binary counter ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 pp.: ill.) (IC type: 564IE10).

The comparison block is k two-input mod21 addition circuits (*1Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i Svyaz, 1990. 496 p.: ill.) (IC type: 564LP2) and two-input logical elements implementing the OR-NOT function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i Svyaz, 1990. 496 p.: ill.) (IC type: 564LE5).

A logical adder is a set of two-input logical elements that implement the “OR” function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LE5).

The fifth and sixth keys are k two-input logic elements implementing the “AND” function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 133LI1).

The signal decoder is a logical two-input elements implementing the "OR-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i svyaz, 1990. 496 p.: ill.) (IC type: 564LE5), logical two-input elements implementing the "AND-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i svyaz, 1990. 496 p.: ill.) (IC type: 564LA7) and a two-stage synchronous D-trigger ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Edited by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564TM2).

The converter that performs the logarithm operation in GF(2 ^k ), the converter that performs the antilogarithm operation in GF(2 ^k ), the converter of the inverse elements of GF(2 ^k ), the field convolution calculator in GF(2 ^k ) are k two-input mod2 addition circuits ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Ed. by S.V. Yakubovsky. Moscow: Radio i Svyaz, 1990. 496 p.: ill.) (IC type: 564LP2) and two-input logical elements that implement the "AND-NOT" function ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova and etc.; Ed. by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LA7).

The RAM is implemented using integrated circuits ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Edited by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 537RU1).

The majority element is implemented on integrated circuits ¹ ( ¹ Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova et al.; Edited by S.V. Yakubovsky. Moscow: Radio and Communications, 1990. 496 p.: ill.) (IC type: 564LP13), each of which represents three three-input majority elements.

The listed new set of essential features ensures an increase in the probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors due to the use of an additional mechanism that analyzes all elements of the code word to make the most complete use of its potential redundancy and reduce the probability of errors.

The conducted analysis of the state of the art allowed us to establish that there are no analogues characterized by a set of features identical to all the features of the claimed technical solution, which indicates compliance with the patentability condition of “novelty”.

A search of prior art in this and related fields of technology to identify features that match the distinctive features of the claimed invention from the prior art revealed that these features do not clearly follow from the prior art. The prior art also reveals no prior art knowledge of the impact of the transformations contemplated by the essential features of the claimed invention on achieving the stated technical result. Consequently, the claimed invention meets the patentability requirement of "inventive step." Description of the drawings

The claimed device is illustrated by drawings:

Fig. 1 - structural diagram of the receiving side of the device for multi-threshold decoding of Gold sequences based on the allocation of qualifying sections and majority processing of the calculated combinations.

Fig. 2 - experimental dependences of the probability of correct decoding on the probability of a bit error when receiving a code word in a discrete symmetric channel (DSC) without memory with single independent errors, which is a Gold sequence for the prototype device and the claimed device.

The proposed device comprises: a 2k-bit (symbol) OLZ (1), a "Rest" state analyzer (2), a first transform matrix (3), a first key (4), a first accompanying matrix (5), a first k-bit (symbol) OLZ (6), a second key (7), a counter with a threshold of m consecutively arriving logical "1"s (8), a comparison unit (9), a counter with a threshold of z logical "1"s (10), a fifth key (11), a third k-bit (symbol) OLZ (12), a logical adder (13), a second transform matrix (14), a third key (15), a second accompanying matrix (16), a second k-bit (symbol) OLZ (17), a fourth key (18), a signal decoder (19), a converter that performs a logarithm operation in GF(2 ^k ) (20), a converter that performs an antilogarithm operation in GF(2 ^k ) (21), GF(2 ^k ) inverse element converter (22), GF(2 ^k ) field convolution calculator (23), sixth key (24), RAM (25), majority element (26). A 2k-bit (symbol) OLZ (1) is connected to the output of the communication channel with its input, the output of which is connected to the input of the second transforming matrix (14), the input of the first transforming matrix (3) and the input of the “Rest” state analyzer (2), the output of which is connected to the second input of the counter with a threshold of m consecutively incoming logical “1”s (8), the output of the first transforming matrix (3) is connected to the first information input of the first switch (4), the output of which is connected to the first information input of the comparison unit (9), the input of the first accompanying matrix (5) and the first information input of the field convolution calculator in GF(2 ^k ) (23), the output of the counter with a threshold of m consecutively incoming logical “1”s (8) is connected to the second control input of the first switch (4), the second output of the second switch (7) is connected to the second information input of the first switch (4), the output of the signal decoder (19) is connected to the first control input of the first switch (4), the output of the first accompanying matrix (5) connected to the input of the first OLZ for k bits (symbols) (6), the output of which is connected to the information input of the second switch (7) and the information input of the fifth switch (11), the output of the counter with a threshold of m consecutive incoming logical "1"s (8) is connected to the second control input of the second switch (7), the output of the signal decoder (19) is connected to the first control input of the second switch (7), the first output of which is connected to the second information input of the comparison unit (9), the first input of the counter with a threshold of m consecutive incoming logical "1"s (8) is connected to the output of the comparison unit (9), the output of the counter with a threshold of m consecutive incoming logical "1"s (8) is connected to the second control input of the third switch (15) and the second control input of the fourth switch (18), the output of the comparison unit (9) is connected to the control input of the sixth switch (24) and to the input of the counter with a threshold of z logical "1"s (10), the output of which is connected to the third control input of the third switch (15) and the third control input of the fourth key (18), the output of the signal decoder (19) is connected to the control input of the fifth key (11), the output of which is connected to the input of the third k-bit (symbol) OLZ (12), the output of which is connected to the first input of the logical adder (13), the second input of which is connected to the output of the majority element (26), the output of the second transform matrix (14) is connected to the input of the converter that performs the logarithm operation in GF(2 ^k ) (20) and to the first information input of the third key (15), the output of which is connected to the input of the second accompanying matrix (16), the output of the fourth key (18) is connected to the second information input of the third key (15), the output of the signal decoder (19) is connected to the first control input of the third key (15), the output of the second accompanying matrix (16) is connected to the input of the second k-bit (symbol) OLZ (17), the output of which is connected to the information input the fourth key (18), the output of which is connected to the input of the signal decoder (19), the output of which is connected to the first control input of the fourth key (18) and to the control input of the majority element (26), the output of the converter performing the logarithm operation in GF(2 ^k ) (20) is connected to the input of the converter performing the antilogarithm operation in GF(2 ^k ) (21), the output of which is connected to the input of the converter of the inverse elements of GF(2 ^k ) (22), the output of which is connected to the second information input of the field convolution calculator in GF(2 ^k ) (23), the output of which is connected to the information input of the sixth key (24), the output of which is connected to the input of the RAM (25), the output of which is connected to the information input of the majority element (26).

The size of the OLZ (k) per k bits (symbols) is set equal to the size of the generator (LRR) that forms the information block during transmission. The generator size is selected based on the requirements for the decoding device in the data transmission equipment.

The size of the square (accompanying) matrix k × k bits, which performs the LRR function, is determined by the size of the received information block (k).

The structural diagram of the accompanying matrix corresponds to the feedback vector of the selected characteristic polynomial (polynomial).

The structural diagram of the transforming (rectangular) matrix 2k × k bits corresponds to the roots of the selected characteristic polynomial (polynomial), which are calculated before the synthesis of the device [Kognovitsky O.S. Theory, methods and algorithms for solving problems in telecommunications based on the dual basis and recurrent sequences: dis. Doctor of Technical Sciences: 05.12.13. - SPbSUT, 2011. - 427 p., pp. 39-54].

The value m of the counter with a threshold of m consecutive incoming logical “1”s is selected in accordance with the requirements imposed on the value of P _ZOT (the probability of correct allocation of the scoring segment) under interference conditions in the communication channel, but not less than 1. In most cases, the value m is set comparable to the size of the OLZ (k) per k bits (symbols).

The value z of the counter with a threshold of z logical “1” is selected in accordance with the requirements imposed on the value of P _ЗОТ (the probability of correct selection of the scoring segment) under interference conditions in the communication channel, but not less than 1 and z<m.

The industrial application of the invention is due to the fact that it can be implemented using a modern element base, achieving the purpose specified in the invention.

An experimental verification of the characteristics of a multithreshold decoding device for Gold sequences based on the allocation of valid sections and majority processing of the calculated combinations was performed on a computer using the Anaconda 3 object-oriented programming environment in Python 3.7 and yielded positive results. Simulating 10,000 repetitions revealed that the experimental dependences of the probability of correct codeword decoding on the bit error probability in a memoryless BSC with single independent errors for the proposed device demonstrate a probability advantage over similar dependences for the prototype device (Fig. 2). Consequently, while maintaining the requirements for the probability of correct decoding, the proposed device ensures reliable information transmission on communication channels with a higher probability of single independent errors.

The technical result of increasing the probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors is achieved through the use of an additional mechanism that analyzes all elements of the code word to fully utilize its potential redundancy and reduce the probability of errors.

The operating principle of the proposed device is as follows. Initially, the decoding device operates in a serial-parallel mode. The signal from the first information input is received at the output of the first switch (4), the signal from the first information input is received at the output of the third switch (15), the signal from the input of the second switch (7) is received at its first output, the fourth switch (18), the fifth switch (11) and the sixth switch (24) are open. The input signal (a combination of 2k unit bits (symbols)) at the current clock cycle of the decoding device (t) is received sequentially from the communication channel to the input of the 2k-bit (symbol) OLZ (1) and is written into its registers, and then the values from the 2k registers of the 2k-bit (symbol) OLZ (1) are sent to the input of the first transformation matrix (3) and the input of the second transformation matrix (14), where the corresponding values of the Galois field elements are calculated. Next, through the first key (4), the values calculated in the first transform matrix (3) are fed from its output to the first information input of the comparison unit (9), to the first information input of the field convolution calculator in GF(2 ^k ) (23) and to the input of the first accompanying matrix (5); in the first accompanying matrix (5), the value of the Galois field element is calculated at the next (t+1) clock cycle of the device operation, which is then fed to the input of the first OLZ for k bits (symbols) (6), where it is stored for one clock cycle. Through the third key (15), the values calculated in the second transform matrix (14) are fed from its output to the input of the second accompanying matrix (16) and to the input of the converter that performs the logarithm operation in GF(2 ^k ) (20). In the second accompanying matrix (16), the value of the Galois field element is calculated at the next (t+1) clock cycle of the device operation, which is then fed to the input of the second k-bit (symbol) OLZ (17), where it is stored for one clock cycle. In the converter that performs the logarithm operation in GF(2 ^k ) (20), the value of the ordinal number of the Galois field element is calculated, which is then fed to the input of the converter that performs the antilogarithm operation in GF(2 ^k ) (21), in which the value of the Galois field element of the first generator that forms the segment of the first M-sequence from the information word is calculated, corresponding in time to the Galois field of the second generator that forms the segment of the second M-sequence that determines the phase of the processed pseudorandom Gold sequence, which is then fed to the input of the inverse element converter GF(2 ^k ) (22), in which the value of the corresponding inverse element of the Galois field is calculated. Next, the value calculated in the inverse element converter GF(2 ^k ) (22) is fed to the second information input of the field convolution calculator in GF(2 ^k ) (23). The values obtained in the field convolution calculator in GF(2 ^k ) (23) are constantly fed to the information input of the sixth switch (24). At the next operation cycle of the device (t+1), digital symbols from the 2k-bit (symbol) OLZ registers (1) will be fed to the first information input of the comparison block (9) through the first transformation matrix (3) and the first switch (4), and symbols from the output of the first k-bit (symbol) OLZ (6), stored there earlier for one cycle, will be fed to the second information input of the comparison block (9), which will coincide if there are no errors in the input signal. When the input signals coincide, a logical signal "1" appears at the output of the comparison unit (9), which is fed to the input of the counter with a threshold of m consecutively incoming logical "1"s (8), to the input of the counter with a threshold of z logical "1"s (10), and to the control input of the sixth switch (24). The incoming logical signal "1" closes the sixth switch (24), after which the code combination obtained in the field convolution calculator in GF(2 ^k ) (23) is fed in phase through the sixth switch (24) to the input of the RAM (25) and written there. Then, the values written in the RAM (25) are simultaneously fed in sequential code to the information input of the majority element (26). The counter with a threshold of z logical "1"s (10), in the case of accumulation of z logical "1"s, switches on the output of the third switch (15) with its second information input and closes the fourth switch (18). In this way, the device switches to a parallel-parallel operating mode, namely, digital symbols from the registers of the second OLZ with k bits (symbols) (17) through the fourth key (18) are fed to the input of the signal decoder (19) and to the second information input of the third key (15), from the output of which they are fed to the second accompanying matrix (16), where the states of the registers of the second OLZ with k bits (symbols) (17) are calculated in the next clock cycle of the device and are written into the registers of the second OLZ with k bits (symbols) (17). In case of coincidence of the code combination received at the input of the signal decoder (19) with the combination of this signal decoder (19), a cyclic synchronization signal is extracted, which is received at the control input of the majority element (26), which, after receiving the cyclic synchronization signal, performs a bit-by-bit comparison of the majority of code combinations received from the output of the RAM (25), and forms a code combination, which is received at the input of the logical adder (13), which is the result of the majority processing of the calculated combinations of the device. In parallel with this, the counter with a threshold for m consecutively received logical "1"s (8), in case of accumulation of m consecutive logical "1"s, switches on the output of the first switch (4) with its second information input, the output of the third switch (15) with its second information input, the input of the second switch (7) with its second output and closes the fourth switch (18). In this way, the device switches to the parallel-parallel operating mode, namely, the digital symbols from the registers of the first k-bit (symbol) OLZ (6) via the second key (7) are sent to the first key (4), from the output of which they are sent to the first accompanying matrix (5), where the states of the registers of the first k-bit (symbol) OLZ (6) are calculated on the next operating cycle of the device and are written into the registers of the first k-bit (symbol) OLZ (6), and the digital symbols from the registers of the second k-bit (symbol) OLZ (17) via the fourth key (18) are sent to the input of the signal decoder (19) and to the second information input of the third key (15), from the output of which they are sent to the second accompanying matrix (16), where the states of the registers of the second k-bit (symbol) OLZ (17) are calculated on the next operating cycle of the device and are written into the registers of the second k-bit (symbol) OLZ (17). In addition, digital symbols from the registers of the first k-bit (symbol) OLZ (6) are constantly fed to the information input of the fifth key (11). In the event of a coincidence of the code combination fed to the input of the signal decoder (19) with the combination of this signal decoder (19), a cyclic synchronization signal is extracted, closing the fifth key (11), after which the code combination located in the registers of the first k-bit (symbol) OLZ (6) is fed in phase through the fifth key (11) in parallel code to the input of the third k-bit (symbol) OLZ (12) and is written into its registers and then, on the next clock cycle of the device, is fed to the input of the logical adder (13), which is the result of the device operation. In addition, the cyclic synchronization signal transfers the device to the initial state (switches on the output of the first switch (4) with its first information input, the output of the third switch (15) with its first information input, the input of the second switch (7) with its first output, and opens the fourth switch (18). The fifth switch (11) opens independently after the end of the receipt of the cyclic synchronization signal, and the sixth switch (24) opens independently after the end of the receipt of the logical signal "1". In the event of a zero combination being received from the output of the 2k-bit (symbol) OLZ (1) to the input of the "Idle" state analyzer (2), a signal to reset the counter state at any clock cycle of the device is sent from the output of the "Idle" state analyzer (2) to the input of the counter with a threshold of m consecutive incoming logical "1"s (8).

The invention, by using an additional mechanism that analyzes all elements of a code word to make the most of its potential redundancy and reduce the likelihood of errors, makes it possible to increase the probability of correct decoding of a code word on a discrete symmetric communication channel with single independent errors.

Fig. 2 shows that for a fixed bit error probability in a memoryless DSC, the probability of correct decoding for the claimed device is higher than for the prototype device.

Claims (1)

A device for multithreshold decoding of Gold sequences (GS) based on the allocation of valid sections and majority processing of the calculated combinations, containing a single-channel delay line (DL) for 2 k bits (symbols), a "Rest" state analyzer, a first transform matrix, a first key, a first accompanying matrix, a first DL for k bits (symbols), a second key, a counter with a threshold for m consecutively incoming logical "1"s, a comparison unit, a fifth key, a third DL for k bits (symbols), a second transform matrix, a third key, a second accompanying matrix, a second DL for k bits (symbols), a fourth key, a signal decoder, connections of the output of the DL for 2 k bits (symbols) to the input of the "Rest" state analyzer, the input of the first transform matrix and the input of the second transform matrix, the output of the "Rest" state analyzer to the second input of the counter with a threshold for m consecutively incoming logical "1"s, the output of the first transform matrix with the first information input of the first switch, the output of the first switch with the first information input of the comparison unit and the input of the first accompanying matrix, the output of the counter with a threshold of m consecutively incoming logical "1"s with the second control input of the first switch, the second output of the second switch with the second information input of the first switch, the output of the signal decoder with the first control input of the first switch, the output of the first accompanying matrix with the input of the first k- bit (symbol) OLZ, the output of the first k- bit (symbol) OLZ with the information input of the second switch and the information input of the fifth switch, the output of the counter with a threshold of m consecutively incoming logical "1"s with the second control input of the second switch, the output of the signal decoder with the first control input of the second switch, the first output of the second switch with the second information input of the comparison unit, the first input of the counter with a threshold of m consecutively incoming logical "1"s with the output of the comparison unit, the output of the counter with a threshold of m consecutively incoming logical "1"s with the second control input of the third switch and the second control input of the fourth key, the output of the signal decoder with the control input of the fifth key, the output of the fifth key with the input of the third OLZ on k bits (symbols), the output of the second conversion matrix with the first information input of the third key, the output of the third key with the input of the second accompanying matrix, the output of the fourth key with the second information input of the third key, the output of the signal decoder with the first control input of the third key, the output of the second accompanying matrix with the input of the second OLZ on k bits (symbols), the output of the second OLZ on k bits (symbols) with the information input of the fourth key, the output of the fourth key with the input of the signal decoder, the output of the signal decoder with the first control input of the fourth key, characterized in that it is supplemented by the introduction of a counter with a threshold of z logical "1", a logical adder, a converter performing a logarithm operation in GF (2 ^k ), a converter performing an antilogarithm operation in GF (2 ^k ), the GF (2 ^k ) inverse element converter, the GF (2 ^k ) field convolution calculator, the sixth key, the random access memory (RAM), the majority element, the connection of the output of the first key to the first information input of the GF (2 ^k ) field convolution calculator, the output of the comparison unit to the input of the counter with a threshold of z logical "1"s and to the control input of the sixth key, the output of the counter with a threshold of z logical "1"s with the third control input of the third key and the third control input of the fourth key, the output of the third k- bit (symbol) OLZ with the first input of the logical adder, the output of the majority element with the second input of the logical adder, the output of the second transform matrix with the input of the converter performing the logarithm operation in GF (2 ^k ), the output of the signal decoder with the control input of the majority element, the output of the converter performing the logarithm operation in GF (2 ^k ) with the input of the converter performing the antilogarithm operation in GF (2 ^k ), the output of the converter performing the antilogarithm operation in GF (2 ^k ) with the input of the converter of the inverse elements of GF (2 ^k ), the output of the converter of the inverse elements of GF (2 ^k ) with the second information input of the field convolution calculator in GF (2 ^k ), the output of the field convolution calculator in GF (2 ^k ) with the information input of the sixth key, the output of the sixth key with the input of the RAM, the output of the RAM with the information input of the majority element.