RU2629659C1 - Method of manufacturing semiconductor appliance - Google Patents

Method of manufacturing semiconductor appliance Download PDF

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Publication number
RU2629659C1
RU2629659C1 RU2016145895A RU2016145895A RU2629659C1 RU 2629659 C1 RU2629659 C1 RU 2629659C1 RU 2016145895 A RU2016145895 A RU 2016145895A RU 2016145895 A RU2016145895 A RU 2016145895A RU 2629659 C1 RU2629659 C1 RU 2629659C1
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nm
layer
cm
temperature
growth rate
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RU2016145895A
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Russian (ru)
Inventor
Гасан Абакарович Мустафаев
Абдулла Гасанович Мустафаев
Арслан Гасанович Мустафаев
Наталья Васильевна Черкесова
Original Assignee
Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ)
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Priority to RU2016145895A priority Critical patent/RU2629659C1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/203Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using physical deposition, e.g. vacuum deposition, sputtering
    • H01L21/2033Epitaxial deposition of elements of Group IV of the Periodic System, e.g. Si, Ge
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/205Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
    • H01L21/2053Expitaxial deposition of elements of Group IV of the Periodic System, e.g. Si, Ge

Abstract

FIELD: electricity.
SUBSTANCE: in method of manufacturing a semiconductor appliance, a base-collector heterojunction is formed by growing an n-layer of Si 400 nm thick at the temperature of 1000°C with the growth rate of 2.5 nm/s, with the concentration of arsenic As (3-5)*1016 cm-3, followed by growing a p-layer of SiGe 50 nm thick with the growth rate of 0.5 nm/s at the temperature of 625°C, with the boron concentration B (2-4)*1016 cm-3, the pressure 3*10-7 Pa.
EFFECT: reducing the density of defects, improving the parameters and the reliability, increasing the percentage of yield of suitable appliances.
1 tbl

Description

The invention relates to the field of production technology of semiconductor devices, in particular to the technology of manufacturing devices with a heterostructure with reduced defectiveness.

A known method of manufacturing a GaAs / Si heterostructure by forming a multilayer transition structure, according to which, in order to prevent the dislocation from spreading between the GaAs layer and the silicon substrate, intermediate AIGaAs layers formed by MBE or PFHO from the vapor phase of organometallic compounds are introduced [Application 1293611, Japan, MKI H01L 21 / 205].

In such multilayer structures, due to the low manufacturability of the process of forming the layers, the defectiveness increases and the electrophysical parameters of the devices deteriorate.

A known method of manufacturing a device with a heterostructure on a semi-insulating GaAs substrate with the deposition of an epitaxial layer of n + GaAs: Si on it (emitter of a bipolar transistor with an impurity concentration of 5 * 10 18 cm -3 ) and n - GaAs: Si (10 17 cm -3 ). Next, an n - Ge: Si epitaxial layer is grown (collector 5 * 10 16 cm -3 ); the lower part of this layer due to Ga diffusion from the underlying GaAs layer acquires p + type conductivity [US Patent 5047365, MKI H01L 21/20]. Then, by implanting B + ions, p + regions (base layers) are formed on the sides of the Ge layer, and high-resistance insulating regions are formed on the sides of the n - GaAs layer.

The disadvantages of the method are:

- increased density of defects;

- low manufacturability;

- low gain values.

The problem solved by the invention is to reduce the density of defects, ensure manufacturability, improve parameters, increase reliability and increase the percentage of yield.

The problem is solved by the formation of a base-collector heterostructure by growing an n-layer of Si with a thickness of 400 nm at a temperature of 1000 ° C with a growth rate of 2.5 nm / s, with a concentration of arsenic As (3-5) * 10 16 cm -3 , followed by growing p -SiGe layer with a thickness of 50 nm with a growth rate of 0.5 nm / s at a temperature of 625 ° C, with a boron concentration of B (2-4) * 10 16 cm -3 , pressure 3 * 10 -7 Pa.

The technology of the method consists in the following: on a semi-insulating GaAs substrate, after applying an n + GaAs: Si and n - GaAs: Si layer on it, an n-layer of Si is grown with a thickness of 400 nm at a temperature of 1000 ° C with a growth rate of 2.5 nm / s, s the concentration of arsenic As (3-5) * 10 16 cm -3 . Then a 50-nm-thick SiGe p-layer is grown with a growth rate of 0.5 nm / s at a temperature of 625 ° C, with a boron concentration of B (2-4) * 10 16 cm -3 , a pressure of 3 * 10 -7 Pa was fed into the reactor SiH 2 Cl 2 and Ge pairs in a mixture with H 2 . For doping, ASH 3 and B 2 H 6 were used . Next, contacts were formed using standard technology.

According to the proposed method, semiconductor devices were manufactured and investigated. The processing results are presented in the table.

Figure 00000001

Figure 00000002

Experimental studies have shown that the yield of suitable structures on a batch of plates formed in the optimal mode increased by 19.3%.

Effect: reducing the density of defects, ensuring manufacturability, improving parameters, improving reliability and increasing the percentage of yield.

The stability of the parameters over the entire operating temperature range was normal and consistent with the requirements.

The proposed method of manufacturing a semiconductor device by forming a base-collector heterostructure by growing an n-layer of Si with a thickness of 400 nm at a temperature of 1000 ° C with a growth rate of 2.5 nm / s, with an arsenic concentration of As (3-5) * 10 16 cm -3 , s subsequent growth of a p-layer of SiGe with a thickness of 50 nm with a growth rate of 0.5 nm / s at a temperature of 625 ° C, with a boron concentration of B (2-4) * 10 16 cm -3 , pressure 3 * 10 -7 Pa allows to increase the percentage yield.

Claims (1)

  1. A method of manufacturing a semiconductor device, including a substrate, an epitaxial layer, doping processes, characterized in that the base-collector heterojunction is formed by growing an n-layer of Si with a thickness of 400 nm at a temperature of 1000 ° C with a growth rate of 2.5 nm / s, with an arsenic concentration As (3-5) * 10 16 cm -3 , followed by growing a 50 nm thick SiGe p-layer with a growth rate of 0.5 nm / s at a temperature of 625 ° C, with a boron concentration of B (2-4) * 10 16 cm -3 , pressure 3 * 10 -7 Pa.
RU2016145895A 2016-11-22 2016-11-22 Method of manufacturing semiconductor appliance RU2629659C1 (en)

Priority Applications (1)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047365A (en) * 1988-03-25 1991-09-10 Nec Corporation Method for manufacturing a heterostructure transistor having a germanium layer on gallium arsenide using molecular beam epitaxial growth
EP0779652A2 (en) * 1995-12-12 1997-06-18 Lucent Technologies Inc. Method for making a heterojunction bipolar transistor
WO2001024249A1 (en) * 1999-09-29 2001-04-05 France Telecom Method for preventing diffusion of boron in silicon by ion implantation of carbon
US6362065B1 (en) * 2001-02-26 2002-03-26 Texas Instruments Incorporated Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer
US6586297B1 (en) * 2002-06-01 2003-07-01 Newport Fab, Llc Method for integrating a metastable base into a high-performance HBT and related structure
RU2507633C1 (en) * 2012-09-24 2014-02-20 Федеральное Государственное Унитарное Предприятие "Научно-Производственное Предприятие "Пульсар" Bipolar transistor based on heteroepitaxial structures and method of its realisation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047365A (en) * 1988-03-25 1991-09-10 Nec Corporation Method for manufacturing a heterostructure transistor having a germanium layer on gallium arsenide using molecular beam epitaxial growth
EP0779652A2 (en) * 1995-12-12 1997-06-18 Lucent Technologies Inc. Method for making a heterojunction bipolar transistor
WO2001024249A1 (en) * 1999-09-29 2001-04-05 France Telecom Method for preventing diffusion of boron in silicon by ion implantation of carbon
US6362065B1 (en) * 2001-02-26 2002-03-26 Texas Instruments Incorporated Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer
US6586297B1 (en) * 2002-06-01 2003-07-01 Newport Fab, Llc Method for integrating a metastable base into a high-performance HBT and related structure
RU2507633C1 (en) * 2012-09-24 2014-02-20 Федеральное Государственное Унитарное Предприятие "Научно-Производственное Предприятие "Пульсар" Bipolar transistor based on heteroepitaxial structures and method of its realisation

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