RU2553091C2 - System for two-way high-speed short-wave radio communication - Google Patents

Abstract

FIELD: physics, communications.

SUBSTANCE: invention relates to radio communication and can be used in constructing high-speed two-way radio links operating at one frequency when transmitting discrete or analogue signals. A system for two-way high-speed short-wave radio communication consists of two transceiving sets, each comprising an analogue signal source, an analogue signal receiver, a signal compressor, a signal expander, a control unit, a modulator, a transmitter, a transceiving antenna, a first input signal switch, a demodulator, a clock signal demodulator, a receiver, wherein each transceiving set further includes an encoder, a decoder, a discrete signal source, a discrete signal receiver, a first radio signal switch, an output signal switch, a digital selective call (DSC) signal generator and a second input signal switch.

EFFECT: high link throughput and more radio subscribers that can operate at the same operating frequency.

8 cl, 2 dwg

Description

The invention relates to the field of radio communications and can be used in the construction of high-speed duplex radio lines operating at the same frequency when transmitting (receiving) discrete or analog signals.

A known system of duplex radio communication, consisting of two transceiver sets, each of which contains a series-connected signal source, modulator, transmitter, as well as series-connected receiver, demodulator, receiver, and a transceiver antenna, the input and output of which is connected to the output of the transmitter and input receiver, respectively, switching each of the mentioned sets to the “receive” or “transmission” mode is performed manually [1].

Of the known duplex radio communication systems, the closest in essence to the tasks to be solved and most of the matching features is the duplex radio communication system [2], which consists of two transceiver sets, each of which contains an analog signal source and an analog signal receiver, a signal compression device and a signal expansion device, a unit control, the output of which is connected to the control input of the signal compression device, a modulator, a series-connected transmitter and a transceiver antenna, as well as first switch input signal, a demodulator whose output is coupled to an input of the signal expansion unit, the demodulator clock signal, whose output is connected to the input of the control unit, and a receiver, whose output is connected in parallel with the input of the demodulator and the input of the demodulator clock.

Consider the disadvantages of the known duplex radio communication system [2] when working in a short-wave (KB) radio channel.

Each transceiver kit of this system contains two modulators: a modulator of the main transmitted signal and a clock signal modulator to enable synchronous separation in time of the tuning of the radio from the “receive” mode to the “transmit” mode or vice versa.

For more noise-tolerant selection of a clock signal from messages received by each transceiver set of quanta, in [2] it is proposed to use various types of modulation of the main transmitted signal and the clock signal:

- when transmitting the main telephone (TLF) signal - an analog type of modulation, for example, using the radiation class АЗЕ - two-way telephony with amplitude modulation of the carrier frequency [3];

- when transmitting a clock signal - a discrete type of modulation, for example, frequency telegraphy F1B-500, 300 Baud.

Switching of various analog modulating signals to the same input is possible only when the transmitter exciter has input of external information with any kind of modulation at an intermediate frequency (IF). For example, modern pathogens of the Priboy type, R-170 VM [4] and pathogens of the old park of R-170V type (technical specifications TsL2.209023 TU) have an IF input - at a frequency of 128 kHz. In accordance with [2], the main and synchronizing signals must be generated on the inverter and switched to the input of exactly this type of pathogen.

It is known that in order to increase the energy of the transmitted resulting signal, it is necessary to ensure its formation without phase discontinuity and spasmodic changes in the amplitude of the carrier wave [5], in this case, at the moments when the type of modulation changes. A necessary condition for eliminating abrupt phase changes is the use of a single reference oscillator to form on the inverter both the main transmitted signal and the clock signal.

However, in the known duplex radio communication system, the formation of the main and synchronizing modulating oscillations is carried out from various autonomous modulators (there are no electrical connections between the modulators). Thus, the output oscillations of these modulators, which can be formed only from autonomous reference generators in the composition of these modulators, will differ both in phase and in frequency (within the limits due to the instability of the used generators and the accuracy of their initial frequency adjustment).

Accordingly, at the moments of switching of the modulating signals, the phase and amplitude of the resulting signal at the input of the transmitter exciter can change abruptly; moreover, the frequency of the transmitted signal can be slightly different from the frequency of the main signal during the transmission of the clock signal.

Sudden changes in the phase or amplitude of the signal at the input of the pathogen lead to short-term attenuation of the transmitted resulting signal due to transients during further passage of the signal through narrow-band selective pathogen circuits [5].

When a clock signal is transmitted at the beginning of each transmitted quantum of the message, abrupt changes in the phase and amplitude of the carrier wave will lead to a decrease in the energy of the main transmitted signal at the initial time intervals of the generated signal quanta; when a clock signal is transmitted at the end of each transmission quantum, to a decrease in the energy of the transmitted clock signal at the initial time segments of the transmitted broadcast clocks. In both cases, these phenomena, including changes in the frequency of the emitted signal, are undesirable, since they reduce the noise immunity of the reception.

Implementation of the required method of generating the resulting signal in digital form with the digital stream supplied to the digital input of a modern exciter of the R-170 VM type via Ethernet [4] is not possible with this structural design of the well-known duplex radio communication system.

Another disadvantage of the known duplex radio communication system is that the introduction of excess synchronizing information into the transmitted signal (of any kind) leads to a decrease in the communication channel throughput, and also that measures are not taken to suppress unwanted radio emissions of a noise and harmonic nature of the transmitter at the receiver input at “receive” time intervals, which reduces the communication range.

The disadvantage is that it is necessary to expand the bandwidth when transmitting and receiving signals at least twice due to the compression of the transmitted signal twice. For example, for transmitting (receiving) an analog TLF signal by the traditional method, a single-band signal in the upper sideband with amplitude modulation of the radiation class J3E, H3E or R3E [3] with a passband of 3100 Hz is required.

To transmit the same signal using the known system, a two-band signal of the AZE emission class will be required, which will lead to a decrease in the noise immunity of the main signal due to the expansion of the passband of the filter for the main selection of the TLF signal at reception.

In addition, a significant drawback of the known duplex radio communication system is the fact that, when working in a short-wave (KB) radio channel, the structural construction of the transceiver kits of this system cannot ensure the exchange of high-speed data using sources and receivers of a discrete signal, and allows for the exchange of analog only telephone messaging using analog sources and receivers (for example, two microphones and two phones). To prove this statement, we analyze the possibility of the known system working in the KB radio channel using both analog and discrete sources and signal receivers.

As you know, the main obstacle to increasing the transmission speed of binary information on the KB channel is multipath. In this case, the received signal is a combination of components (rays) reflected from various layers of the ionosphere. The number of rays at the receiving point and the magnitude of the multipath interval are determined by the path length, the choice of the operating frequency, and the state of the ionosphere [6, 7]. At frequencies close to the optimal operating frequency (ORC), two beams are often observed, at frequencies much lower than the ORC, the number of beams increases to four, five or more. The magnitude of the multipath interval for KB lies within 2-4 ms, reaching in rare cases large values. In this case, the amplitudes of the rays are subject to fading, and the relations between them can be different and vary in time.

Consider the operation of the well-known duplex radio communication system in a multipath KB channel using traditional methods for transmitting and receiving analog messages. For example, using modern exciters of the R-170 VM type [4]: one for transmitting the main TLF signal (Aze emission class), the other for transmitting the clock signal using frequency telegraphy F1B-500 at a speed of 300 Baud, as recommended in [2] (formed on the inverter and switched to the input of the inverter of the transmitter exciter).

To receive the main TLF signal, as well as receive and demodulate the clock signal, we will use the R-170 PM receiver, which has separate outputs [4]:

- to headphones when receiving TLF signals;

- to the recording equipment when receiving telegraph signals.

With the traditional single-channel method of receiving and demodulating telegraph signals (autocorrelation reception [8]) and with the duration of the elementary sending (binary element) of the signal much longer than the delay time comparable in level of the rays, satisfactory reception of telegraph signals (in the case under consideration, clock signals) is provided: the value of the edge (telegraphic) distortions of the demodulated signal due to multipath and additive interference (noise) do not exceed the correcting ability of the device regenerator state in the demodulator, restoring the true position of the boundaries of the received binary signal [8].

As the duration of the signal element decreases (the transmission speed increases) or the delay between comparable beams increases (when working on KB paths of different lengths), the edges of the received packets are “washed out” at separate time intervals (when the levels of different beams are comparable) or the sequence of received packets shifts in time in the direction of advancing or lagging depending on which of the rays (leading or lagging) at other time intervals exceeds the level w (no less than a certain amount), any other ray. For this reason, a relatively low sync signal transmission rate of 300 Baud (duration of the signal element 3.3 ms) was recommended in [2].

In the known duplex radio communication system, when transmitting an analogue TLF signal, changes in the temporal position of the quanta of the received signal in accordance with changes in the temporal position of the received clock signal do not significantly affect the quality of auditory reception, since the human hearing aid is little sensitive to phase distortion of the signal [8] (after " stitching "quanta of a signal in a signal expansion device).

However, if in the known system instead of an analog TLF signal from the output of the signal source, a discrete binary signal is transmitted, for example, at a speed of 600 bit / s, which, after compression in the signal compression device, must be supplied to the modulator input at a speed of 1200 bit / s, then quanta of the resulting signal generated using traditional modulation methods (for example, using the radiation class G1B (OFT) to transmit the main discrete signal at a speed of 1200 bit / s - the duration of the signal element is 0.83 ms, and class F1B-500 for transmitting a sync signal with a speed of 300 Baud - 3.3 ms, as recommended in [2]), will be unsuitable for performing duplex radio communication in a multipath KB channel.

The fact is that when the difference in the path of individual rays exceeds the duration of the elementary transmission, specific errors may appear in segments or quanta of the demodulated binary sequence in the form of inserts or drops of the corresponding number of characters when changing the beam with the maximum level. Accordingly, when “distorting” the distorted quanta of a binary signal in a signal expansion device, the binary sequence generated at the reception may be completely unsuitable for the receiver of the discrete signal.

Moreover, the structural construction of the well-known duplex radio communication system cannot fundamentally provide synchronous operation of the source and receiver of the discrete signal, which can be considered as terminal equipment (transmitting and receiving) of two transceiver sets interacting on the KB channel.

To implement the synchronous operation of the transmitting and receiving terminal equipment of a radio communication system, clock and cycle synchronization devices are required, and it should also be possible to set each transceiver set in the mode of a master or an initial communication session.

In the known duplex radio communication system this is not provided, i.e. the structural construction of this system cannot claim the universality of the use of various sources and receivers of signals. Thus, taking into account the above, it is confirmed that this system is designed for duplex radio communication using sources of only analog signals. The tasks to which the invention is directed - a system of duplex high-speed short-wave radio communications, are:

- increasing the noise immunity of receiving telephone messages by reducing the bandwidth by at least two times and implementing a modulator and demodulator as part of the system based on the application of the compression method with orthogonal frequency division (OFDM - Orthogonall Frequency Division Multiplexing) with the highest frequency filling density range when using OFDM signals;

- an increase in the bandwidth of the communication channel due to the exclusion of a special clock signal introduced into the resulting transmitted signal, and the use of an OFDM signal with high spectral density for duplex radio communication instead of an analog TLF signal with a significantly lower spectral density;

- expanding the functionality of the system due to the introduction of additional technical means and the use of OFDM signals, which provide duplex exchange on a multipath KB channel both by telephone and by high-speed discrete messages.

- an increase in the number of radio subscribers that can operate at the same operating frequency due to the introduction of technical means for transmitting and receiving digital selective calling (DSC) signals;

- increasing the communication range by reducing the noise level of the transmitter at the input of the receiver at time intervals "reception".

The solution to these problems is achieved by the fact that in the system of a duplex high-speed short-wave communication system consisting of two transceiver sets, each of which contains an analog signal source and an analog signal receiver, a signal compression device and a signal expansion device, a control unit, the output of which is connected to the control input of the device signal compression, modulator, serially connected transmitter and transceiver antenna, as well as the first input signal commutator, demodulated the output of which is connected to the input of the signal expansion device, a clock demodulator, the output of which is connected to the input of the control unit, and a receiver whose output is connected in parallel with the demodulator input and the input of the clock demodulator, are additionally equipped with an encoder, the input of which is connected to the source output, in each transceiver set an analog signal, and a decoder, the output of which is connected to the input of the receiver of the analog signal, a discrete signal source and a discrete signal receiver, the first switch p dio signals, output signal commutator, input, the first and second outputs of which are connected respectively to the output of the signal expansion device, to the input of the decoder and to the input of the receiver of the discrete signal, and the control input of the output signal commutator, which is the control input source signal of the transceiver kit, is combined with the control input the first input signal switch, the output, the first and second inputs of which are connected respectively to the input of the signal expansion device, with the output of the encoder and with the output and of the discrete signal point, in addition, a digital selective signal (DSC) signal conditioner and a second input signal commutator are introduced, the output of which is connected to the modulator input, the output of which is connected to the transmitter input, the output of which is additionally connected to the signal input of the first radio signal commutator, block output control is additionally connected to the control input of the first radio signal switch, with an additional input of the transmitter and with an additional input of the demodulator, and the first additional input One of the control unit, which is the input of the DSC signal transmission control of the transceiver kit, is combined with the control input of the second input signal switch and with the control input of the DSC signal generator, the output of which is connected to the first input of the second input signal switch, the second input of which is connected to the output of the signal compression device, the first and second additional outputs of which are connected respectively to the clock input of the DSC signal conditioner and to the second additional input of the control unit, the third the additional input of which is the input of the installation of the transceiver set into the signal reception mode, and its fourth additional input is connected to the additional output of the signal expansion device, the input of which is additionally connected to the fifth additional input of the control unit.

In each transceiver set, the signal compression device consists of a first memory block, the input and output of which are respectively the input and output of the signal compression device, the first write counter, the first read counter, the first phasing block and the first clock synchronization block, the input of which is combined with the input of the first block memory, and its first and second outputs are connected respectively to the clock input of the first write counter and to the clock input of the first read counter, the output of which is combined with the control the reading input of the first memory unit and the first input of the first phasing unit, the second input of which is combined with the recording control input of the first memory unit and with the output of the first recording counter, the control input of which is connected to the first output of the first phasing unit, the second output of which is connected to the control input of the first read counter, and the second output of the first clock synchronization unit, the third output and the third input of the first phasing unit are respectively the first additional output, the second optional output and control input of the signal compression device.

In each transceiver kit, the control unit contains an OR element, first and second triggers, a third input signal switcher, an OR-NOT element and a DSC signal decoder, the output of which is combined with the first input of the OR element and with the first input of the first trigger, the output of which is connected to the control input the third input signal switch, the output of which is connected to the first input of the OR-NOT element, the second input of which is connected to the output of the second trigger, the first input of which is connected to the output of the OR element, the first and second the inputs of the third input signal switch, the second input of the first trigger combined with the second input of the OR element, the second input of the second trigger, the first and second inputs of the DSC signal decoder and the output of the OR element are NOT inputs, second, first, third, fourth and fifth additional inputs and outputs of the control device.

In each transceiver set, the signal expansion device consists of a second memory block, the input and output of which are the input and output of the signal expansion device, second recording counter, second readout counter, second phasing block, second clock synchronization block and cyclic synchronization block, the input of which is combined with the input of the second memory block and the input of the second clock synchronization block, the first and second outputs of which are connected respectively to the clock input of the second counter with reading and the clock input of the cyclic synchronization unit, combined with the clock input of the second recording counter, and which is an additional output of the signal expansion device, the output of the second recording counter is combined with the recording control input of the second memory block and the first input of the second phasing block, the second input of which is combined with the control the read input of the second memory unit and the output of the second read counter, the control input of which is connected to the first output of the second phasing unit, the second output of which connected to the control input of the second recording counter, and the third input of the second phasing unit is connected to the output of the cyclic synchronization unit.

In each transceiver set, the modulator is made in the form of a series-parallel converter, the input of which is the input of the modulator, and an OFDM signal conditioning unit, the output of which is the output of the modulator.

In each transceiver set, the transmitter contains a series-connected exciter, the input of which is the input of the transmitter, a power amplifier and a harmonic filter, the output of which is the output of the transmitter, the control input of the exciter, which is an additional input of the transmitter, is combined with the control input of the power amplifier and the control input of the harmonic filter, which contains K range filter nodes, the input and output of each of which through movable and fixed contacts of the corresponding two three push-pull switches are connected to the input and output of the harmonic filter, respectively, other fixed contacts of all 2K three-pin harmonic filter switches are connected to the common bus and are normally closed with the corresponding movable contacts, each range filter unit contains a main filter element, the input of which is the input of the range filter unit, and an additional filter element, the output of which is the output of the range filter unit, as well as a second radio signal switch la, the signal input of which is combined with the output of the main and the input of the additional filtering elements, the signal output of the second switch of the radio signal is connected to a common bus, and its control input is the control input of the range filter node, the control inputs of all range filter nodes are combined with the control input of the harmonic filter.

In each transceiver set, the demodulator is made in the form of a series-connected OFDM signal demodulation unit, the input and control input of which are respectively the input and additional input of the demodulator, and the parallel-serial converter, the output of which is the output of the demodulator.

In each transceiver set, the clock demodulator is made in the form of a series-connected amplitude detector, the input of which is the input of the clock demodulator, and a regenerator, the output of which is the output of the clock demodulator.

Figure 1 shows the electrical structural diagram of the proposed system; figure 2 is a timing chart explaining the operation of the system.

A duplex high-speed short-wave radio communication system consisting of two transceiver sets 1, each of which contains an analog signal source 2 and an analog signal receiver 3, a signal compression device 4 and a signal expansion device 5, a control unit 6, the output of which is connected to the control input of the signal compression device 4, a modulator 7, a series-connected transmitter 8 and a transceiver antenna 9, as well as a first input signal switcher 10 demodulator 11, the output of which is connected to the input 5 roystva extension signal, a clock demodulator 12, whose output is connected to the input of the control unit 6 and a receiver 13, whose output is connected in parallel with the input of the demodulator 11 and the clock input of the demodulator 12.

Each transceiver set 1 contains an encoder 14, the input of which is connected to the output of the analog signal source 2, and a decoder 15, the output of which is connected to the input of the analog signal receiver 3, a binary signal source 16 and a digital signal receiver 17, the first radio signal switch 18 ₁ , the output switch signals 19, an input whose first and second outputs are connected respectively to the output of the signal expansion device 5, to the input of the decoder 15 and to the input of the recipient of the discrete signal 17, and the control input of the output switch signal 19, which is the input source control signal of the transceiver kit 1, is combined with the control input of the first input signal commutator 10 ₁ , the output, the first and second inputs of which are connected respectively to the input of the signal expansion device 4, with the output of the encoder 14 and with the output of the digital signal source 16 in addition, each transceiver assembly 1 comprises a generator of digital selective calling signal (DSC) 20 and second switch input signals February _10, output of which is connected to an input of modulator 7, O d is connected to the input of the transmitter 8, whose output is connected further to the signal input of the first switch radio Jan. _18, 6 control unit output is connected further to a control input of the first switch radio Jan. _18, with an additional input predatchika 8 and the additional input of the demodulator 11, and the first an additional input of the control unit 6, which is a transmission control signal input DSC transceiver assembly 1, is combined with the control input of the second switch input signal generator 10 ₂ and to the control conductive input signal shaper DSC 20, whose output is connected to a first input of the second switch input signal generator 10 _2, a second input coupled to an output of the signal compression device 4, the first and second additional outputs which are connected respectively to the clock input of the signal of the DSC 20 and a second additional the input of the control unit 6, the third additional input of which is the input of the installation of the transceiver set 1 in the signal reception mode, and its fourth additional input is connected to the additional the output of the signal expansion device 5, the input of which is additionally connected to the fifth additional input of the control unit 6.

The signal compression device 4 consists of a first memory block 21 ₁ , the input and output of which are respectively the input and output of the signal compression device 4, the first write counter 22 ₁ , the first read counter 23 ₁ , the first phasing block 24 ₁ and the first clock synchronization block 25 ₁ having an input merged with the input of the first memory unit 21 _1, and its first and second outputs connected respectively to the clock input of a first recording clock counter 22 ₁ and a clock input of the first read counter 23 ₁ whose output is combined with the control input m read memory unit 21 ₁ and the first input of the first block phasing Jan. _24, the second input of which is combined with the control input of the record of the first memory unit 21 ₁ and the output of the first write counter January _22, managing the input of which is connected to the first output of first block phasing Jan. _24, the second the output of which is connected to the control input of the first readout counter 23 ₁ , and the second output of the first clock synchronization block 25 ₁ , the third output and the third input of the first phasing block 24 ₁ are the first additional output, respectively Direct output and control input of the signal compression device 4.

The control unit 6 contains an OR element 26, the first and second triggers 27 ₁ and 27 ₂ , a third input signal switch 10 ₃ , an OR-NOT element 28 and a DSC signal decoder 29, the output of which is combined with the first input of the OR element 26, and with the first input the first trigger 27 ₁ , the output of which is connected to the control input of the third input signal switch 10 ₃ , the output of which is connected to the first input of the OR-NOT 28 element, the second input of which is connected to the output of the second trigger 27 ₂ , the first input of which is connected to the output of the OR element 26 , and the first and second entrance third switch input signals of 10 _3, a second input of the first flip-flop on January _27, combined with a second input of the OR gate, the second input of the second flip-flop on February _27, the first and second inputs of a signal decoder DSC 29 and an output of OR-NO element 28 are respectively input, second, first , third, fourth and fifth additional inputs and output of the control device 6.

The signal expansion device 5 consists of a second memory block 21 ₂ , the input and output of which are respectively the input and output of the signal expansion device 4, the second write counter 22 ₂ , the second read counter 23 ₂ , the second phasing block 24 ₂ , the second clock synchronization block 25 ₂ and a cyclic synchronization block 30, the input of which is combined with the input of the second memory block 22 ₂ and the input of the second clock synchronization block 25 ₂ , the first and second outputs of which are connected respectively to the clock input of the second readout counter 23 ₂ and the clock input of the cyclic synchronization block 30, combined with the clock input of the second recording counter 22 ₂ , and which is an additional output of the signal expansion device 5, the output of the second recording counter 22 _{2 is} combined with the recording control input of the second memory block 21 ₂ and the first input of the second phasing block 24 ₂ , the second input of which is combined with the control input of the read of the second memory block 21 ₂ and the output of the second readout counter 23 ₂ , the control input of which is connected to the first output of the second phasing block 24 ₂ , the second the output of which is connected to the control input of the second recording counter 22 ₂ , and the third input of the second phasing unit 24 _{2 is} connected to the output of the cyclic synchronization unit 30.

The modulator 7 is made in the form of series-parallel series-parallel Converter 31, the input of which is the input of the modulator, and the OFDM 32 signal conditioning unit, the output of which is the output of the demodulator 7.

The transmitter 8 contains a series-connected exciter 33, the input of which is the input of the transmitter 8, a power amplifier 34 and a harmonic filter 35, the output of which is the output of the transmitter 8, the control input of the exciter 33, which is an additional input of the transmitter 8, is combined with the control input of the power amplifier 34 and the control the input of the harmonic filter 35, which contains K range filter nodes 36, the input and output of each of which through movable and fixed contacts of the corresponding two three-pin switch fels are connected to the input and output of the harmonic filter 35, respectively, other fixed contacts of all 2K three-contact switches of the harmonic filter 35 are connected to a common bus and normally closed with the corresponding movable contacts, each range filter unit 36 contains a main filter element 38, the input of which is an input of the range filter node 36, and an additional filter element 39, the output of which is the output of the range filter node 36, as well as the second radio signal switch, a signal the input of which is combined with the output of the main 38 and the input of an additional 39 filter elements, the signal output of the second 18 g radio signal switch is connected to a common bus, and its control input is the control input of the range filter node 36, the control inputs of all range filter nodes 36 are combined with the control input harmonics filter 35.

The demodulator 11 is made in the form of an OFDM 40 signal demodulation unit connected in series, the input and control input of which are respectively the input and additional input of the demodulator 7, and the parallel-serial converter 41, the output of which is the output of the demodulator 11.

The clock demodulator 12 is made in the form of a series-connected amplitude detector 42, the input of which is the input of the clock demodulator 12 and the regenerator 42, the output of which is the output of the clock 12 demodulator.

System duplex high-speed short-wave radio operates as follows.

In the initial state (before the start of duplex exchange of analogue telephone or discrete information), each transceiver set 1 (PPC) of the system is set to “receive” mode by applying “Ex. PFP "(the third additional input of the control device 6) of the pulse signal in the form of a short-term logical level" 1 ". In the control device 6, the pulse signal transfers the second trigger 27 ₂ to a single (inhibitory) state, and its output logic level “1” blocks the control signal from the output of the third switch 10 ₃ to the output of the “OR-NOT” element, which is the output of the control unit 6 . As a result, the logic level "0" from the output control unit 6, acting on the additional input of transmitter 8 to the first switch control input radio January ₁₈ and an additional input of the demodulator 11 locks the output signal of the transmitter 8 inlet and receive antenna 9 and simultaneously provides the connection to the transceiver antenna 9 input receptacle 13 through the first switch ₁₈ January radio.

In this case, the signal received by the transceiver antenna 9, which is a combination of various types of interference, is filtered by the selective circuits of the receiver 13 and, from its output, for example, in digital form [4] is fed in parallel to the inputs of the clock demodulator 12 and demodulator 11, which operate in continuous mode (the operation of the demodulator 11 is not blocked by the control signal at its additional input).

Consider the operation of the system when the exchange of information between two PICs will be carried out using sources of analog signals 2 and recipients of analog signals 3.

To do this, enter “Ex. IS ”(control of the signal source) of each control panel, the logical level“ 0 ”must be received, at which the first input signal switch 10 ₁ connects the output of encoder 14 to the input of the signal compression device 4, which provides the conversion of the analog TLF signal from the output of the source of analog signal 2 to binary stream, and the switch of the output signals 19 connects the output of the signal expansion device 21 ₂ to the decoder 15, which performs the inverse operation of converting the received binary stream into an analog TLF signal, which e is supplied to the receiver of the analog signal 3.

If it is necessary to conduct a duplex communication session at the initiative of one of the radio subscribers, the corresponding control panel, for example, the first one is transferred to the “leading” mode by applying “Ex. DSC ”(DSC signal transmission control) commands in the form of a logical level“ 1 ”. This level, arriving at the control inputs of the second commutator of the input signals 10 ₂ and the signal conditioner DSC 20, enables the shaper 20 and the switching of its output signal through the second commutator of the input signals 10 ₂ to the input of the modulator 7.

The DSC signal is generated in the form of a binary sequence with the encoded and periodically repeated digital address of the called subscriber. The DSC signal transmission speed is equal to the double transmission rate of the main signal V = 1 / T bit / s (T is the duration of the source signal element at the output of the first input signal switch 10 ₁ : either discrete - binary, or analog telephone, converted to binary stream) and is equal to the pulse repetition rate of 2F _{t PRD1} at the first additional output of the signal compression device 4.

The duration of the DSC signal generation is determined by the duration of the logic level “1” at the input “Ex. DSC ”and should not be less than the time interval necessary for reliable detection of the DSC signal in the second (slave) control panel.

At the same time, the control logic level is “1” from the input “Ex. DSC ”of the leading control panel is fed to the first additional input of the control unit 6, in which it enters the second input of the OR element 26 and the second input of the first trigger 27 ₁ , translating the first 27 ₁ and second 27 ₂ triggers into single and zero states, respectively, in which an output of NOR 28 through a third switch input signals Mar. ₁₀ is switched from the second additional signal compression device 4 outputs a control signal meander-defining repetitive work cycles ( "reception-transmission") AUC of frequency F _{n Tx1} ( "transmission "Covering the logic level" 1 "," reception "covering the logic level" 0 ").

At each time interval, the “transmission” of the control meander, the transmitter 8 provides amplification of the signal power from the output of the modulator 7, filtering it from undesirable frequency components in one of the K range filter nodes 36 (the transparency band of which ensures the transmission of the transmitted signal), connected via three-pin switches 37 to the input and output of the harmonic filter 35, and radiation through the transceiver antenna 9 quanta of the signal, carrying information about the DSC signal.

The initial modulating binary sequence of the DSC signal from the output of the second input signal switch South is fed to the input of the serial-parallel converter 31 of the modulator 7, where it is divided into N parallel streams (N is the number of frequency channels of the modulator 7, in each of which the duration of the binary symbols is increased by N times )

The formation of the subsequent multi-frequency OFDM signal in the band of the telephone channel (3100 Hz), which modulates the transmitter 9, is performed in the OFDM 32 signal conditioning unit in a known manner, for example, as described in [9].

At intervals of “reception” of the control meander, the pathogen 33 and the power amplifier 34 of the transmitter 8 are locked, and in the connected range filtering unit 36, they are connected to the output bus of the main filter element 38 and the output of the additional filter element 39 through a closed second radio signal switch I82, made on pin diodes.

In this case, the sequential oscillatory circuit of the band-pass filtering unit 36, consisting of the main 38 and additional 39 filter elements, is converted with respect to the input of the transceiver antenna 9 into a parallel oscillatory circuit with a resonance frequency close to the cut-off frequency of the band-pass filtering node 36. The resistance of such a parallel oscillatory circuit in the transparency band of the band-pass filtering unit 36 is inductive in nature, the module of which is larger than the input resistance Ia receiver 13 being connected in intervals "reception" antenna to the transceiver 9 via a first radio switch January ₁₈ formed on the pin-diodes.

Thus, at time intervals "reception" of the control meander provides the necessary attenuation of the noise level from the output of the transmitter 8 and the preservation of the sensitivity of the receiver 13.

Consider the operation of the second (slave) PPC when receiving a DSC signal.

In the initial state (before the transmission of the DSC signal by the first PPC), the second PPC, as noted above, is in the “receive” mode.

When transmitting the DSC signal, as well as during the subsequent transmission by the first PPC of the main discrete signal received by the receiver 13 of the second PPC, the radio signal is a signal in the form of a signal of multi-frequency amplitude telegraphy (AT) [10].

Thus, in the received signal, in addition to the basic information contained in the quanta of the OFDM signal, there is also synchronization information about the boundaries of the reception - transmission transmission time intervals, which can be used to ensure synchronous operation of two control panels without introducing excessive clock information into the transmitted signal.

The clock signal corresponding to the control square wave of the first PPC is extracted by the demodulator of the clock signal 12 of the second PPC, in which the signal is first detected by the amplitude detector 42 [10], after which the AT signal is regenerated by the regenerator 43, where the temporal position of the edges of the packet edges of the detected square wave is averaged and restored form [8] as the control meander, ensuring the operation of the slave control panel in antiphase with respect to the work of the leading control panel.

Due to the periodicity and rather long duration of the sequence of transmission-reception cyclic intervals, the regenerated meander can be restored with a high degree of reliability.

At the same time, the received signal is demodulated by the OFDM signal demodulator 40 of the demodulator 11, for example, in a known manner [9], after which N synchronous binary streams are converted in parallel-serial converter 41 into a single binary sequence with an ether transmission speed V = 2F _{t prm2} = 2F _{t prd1} .

The DSC signal is detected by the DSC signal decoder 29 of the control unit 6, the signal input of which receives the output signal of the demodulator 11, and its clock input receives a sequence of clock pulses from the additional output of the signal compression device 4, synchronous with the binary symbol sequence of the input signal.

When a DSC signal is detected in the demodulated quanta of the signal, the output of the decoder 29 generates a pulse signal-short-term logic level "1", which, entering the first inputs of the first trigger 27 ₁ and the OR element 26, sets the first 27 ₁ and second 21 ₂ triggers to zero states which ensures switching of the received control meander from the output of the clock demodulator 12 (via the third input signal switch 10 ₃ and the OR-NOT 28 element) to the output of the control unit 6. This provides a remote translation second PPC in the “slave” state.

Detection of a DSC signal by a DSC 29 decoder may also be accompanied by sound or light signaling for the called subscriber, after which duplex TLF radio communication can be carried out similarly to telephone conversations.

After transferring the second control panel to the “slave” mode, its transceiver antenna 9 begins to radiate quanta of the information radio signal on air at “transmission” time intervals of the regenerated control meander.

Let us consider in more detail the process of establishing and maintaining duplex radio communications.

Upon completion of the transmission of the DSC signal by the first control panel (when the unit logic level changes to the zero level at the “DSC control” input), the second input signal switch 10 ₂ connects an information binary sequence from the output of the signal compression device 4 to the input of the modulator 7.

The signal compression device 4 operates as follows.

At the input of the device through the first switch of the input signals 10 ₁ , a binary signal can be received either from the output of the encoder (digital speech) or from the output of the source of a discrete signal (data) with a transmission speed V bit / s. For clarity, the description of the operation, we assume that the input signal is a periodically repeated combination of binary symbols of type 1110010 (figa).

In the signal compression device 4, the input signal is supplied simultaneously to the first clock synchronization block (BTS) 25 ₁ and the first memory block 21 ₁ , which can be a random access memory with separate and independent control inputs for recording and reading information.

BTS 25 _{1 is} intended for the formation of clock sequences of pulses for the first write counter 22 ₁ and the first read counter 23 ₂ information synchronous with the repetition rate of binary symbols of the input signal. In this case, to ensure compression of the binary signal by a factor of 2 at the output of signal compression device 4, it is necessary that the pulse repetition rate be two times higher than the pulse repetition rate F _{t prd1} .

The clock sequence F _{t prd1} and 2F _{t prd1} (figb, c) can be formed at the outputs of the intermediate frequency dividers BTS by dividing the frequency of the master oscillator having high stability. The phase of pulses at the output of the dividers can be changed using the phase-locked loop by adding or subtracting pulses in a sequence of pulses with a higher frequency in accordance with changes in the phase of the input binary symbols [8, p. 252].

Capacities M ₁ and M ₂ counters write (22 ₁ ) and read (23 ₂ ) should be determined as follows.

To conduct duplex radio communication, each control panel should periodically switch from receiving to transmitting in antiphase with respect to each other with a frequency of F = 1 / T _c , where T _c is the duration of one cycle “transmission” - “reception”. The duration T _c is selected based on the permissible delay value of the digitally converted telephone signal (0.1 ... 0.3 s) and the characteristics of the used transceiver means. For radio communication by discrete messages, the value of T _c can be selected over a wider range.

When the bit rate of the binary characters of the digitized speech signal is V bit / s, the capacity M _{1 of the} write counter 22 ₁ or the number of binary characters periodically recorded by the write counter 22 ₁ in the memory block 21 ₁ for one cycle of duration T _c = M ₁ T (binary characters or clock intervals (TI) of the frequency F _{t prd1} ), you can choose between: M ₁ = T _c / T ~ (0.1 ... 0.3) · V. Moreover, the integer M ₁ must be even to ensure a delay of T _c / 2 between the moments of writing and reading information in the first memory block 21 ₁ .

To ensure compression of the initial quantum of the signal with a duration of T _c in 2 times, the following is performed:

- in the first half of each cycle (time interval “reception” of duration T _c / 2) sequential recording is performed (in the corresponding memory cells of the memory block 21 ₁ ) M ₁ binary symbols of the signal being prepared for transmission of the quantum;

- in the second half of each cycle (time interval "transmission")

from these cells of the memory block 21 ₁ sequential reading of binary information is performed at double speed and with a delay by the value of T _c / 2 with respect to the moments of recording.

For this, it is necessary that the capacity M _{2 of the} read counter 23 ₁ be 2 times the capacity of the write counter 22 ₁ , i.e. M ₂ = 2M ₁ . Moreover, the first M ₁ read cell addresses successively changed at the output of the read counter 23 ₁ with a clock frequency of 2F _{t prd1} must correspond to the memory cell addresses where M _{1 the} input characters of the first memory block 21 ₁ were recorded, and the subsequent M ₁ read addresses should correspond to cells, in each of which the symbol "0" is constantly recorded.

Accordingly, the number of memory cells in the memory block 21 _{1 of the} signal compression device 4 must be at least M ₂ .

For clarity in FIG. 2a, the cycle duration T _c in clock intervals (TI) or the capacity M _{1 of the} write counter 22 _{1 is} taken to be M ₁ = 16, the capacity of the read counter 23 ₁ -M ₂ = 32. In this case, a 4-bit binary counter can be used as a write counter 22 ₁ , and a 5-bit binary counter as a read counter 23 ₁ .

Each state of the recording counter (in the case under consideration, from 0 to 15) has its own memory cell in the memory block 21 ₁ , into which a logical level is written corresponding to the binary symbol at the input of the memory block and which is stored in the cell for one cycle.

On fig.2g, d, g, h, and shows the logical levels of memory cells with numbers 1, 2, 3, ..., 15, 16, corresponding to numbered from 1 to 16 characters of the input binary sequence, conventionally divided into cyclic intervals of duration T _c = 16 TI each.

Reading information from the memory cells is performed with a delay by an amount T _p = 12 TI 8 (or 16 clock pulse frequency 2F intervals _{T Tx1).}

The necessary phase relations between the write and read counters are established by the phasing unit 24 ₁ by comparing the states of the counters (output bit binary numbers) at the inputs 1 and 2 of the phasing unit 24 ₁ and the forced initial setting of the write counter 22 ₁ to the required state by the control signal from the first output of this unit .

In addition, the phasing unit 24 ₁ forms a control meander with a binary frequency F _{c prd1} , which controls the operation of the control _panel set to the “leading” mode. Since the outputs of the write and read counters are connected to the inputs 1 and 2 of the phasing block 24 ₁ , the formation of the control signal is quite simple using the output signal of the highest level of the read counter 23 ₁ .

In Fig.2k shows the output signal of the signal compression device 4, in Fig.2l - the control meander of the control unit 6, formed by the phasing unit 24 ₁ in inverse form. The time intervals “transmission” and “reception” of the first (leading) control panel are indicated here, respectively “PRD1” and “PRM1”.

2 times compressed quanta of the transmitted signal at the end of the action of the unit logical level command at the input DSC "AUC first fed through the second switch input signals at the modulator ₁₀ February entrance 7. To simplify the presentation of the principle of operation herein assumed that the number of parallel frequency division multiplexing modulator 7 is equal to N = 8, respectively binary symbols of each photon signal transmitted to the serial-parallel converter 31 modulators 7 are distributed over eight channels for generating a multi-frequency OFDM signal by an OFDM 32 signal conditioning unit. Moreover, the duration of each binary symbol of the input quantum increased it is displayed 8 times, and at each time interval “transmission” (Tx1) of duration T _c / 2 for each of the frequency channels of the OFDM signal is transmitted (by the above method) information on the values of only two characters out of every 16 with the duration of the element signal on the air T _e = 4T.

Further, the process of generating and transmitting quanta of the OFDM information signal is similar to that described above when transmitting a DSC signal.

Similarly to the foregoing, the signal compression device 4 of the second (slave) PPC and its subsequent devices, providing the transmission of the quanta of the OFDM signal on air with duplex transmission of information towards the first PPC, work. However, the transmission of quanta of the response digitized speech signal begins only after the regeneration of the demodulated control meander and the reception of the DSC signal.

A regenerated control meander, similar to the control meander of the first BCP, with a repetition rate of the cyclic intervals F _{c prm2} = F _{c prd1} , is shown in Fig. 2m taking into account the delay of the signal τ ₃ during its propagation from the transmitter of the first BCP to the receiver of the second BCP. For clarity, it is assumed that the delay value corresponds to the duration of one received binary symbol, i.e. τ ₃ = T / 2.

In order to generate second quanta of the signal quanta similar to the first quantization method, it is necessary to combine the beginning of reading binary characters from the first memory block 21 _{1 of the} signal compression device 4 with the beginning of the time interval “transmission” of the regenerated control meander. This is achieved by forcing the readout counter 23 ₁ to the required state by a signal from the second output of the first phasing unit 24 ₁ in accordance with the temporary position (phase) of the “transfer” intervals of the regenerated control meander, which is supplied to the third control input of the first phasing unit 24 ₁ after detecting the signal DSC

On fign conventionally indicated the time boundaries of the quanta of the signal transmitted by the second PPC at the input of the first switch of radio signals 18 _{1 the} first PPC taking into account the propagation delay of the signal from the second set to the first. In this case, the total delay of the first HSC quanta of the signal with respect to the transmitted ones is 2τ ₃ .

Consider the process of receiving an information signal by the first (leading) PPC after receiving the DSC signal by the second (slave) PPC.

We will assume that in the second PPC, the initial signal at the input of signal compression device 4 is similar to that previously considered (Fig. 2a), but with a phase shift (temporary position) of the binary sequence with respect to the control square wave (Fig. 2m).

The first radio signal switch 18 _{1 of the} first PPC, controlled by the meander (Fig. 2l), formed by the signal compression device 4, will switch in time intervals PRM1 (“reception”) to the input of the receiver 13 quanta of the received OFDM signal, truncated at the ends by 2τ ₃ . The shape of the envelope of these quanta corresponds to the output signal of the demodulator of the clock 42, shown in Fig.2o (in the absence of any interference at the input of the receiver 13).

The OFDM signal demodulation unit 40 of the demodulator 11 performs an operation inverse to the operation performed by the OFDM signal conditioning unit. At the same time, N = 8 binary streams are formed at its output, which are converted by a parallel-serial converter 41 into a common stream with a speed of 1 / 2F _{t prd1} (Fig.2p).

The shortening in duration of each high-frequency signal quantum received from the ether by the first radio signal switch 18 ₁ by 2τ ₃ does not affect the noise immunity of receiving binary information. The number of frequency channels N, determining the increase in the duration of the binary symbol (after doubling the transmission rate) in each channel by N times (T _e = NT / 2), is selected based on ensuring the required value of the guard interval when transmitting high-speed information over the KB communication channel [9] , which is significantly larger than 2τ ₃ .

Moreover, only the part of the quantum of the signal corresponding to the last binary symbol in each channel is subjected to reduction in duration (in our example, with N = 8 and T _c = 16 TI, the last is the second symbol of each channel - Fig.2o, in reality, when implementing the system T _c is selected at a much larger value of 16 TI, for example, at T _c = 0.2 s, N = 8 and at a data transfer rate of 4800 bit / s on the KB channel, L = is transmitted in each quantum of the signal for each of their 8 frequency channels 0.2 · 4800/8 = 120 binary characters, i.e. the last in the channel will be the 120th with mvol).

From the output of the demodulator, the discrete signal enters the signal expansion device 5, where the operation is performed, the inverse of the signal compression operation. To do this, in the second block of clock synchronization 25 ₂ (similar to the previously discussed BPS 22 ₁ ), the temporary position of the boundaries of the binary elements from the output of the demodulator 11 is determined and the corresponding clock sequences of pulses 2F _{t prm1} and F _{t prm1 are formed} (Fig.2r, t), providing synchronous recording of information in the second memory block 21 ₂ and its reading using the second write counter 22 ₂ and the second read counter 23 ₂ , the capacity of which is equal to the previously determined values of M ₂ and M _1, respectively.

The necessary delay by half the cyclic interval T _c / 2 of the moments of reading binary information regarding the moments of recording is provided by setting the second read counter 23 ₂ in the required state by the control signal from the first output of the second phasing block 24 ₂ .

In addition, it is necessary that the beginning of the recording in the second memory block 21 _{2 of the} sequence of binary information symbols of each demodulated quantum of the signal (Fig.2p) coincides with the arrival of the first binary symbol of the demodulated quantum, i.e. the first character of the demodulated quantum of the signal must be written in the first memory cell of block 21 ₂ , the next second character, etc., in the second cell

The necessary phasing of the second recording counter 22 _{2 is} provided by the control signal from the second output of the phasing block 24 ₂ in accordance with the temporary position (phase) of the cyclic pulses F _{cs prm1} (Fig.2c) from the output of the cyclic synchronization (BCC) 30. As a cyclic clock signal contained in each cycle of the demodulated signal, you can use a sequence of M ₁ zero binary characters following the last information symbol of the demodulated quantum of the signal (fig.2p).

In order to exclude the appearance of 11 “false” characters “1” at the output of the demodulator after the last information symbol of each demodulated quantum of the signal (due to the action of noise at its input), the operation of the OFDM 40 signal demodulation block is blocked by the control meander from the output of control unit 6 at time intervals "PRD1" (Fig.2l).

To ensure the operation of the BCC, a signal from the output of the demodulator 11 is fed to its information input, and a clock sequence of pulses from the second output of the second BPS 25 ₂ is supplied to its clock input. As the BCC, the BCC given in [11] can be used.

The result of reading information from the second memory block 21 ₂ is shown in FIG. This binary signal is switched by the switch of the output signals 19 to the input of the decoder 15, where it is converted into an analog TLF signal, which is then fed to the receiver of the analog signal 3.

Similarly, the reception of the information signal by the second (slave) PPC in the process of conducting duplex radio communication after receiving the DSC signal. In contrast to the reception of information by the first PPC, the received signal quanta are not shortened here because the “PRM2” time intervals of the regenerated control meander coincide with the duration of the quanta of the binary sequence of the demodulated signal.

When duplex exchange of discrete information to the input "Ex. IS "(control of the signal source) of each control panel, the logical level" 1 "is supplied, at which the input of the signal compression device 4 of the discrete signal source 16 is connected by the first input signal switch 10 ₁ and the output signal switch 19 - the output of the signal expansion device 5 the input of the recipient of the discrete signal 17. The process of conducting duplex radio communication using discrete sources 16 and the receivers 17 of the signals PPC similar to the above.

From a practical point of view, all the components of a high-speed duplex radio communication system are realizable, as specified in the presentation of the system. The encoder and decoder are the transmitting and receiving parts of industrially produced vocoders [12, 13], which provide the conversion of the speech signal into a binary stream with speeds of 600, 1200, 2400, 4800 bit / s.

The modulator and demodulator are the receiving and transmitting parts of industrially produced high-speed modems of parallel type for transmitting data at speeds of up to 9600 bps in the band of the telephone channel (3100 Hz).

Implementation of the present invention is a system of high-speed duplex radio communications, will achieve the following advantages in relation to the known systems of duplex radio communications [1, 2]:

- increasing the noise immunity of receiving telephone messages by reducing the bandwidth by at least two times and implementing a modulator and demodulator as part of the system based on the application of the compression method with orthogonal frequency division (OFDM - Orthogonall Frequency Division Multiplexing) with the highest frequency filling density range when using OFDM signals;

- an increase in the bandwidth of the communication channel due to the exclusion of a special clock signal introduced into the resulting transmitted signal and the use of an OFDM signal with high spectral density for duplex radio communication instead of an analogue TLF signal of the AZE radiation class with a significantly lower spectral density;

- expanding the functionality of the system due to the introduction of additional technical means and the use of OFDM signals, which provide duplex exchange on a multipath KB channel both by telephone and by high-speed discrete messages.

- an increase in the number of radio subscribers that can operate at the same operating frequency due to the introduction of technical means for transmitting and receiving DSC signals;

- increasing the communication range by reducing the noise level of the transmitter at the input of the receiver.

In conclusion, we note that the use of the proposed duplex system for high-speed short-wave radio communications will make it possible to practically implement the full-duplex radio exchange mode at the same frequency with both voice messages and high-speed data on KB radio routes of various lengths.

Information sources:

1. Two-way communication device, Sat The best designs of radio amateurs, M: DOSAAF, 1975, S. 79-80.

2. Pat. 2190301 RF Duplex radio communication system / A.N. Yuriev, B.N. Yaroshevich, V.I. Levchenko, B.G. Shadrin. - 2002.

3. GOST R-50016-92 Requirements for the bandwidth of radio frequencies and out-of-band emissions of radio transmitters.

4. Berezovsky V.A., Dulkeit I.V., Savitsky O.K. Modern decameter radio communication: equipment, systems and complexes / Edited by V.A. Berezovsky. - M .: Radio engineering, 2011 .-- 444 p.

5. Makarov S.B., Tsikin I.L. Discrete messaging over limited bandwidth radio channels. - M .: Radio and Vyaz, 1988 .-- 304 p.

6. Kalinini A.I., Cherenkova E.L. Propagation of radio waves, M .: Communication, 1971.

7. Cherenkova E.L. Distortion of telegraph signals in shortwave transmission. Svyazizdat, 1955.

8. N.A. Sartasov, V.M. Edvabny, V.V. Gribin Short-wave radio receivers. M .: Communication, 1971. - 288 p.

9. A.M. Kiselev, V.V. Mahotin, N.Yu. Ryzhov, G.V. Shatalova Method for the implementation of a high-speed parallel modem // Radio communication technology / Omsk Research Institute of Instrument Engineering. - 2006. Issue 11 - S.5-15.

10. Gonorovsky I.S. Radio circuits and signals. M .: Sov. Radio, 1977 .-- 608 p.

11. A.S. No. 1138954 Cyclic synchronization device / B.G. Shadrin. - 1985.

12. Equipment for the transmission of discrete information MS-5 / Edited by A.M. Zaezdnogo and Yu.B. Okuneva. - M .: Communication, 1970 .-- 152 p.

13. Chamberlain M.W. A 600 bps MELP vocoder for use on hf channels .. // IEEE. 2001. URL: http://ieeexplore.ieee.org.

Claims (8)

1. Duplex high-speed short-wave radio communication system, consisting of two transceiver sets, each of which contains an analog signal source and an analog signal receiver, a signal compression device and a signal expansion device, a control unit whose output is connected to the control input of the signal compression device, a modulator, in series connected transmitter and transceiver antenna, as well as the first input signal switch, a demodulator, the output of which is connected to the input of the expander signal oscillations, a clock demodulator, the output of which is connected to the input of the control unit, and a receiver, the output of which is connected in parallel with the demodulator input and the input of the clock demodulator, characterized in that an encoder is added to each transceiver set, the input of which is connected to the output of the analog signal source, and a decoder, the output of which is connected to the input of the receiver of the analog signal, a discrete signal source and a discrete signal receiver, a first radio signal switch, an output switch signal, the input, the first and second outputs of which are connected respectively to the output of the signal expansion device, with the input of the decoder and with the input of the receiver of the discrete signal, and the control input of the output signal switch, which is the control signal source input of the transceiver set, is combined with the control input of the first input switch signals, the output, the first and second inputs of which are connected respectively to the input of the signal expansion device, with the output of the encoder and with the output of the discrete signal source in addition, a digital selective call signal (DSC) driver and a second input signal commutator are introduced, the output of which is connected to the modulator input, the output of which is connected to the transmitter input, the output of which is connected additionally to the signal input of the first radio signal switch, the control unit output is additionally connected to the control input of the first radio signal switch, with an additional input of the transmitter and with an additional input of the demodulator, and the first additional input of the control unit, which with the input of the DSC signal transmission control of the transceiver set, it is combined with the control input of the second input signal switch and the control input of the DSC signal generator, the output of which is connected to the first input of the second input signal switch, the second input of which is connected to the output of the signal compression device, the first and second additional the outputs of which are connected respectively to the clock input of the DSC signal conditioner and to the second additional input of the control unit, the third additional input of which о is the input of the installation of the transceiver set into the signal reception mode, and its fourth additional input is connected to the additional output of the signal expansion device, the input of which is additionally connected to the fifth additional input of the control unit. 2. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set the signal compression device consists of a first memory unit, the input and output of which are respectively the input and output of the signal compression device, the first write counter, the first read counter, the first phasing unit and the first clock synchronization unit, the input of which is combined with the input of the first memory unit, and its first and second outputs are connected respectively to the clock input of the first account recording logic and with a clock input of the first readout counter, the output of which is combined with the control input of the memory block and the first input of the first phasing unit, the second input of which is combined with the write control input of the first memory unit and the output of the first write counter, the control input of which is connected to the first output the first phasing unit, the second output of which is connected to the control input of the first readout counter, the second output of the first clock synchronization unit, the third output and the third input of the first a phasing unit are, respectively, the first additional output, a second additional output signal and the control input of the compression unit. 3. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set, the control unit comprises an OR element, a first and second trigger, a third input signal switch, an OR-NOT element and a DSC signal decoder, the output of which is combined with the first the input of the OR element and with the first input of the first trigger, the output of which is connected to the control input of the third input signal switch, the output of which is connected to the first input of the OR-NOT element, the second input of which is connected to the output a second trigger, the first input of which is connected to the output of the OR element, the first and second inputs of the third switch of input signals, the second input of the first trigger combined with the second input of the OR element, the second input of the second trigger, the first and second inputs of the DSC decoder and the output of the OR element - NOT are respectively the input, second, first, third, fourth and fifth additional inputs and output of the control unit. 4. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set the signal expansion device consists of a second memory unit, the input and output of which are respectively the input and output of the signal expansion device, the second write counter, the second read counter, a second phasing unit, a second clock synchronization block and a cyclic synchronization block, the input of which is combined with the input of the second memory block and the input of the second clock synchronization block, the first and second outputs of which are connected respectively to the clock input of the second readout counter and to the clock input of the cyclic synchronization unit, combined with the clock input of the second record counter and which is an additional output of the signal expansion device, the output of the second record counter is combined with the recording control input of the second memory block and with the first input of the second phasing unit, the second input of which is combined with the read control input of the second memory unit and with the output of the second readout counter, unitary enterprise ulation input coupled to the first output of the second phasing unit, the second output of which is connected to a control input of a second write counter and a third input of the second phasing unit connected to the output of frame sync block. 5. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set the modulator is made in the form of series-connected serial-parallel converter, the input of which is the input of the modulator, and the OFDM signal conditioning unit, the output of which is the output of the demodulator. 6. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set the transmitter contains a series-connected exciter, the input of which is the input of the transmitter, a power amplifier and a harmonic filter, the output of which is the output of the transmitter, the control input of the exciter, which is additional the input of the transmitter is combined with the control input of the power amplifier and the control input of the harmonic filter, which contains K range filter nodes, input d and the output of each of which, through the movable and fixed contacts of the corresponding two three-pin switches, is connected to the input and output of the harmonics filter, respectively, the other fixed contacts of all 2K three-pin switches of the harmonics filter are connected to the common bus and are normally closed with the corresponding moving contacts, each range filtering unit contains the main filter element, the input of which is the input of the range filter unit, and an additional filter element, output to otorogo is the output of the band-pass filtering node, as well as the second switch of radio signals, the signal input of which is combined with the output of the main and the input of the additional filtering elements, the signal output of the second switch of radio signals is connected to a common bus, and its control input is the control input of the band-filter node, the control inputs of all range filter nodes combined with the control input of the harmonic filter. 7. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set, the demodulator is made in the form of series-connected OFDM signal demodulation units, the input and control input of which are respectively the input and additional input of the demodulator, and the parallel-serial converter, the output of which is the output of the demodulator. 8. The duplex high-speed short-wave radio communication system according to claim 1, characterized in that in each transceiver set, the clock demodulator is made in the form of a series-connected amplitude detector, the input of which is the input of the clock demodulator, and the regenerator, the output of which is the output of the clock demodulator.

Images