RU2405273C1 - Demodulator of phase-shift signals - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention can be used in receiving devices for demodulation of phase-shift signals using classical methods of shaping of reference voltage. Essence of invention consists in application of two delay elements, two phase changers, three amplifiers with direct and inverted outputs, three commutators and one summing limiting amplifier for elimination of phase inversion, as well as three additional phase detectors, three threshold devices and three toggle flip-flops for indication and control of phase slue.

EFFECT: eliminating sufficient disadvantage of methods - inverse operation phenomenon.

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Description

The invention relates to radio engineering and can be used in receiving devices for demodulating phase-shifted signals.

A device for demodulating phase-shifted signals is described in the book “Penin P.I. Digital information transmission systems. Textbook for universities. M., Sov. Radio, 1976, p.152 ", containing a phase detector combined at the input, the input and output of which are the input and output of the device, respectively, and a device for generating a reference voltage, the output of which is connected to the second input of the phase detector. The disadvantage of this device is the low noise immunity, characterized by the fact that under the influence of interference the polarity of the output signal can change to inverse, which leads to an erroneous reception of a combination of transmitted characters.

There is also known a device for demodulating phase-shifted signals according to the author's certificate (AS) of the USSR No. 1483666, M. Kl ⁴ H04L 27/22, containing a serially connected driver of the meander, the input of which is the input of the device, the adder modulo two and the D-trigger, the output of which is the output of the device, and the D-input is connected to the output of the square wave driver, as well as two frequency multipliers connected in series, the input of which is connected to the input of the square wave driver, a clock generator and a shift register, output otorrhea connected to the second input of the modulo two adder, a second input coupled to the output of the square wave. The disadvantage of this device is the low noise immunity at the moments of a low level of the input signal (the moments when the sine wave is near zero), in this case, the effect of noise at the input of the square wave driver will result in the appearance of spurious pulses on the D-input of the trigger and incorrect reception of the code combination.

The closest analogue is the device described in the book “Penin P.I. Digital information transmission systems. Textbook for universities. M., Sov. Radio, 1976, p.152 ", containing a phase detector combined at the input, the input and output of which are the input and output of the device, respectively, and a device for generating a reference voltage.

To improve noise immunity, a phase-manipulated signal demodulator is proposed, comprising a phase detector combined at the input, the first input and output of which are the input and output of the device, respectively, and a reference voltage generating device, characterized in that a first amplifier, the input of which is connected to the output, is connected in series reference voltage generating devices, a first switch summing an amplifier-limiter, the output of which is connected to the second input of the phase a vector, the inverse output of the first amplifier is connected to the second input of the first switch, the first delay element is connected in series, the input of which is connected to the output of the reference voltage generating device, the first phase shifter, the second amplifier and the second switch, the output of which is connected to the second input of the summing limiter amplifier, and the inverse output of the second amplifier is connected to the second input of the second switch, the second delay element is connected in series, the input of which is connected to the output the first delay element, the second phase shifter, the third amplifier, the third switch, the output of which is connected to the third input of the summing amplifier-limiter, and the inverse output of the third amplifier is connected to the second input of the third switch, a second phase detector connected in series, the first input of which is connected to the output of the summing amplifier -limiter, and the second input to the output of the third switch, the first threshold device, the first counting trigger, the output of which is connected to the control input of the third comm an ator, connected in series with a third phase detector, the first input of which is connected to the output of the summing amplifier-limiter, and the second input is connected to the output of the second switch, a second threshold device, and a second counting trigger, the output of which is connected to the control input of the second switch, and the fourth phase detector is connected in series , the first input of which is connected to the output of the summing amplifier-limiter, and the second input is to the output of the first switch, the third threshold device, the third counting trigger, exit for which it is connected to the control input of the first switch.

The drawing shows a diagram of the device. It depicts:

1 - a device for forming a reference voltage;

2, 14, 17, 20 - the first, second, third and fourth phase detectors, respectively;

4, 9, 13 - the first, second and third switches, respectively;

5 - summing amplifier limiter;

15, 18, 21 - the first, second and third threshold devices

respectively;

6, 10 - the first and second delay elements, respectively;

7, 11 - the first and second phase shifters, respectively;

16, 19, 22 - the first, second and third counting triggers, respectively.

The demodulator comprises: a reference voltage generating device 1, a first phase detector 2, a first amplifier 3, a first switch 4, a summing limiter amplifier 5, a first delay element 6, a first phase shifter 7, a second amplifier 8, a second switch 9, a second delay element 10, the second phase shifter 11, the third amplifier 12, the third switch 13, the second phase detector 14, the first threshold device 15, the first counting trigger 16, the third phase detector 17, the second threshold device 18, the second counting trigger 19, the fourth phase detection OP 20, third threshold device 21, third counting trigger 22.

The device operates as follows. In the initial state, the first 16, second 19 and third 22 counting triggers are set to zero. The first 4, second 9, third 13 switches are installed in such a way that they transmit signals from the direct outputs of the first 3, second 8 and third 12 amplifiers to the output. At the inputs of the second 14, third 17 and fourth 20 phase detectors there are common-mode signals and a low signal level is set at their outputs. Using phase shifters 7 and 11, such a phase of the signals is set at the inputs of the summing amplifier of the limiter 5 so that the signal at its output is maximum (without the limiting mode). The threshold at the first 15, second 18 and third 21 threshold devices is set so that a signal close to the minimum signal level from the outputs of the second 14, third 17 and fourth 20 phase detectors corresponds to a logical zero. If this level is exceeded, a logical unit is recorded.

The signal from the device for forming the reference voltage 1 is supplied simultaneously to the first amplifier 3 and the first delay element 6. From the direct output of the first amplifier 3, the signal through the first switch 4 is fed to the first input of the summing amplifier-limiter. After the first delay element 6, the delayed signal is fed simultaneously to the second delay element 10 and to the first phase shifter 7. From the output of the phase shifter 7, the signal goes to the second amplifier 8, from the direct output of which through the second switch 9 it goes to the second input of the summing amplifier-limiter 5. After the second delay element 10, the signal acquires a delay (relative to the device for generating the reference voltage 1) equal to the total delay time of the first 6 and second 10 delay elements, and enters the second phase schatel 11, then to the direct output of the third amplifier 12, and then via the third switch 13 to the third input of the summing amplifier-limiter 5.

At the inputs of the second 14, third 17 and fourth 20 phase detectors there are common-mode signals, so there will be a minimum signal at their outputs. The outputs of the first 15, second 18 and third 21 threshold devices will be a signal of zero level. The first 16, second 19 and third 22 counting triggers remain in the zero state. The first 4, second 9 and third 13 switches remain in their original state. At the inputs of the summing amplifier-limiter 5 there are in-phase signals. After addition, amplification and limitation in the summing amplifier-limiter 5, the signal is supplied to the second (reference) input of the first phase detector 2.

After the inversion of the signal from the output of the device for forming the reference voltage 1, the signal passes through the first switch 4 and is fed to the input of the summing amplifier-limiter 5 with the opposite phase. Moreover, due to delays in the delay elements 6 and 10, the phase of the signals at the outputs of the second 9 and third 13 switches will remain unchanged. The amplitudes of the two signals on the summing amplifier-limiter 5 add up and one is subtracted. Since the gain of the summing amplifier-limiter 5 is selected so that a signal with such a level at the input would be maximum at the output, but would not lead to limitation, the output of the summing amplifier-limiter 5 will remain the signal of the same level as it was, and with the same phase as before the inversion.

In this case, the opposite phase signals will appear at the inputs of the fourth phase detector 20 and the signal at its output will change its level to high. At the output of the third threshold device 21, the signal from the zero level will change to a single one, along the rising edge the third counting trigger 22 will go into a single state. The first switch 4 will switch to the inverse output of the first amplifier 3, the phase of the signal at the output of the first switch 4 will change to the original. At the inputs of the summing amplifier-limiter 5, in-phase signals will again be present, it will switch to the limiting mode, but the phase of the signal at the reference input of the phase detector 2 will not change. In this case, the inputs of the fourth phase detector will again have in-phase signals and the signal at its output will change to low. The pulse at the input of the third counting trigger 22 will end, leaving it in a single state.

Then the signal with the inverse phase will appear at the output of the first 6 delay element, the phase of the signal at the direct output of the second amplifier 8 and at the output of the second switch 9 will change to inverse relative to the initial one. At the inputs of the summing amplifier-limiter 5 there will be two signals with the main phase and one with the inverse. In this case, again, the amplitudes of the two signals in the summing amplifier-limiter 5 add up and one is subtracted, the amplifier exits the limiting mode with the same output signal level, but the phase of the output signal remains unchanged.

At this time, antiphase signals will appear at the inputs of the third phase detector 17 and the signal at its output will change its level to high. At the output of the second threshold device 18, the signal from the zero level will change to a single one, on the leading edge the counting trigger 19 will go into a single state, and the second switch 9 will switch from direct to the inverse output of the second amplifier 8. At the same time, three inputs at the inputs of the summing amplifier-limiter 5 in-phase signal and it will go into limiting mode. In this case, the phase at its output and at the reference input of the phase detector 2 will remain unchanged.

Similarly, when a signal with an inverse phase appears at the output of the second delay element 10, the phase of the signal at the direct output of the third amplifier 12 and the third switch 13 will change to inverse, two signals with the main phase and one with the inverse will be present at the inputs of the summing amplifier-limiter 5 and it will exit the restriction mode. At the same time, at the output of the summing amplifier-limiter 5, the signal remains with the previous phase.

At this time, antiphase signals will appear at the inputs of the second phase detector 14 and the signal at its output will change its level to high. At the output of the first threshold device 15, the signal from the zero level will change to a single one, the first counting trigger 16 will go into a single state. The third switch 13 will switch to the inverse output of the third amplifier 12. As a result, the common mode signals will again be present at the inputs of the summing amplifier-limiter 5 and it will switch to the limiting mode, but the phase of the signal from its output will not change.

Common-mode signals will appear at the inputs of the second phase detector 14, and the output will be low. At the input of the first counting trigger 16, the pulse ends, leaving it in a single state.

At the end of these events, the first 4, second 9, third 13 switches transmit the output signals from the inverse outputs of the first 3, second 8 and third 12 amplifiers, the first 16, second 19 and third 22 counting triggers are in a single state, and the state of other devices is not different from the original.

If the phase of the signal is reversed again, the summing amplifier-limiter 5 exits the limiting mode, keeping the signal phase at the output unchanged, and a high level appears at the output of the fourth phase detector 20. At the output of the third threshold device 21, zero will change to unity, the third counting trigger 22 will be set from one to zero, and the first switch 4 will switch to transmitting the signal from the direct output of the first amplifier 3. The summing amplifier-limiter 5 will enter the limiting mode, keeping the signal phase at output unchanged. This will lead to the return of the signal levels from the outputs of the fourth phase detector 20 and the third threshold device 21 to its original state.

Then the process will be repeated in the chain: the third phase detector 17, the second threshold device 18, the second counting trigger 19. The second switch 9 will switch from the inverse output to the direct one. The third phase detector 17 and the second threshold device 18 will return to their original state, and the state of the second counting trigger 19 will remain unchanged.

A similar process will go through the chain: the second phase detector 14, the first threshold device 15, the first counting trigger 16. The third switch 13 will switch from the inverse output to the direct one. The second phase detector 14 and the first threshold device will return to their original state, and the state of the first counting trigger 16 will not change.

In all cases, at the output of the summing amplifier-limiter 5, the amplitude and phase of the output signal will remain unchanged.

Thus, in a circuit that implements synchronous reception of a phase-shifted signal, when the phase is inverted from the output of the device for generating the reference voltage, the phase at the reference input of the first phase detector 2 remains unchanged. Therefore, the claimed device noise immunity is higher than that of analogues.

In the claimed device, the summing amplifier-limiter can be implemented on a high-speed operational amplifier. If we consider the signal levels at its inputs to be the same, then its gain is selected so that when the level of the input signal is such as at one of the inputs, it gives a signal of maximum level without restriction. If this level is exceeded, it must enter restriction mode. The following requirement is imposed on delay elements.

where t _E3 is the delay time of each of the delay elements;

t _PD - delay time of the second 14, third 17 and fourth 20 phase detectors;

t _PU - delay time of each of the threshold devices;

t _SCH - delay time of each of the counting triggers;

t _K is the delay time of each of the switches, which in total will be no more than fifty microseconds.

This requirement is met in excess by the delay device on the quartz (or SAW) resonator. The delay time of such a device will be 2Q / F ₀ ~ 0.04 seconds (for a quartz resonator) and ~ 0.005 C (for a SAW resonator), where Q = 10 ⁵ is the quality factor of a quartz crystal, and Q = 10 ⁴ is a SAW resonator, F ₀ = 50 MHz is the frequency of the reference signal.

The remaining elements of the device can be performed on a standard element base and do not have any features.

Claims (1)

A phase-shifted signal demodulator comprising a phase detector combined at the input, the first input and output of which are the input and output of the device, respectively, and a reference voltage generating device, characterized in that a first amplifier is connected in series, the input of which is connected to the output of the reference voltage generating device , the first switch, the summing amplifier-limiter, the output of which is connected to the second input of the phase detector, the inverse output of the first amplifier The device is connected to the second input of the first switch, the first delay element is connected in series, the input of which is connected to the output of the reference voltage generating device, the first phase shifter, the second amplifier and the second switch, the output of which is connected to the second input of the summing amplifier-limiter, and the inverse output of the second amplifier is connected to the second input of the second switch, a second delay element connected in series, the input of which is connected to the output of the first delay element, the second phase rotation eh, the third amplifier, the third switch, the output of which is connected to the third input of the summing amplifier-limiter, and the inverse output of the third amplifier is connected to the second input of the third switch, a second phase detector connected in series, the first input of which is connected to the output of the summing amplifier-limiter, and the second the input to the output of the third switch, the first threshold device, the first counting trigger, the output of which is connected to the control input of the third switch, the third a basic detector, the first input of which is connected to the output of the summing amplifier-limiter, and the second input to the output of the second switch, a second threshold device, a second counting trigger, the output of which is connected to the control input of the second switch, the fourth phase detector, the first input of which is connected to the output of the summing amplifier-limiter, and the second input to the output of the first switch, the third threshold device, the third counting trigger, the output of which is connected to the control input of the first th switch.