RU2286008C1 - Impulse generator - Google Patents

Abstract

FIELD: impulse engineering for use in systems for adjusting several parameters with time-impulse control, and also synchronization.

SUBSTANCE: generator contains (on dwg. 1) elements XOR 7,8,9, inverter 11, AND elements 12,13, diodes 2,3, resistors 4,5, capacitor 6, input bus 1, additional input bus 10 for injecting signal for controlling impulse type at outputs of AND elements 12,13, output buses 14-16.

EFFECT: expanded functional capabilities due to production of impulses, independently adjusted by duration, generated along frontal and back fronts of input impulses (by convention called uneven and even, respectively), and packs with different number of impulses.

4 cl, 3 dwg

Description

The invention relates to a pulse technique and can be used mainly in various systems of simultaneous automatic or semi-automatic control of several parameters with time-pulse control, as well as in various synchronization systems.

There are various pulse shapers that use the principle of doubling the frequency of input pulses by generating output pulses along the leading and trailing edges of the input pulses (see, for example, R. Melen, G. Garland. Integrated circuits with CMOS structures. M .: Energy, 1979, p. 124, Fig. 6-22; or the Handbook of integrated circuits. Edited by B.V. Tarabrin. M: Energy, 1980, p. 669, Fig. 5-142). The disadvantage of these formers is too small functionality.

The closest to the circuit design is a pulse shaper containing an input and three output buses, an exclusive OR gate, an RC serial circuit, an inverter, and two AND logic gates, the outputs of which are connected to the first and second output buses, respectively the first inputs of these elements are combined and connected to the output of the EXCLUSIVE OR element and to the third output bus, the first input of the EXCLUSIVE OR element is connected to the input bus, and the second input is connected to the common point of the RC circuit, the second capacitor output which is connected to a common bus. (See USSR Author's Certificate No. 1283953, 4 Н 03 К 5/01, with priority dated July 24, 1985).

The disadvantage of this pulse shaper is the limited functionality.

The objective is to expand the functionality of the driver, which should allow you to receive independently adjustable in duration pulses generated on the leading and trailing edges of the input pulses (we will conditionally call them odd and even pulses, respectively), transmit odd and even pulses to different output buses with the ability to change in places the types of pulses on these buses. An additional task for individual cases of the use of the shaper is to obtain the ability to generate pulse packets on the output buses with a given, generally different, number of pulses in each packet using external signals, or to transmit identical pulses (either even or odd) to two output buses in the form of both continuous sequences and bursts with a different number of pulses in a packet on each bus.

For this, a pulse shaper containing an input and three output buses, an EXCLUSIVE OR logic element, a serial RC circuit, an inverter and two AND logic elements whose outputs are connected to the first and second output buses, respectively, the first inputs of these elements combined and connected to the output of the EXCLUSIVE OR element and to the third output bus, the first input of the EXCLUSIVE OR element is connected to the input bus, and the second input is connected to a common point on the RC circuit, the second output of the capacitor of which is connected to the common bus, equipped with additionally with two EXCLUSIVE OR elements, two diodes and a second resistor, one output of which is connected to a common point on the RC circuit, the second outputs of both resistors are connected via an on-board diode to the input bus, to which the first inputs of two additional EXCLUSIVE OR elements are connected between the second inputs of which an inverter is connected, connected additionally by its input to the second input bus for controlling the type of pulses (even or odd) on the first two output buses, and the outputs of the elements are EXCLUSIVE OR "connected to the second inputs, respectively, of the elements" AND ". Additional differences are: a) the use of “3I” elements as “And” elements, the third inputs of which are both connected together or separately either to the power bus or to additional input buses for supplying modeling pulses to them to form packs on the first two output buses pulses with a given number of pulses in each packet; c) the use of the fourth element “EXCLUSIVE OR” as the inverter, the second input of which is either connected to the power bus (inverter mode) or to the additional input bus, supplying a “zero” signal, into which both elements “AND” are transferred to the transmission mode the first two output buses of identical pulses to each other (even or odd); c) the use of potentiometers as resistors.

Figure 1 shows the main circuit of the pulse shaper, figure 2 shows the stylized types of pulses at individual points in the circuit, and figure 3 shows the circuit of the shaper with all the additional differences.

In the drawings, the standard designation of electrical elements is applied, where

1 - the first input bus;

2, 3 - diodes;

4, 5 - potentiometers;

6 - capacitor;

7, 8, 9 - elements "EXCLUSIVE OR";

10 - second input bus;

11 - inverter or element "EXCLUSIVE OR";

12, 13 - elements "And";

14, 15, 16 - the first, second and third output buses;

17, 18, 19 - additional control inputs;

And ₁ And ₁₀ - signals on the input buses, respectively, 1 and 10;

And ₆ - type of voltage across the capacitor;

And ₁₄ , And ₁₅ , And ₁₆ - signals on the output buses, respectively 14, 15, 16.

In Fig. 1, the input bus 1 is connected through resistively connected diodes 2 and 3 to resistors 4 and 5, respectively, which are potentiometers with rheostat switching, the second terminals of which are connected to the capacitor 6 connected to the common bus and to the second input of the EXCLUSIVE OR logic element 7, the first input of which is combined with similar inputs of similar elements 8 and 9 and connected to the input bus 1. The second input bus 10 is connected to the second input of the element 8 and to the input of the inverter 11, the output of which is connected to the second input of the element 9. The outputs of the elements 9 and 8 are connected to the first inputs of the elements "And", respectively 12 and 13, the outputs of which are connected to the first two output buses, respectively 14 and 15. The second inputs of the elements "And" 12 and 13 are combined and connected to the output of the element EXCLUSIVE OR 7 and with a third output bus 16.

Figure 2 presents the stylized pulses:

And ₁₀ - at the input of the second input bus 10;

And ₁ - at the first input 1;

And ₁₆ - pulses with doubled frequency on the third output bus 16;

And ₆ is the voltage form on the capacitor 6;

And ₁₄ and ₁₅ are pulses on the first 14 and second 15 output buses.

Figure 3 shows a variant of the circuit of figure 1 with all the additions. Here, the inverter 11 is made on an EXCLUSIVE OR element, the second input of which is connected to the second input bus 10, and the first input is connected to the third input bus 17, which in general can be connected to the power bus (inverter mode) or to the common bus ( “zero”) (repeater mode). As the "And" elements 12 and 13, three-input elements "3I" are installed here, the third inputs of which are connected, respectively, to the additional input buses 19 and 18.

When applied to the input bus 1 and ₁ pulses, they arrive simultaneously at the inputs of the first three elements "exclusive OR" 7, 8 and 9, and through diode 2 and resistor 4 - to a second input element 7 and discharged to a condenser 6. The combination unit ""at the first input and" zero "at the second input of the element 7 causes the appearance on its output, the output bus 16 and at the combined inputs of the elements" And "12 and 13" single "pulse And ₁₆ . Since on the second bus 10 at this time the "And" signal is And ₁₀ , then at the output of the element 8 there will appear a "single" signal, which through the And element 13 will go to the second output bus 15 in the form of an And ₁₅ pulse.

Due to the presence of an inverter 11 at the output of element 9, and through the element "And" 12 and on the first output bus 14, the signal will be "zero". At the same time, through the diode 2 and resistor 4, the charge of the capacitor 6 begins with a time constant t ₁ = (R ₄ + R ₂ ) · C ₆ , where

t ₁ - charge time constant C ₆ ;

R ₄ is the resistance of the resistor 4;

R ₂ is the internal resistance of the diode 2 in the forward direction;

C ₆ - capacitor 6.

As soon as the voltage And ₆ on the capacitor 6 reaches the response level of element 7, equal to from 30% to 70% of the supply voltage (see, for example: R. Melen, G. Garland. Integrated circuits with CMOS structures. M .: Energy, 1979 d., p. 107), at the output of element 7, the combined inputs of the elements 12 and 13 and at the output buses 15 and 16, the voltage will become zero. The capacitor 6 will continue to be charged at this time to the voltage level And ₁ on the input bus 1. As soon as the voltage pulse And ₁ on the input bus 1 becomes "zero", at the output of the element 7, the inputs of the elements "And" 12 and 13 on the output bus 16 will pulse and _16, and as a "zero" signal is sent simultaneously to the first inputs of elements 8 and 9, the "zeros" at both inputs of the element 8 will "zero" at its output and the first input element "and" 13, because of the which, on the output bus 15, the voltage will remain "zero". Since there is a “single” signal at the second input of element 9 due to the inverter 11, the arrival of a zero signal at its first input will cause the appearance of a single signal at its output, the first input of the element “And” 12 and on the first output bus 14 in the form of a pulse And ₁₄ . At the same time, the discharge of the capacitor 6 through the resistor 5 and diode 3 with a time constant t ₂ = (R ₅ + R ₃ ) · C ₆ , where

t ₃ - discharge time constant C ₆ ;

R ₅ is the resistance of the resistor 5;

R ₃ is the internal resistance of the diode 3 in the forward direction.

As soon as the voltage across the capacitor 6 reaches the threshold of operation of the element 7, the pulses And ₁₄ and And ₁₆ will end. Next, the process of forming pulses will be repeated in the same way when the next pulses arrive at the input bus 1. This will happen until the change of the "zero" signal And ₁₀ to "single". Such a change of signal will change the signal at the second input of element 9 from "single" to "zero", and at the second input of element 8 from "zero" to "single". This change of the And ₁₀ signal will change the appearance of the signals on the first 14 and on the second 15 output buses. On bus 14, even pulses generated on the trailing edge of the input pulses And _{1 will be} replaced by odd pulses formed on the leading edge of the pulses And ₁ . On the output bus 15, the opposite is true: odd pulses are replaced by even ones. The duration of the odd pulses is set by potentiometer 4, and the even ones by potentiometer 5 independently of each other.

The operation of the circuit of figure 3 is similar to that described with the following additions:

1. If the additional input buses 17, 18, 19 are connected to the power bus, the circuit of FIG. 3 will be identical to the circuit of FIG. 1.

2. If a zero signal is supplied to bus 17, then element 11 will turn from an inverter into a repeater, therefore, the input signal from the second input bus 10 will simultaneously arrive in the same phase to the second inputs of elements 8 and 9, this will lead to The "signal on bus 10 to the output buses 14 and 15 will only pass odd pulses at a time, and with a" single "signal on the bus 10 to the output buses 14 and 15, only even pulses will pass.

3. When using input buses 18 and 19 to supply modulating pulses to them from external sources, packets of the corresponding pulses will be formed on the output buses 14 and 15, and the number of pulses in the packets will depend on the duration of the “single” pulses on the input buses 18 and 19 . With "zero" signals on these buses on the output buses 14 and 15, pulses will be absent.

The described properties of the presented circuits allow the use of such pulse shapers to solve a variety of problems in automatic and semi-automatic control systems with time-pulse control.

Claims (4)

1. A pulse shaper containing an input and three output buses, an exclusive OR logic element, a serial RC circuit, an inverter and two AND logic elements, the outputs of which are connected to the first and second output buses respectively, the first inputs of these elements are combined and connected to the output of the element EXCLUSIVE OR to the third output bus, the first input of the EXCLUSIVE OR element is connected to the input bus, and the second input is connected to the common point of the RC circuit, the second output of the capacitor of which is connected to the common bus, characterized in that it is additionally equipped with two EXCLUSIVE OR elements, two diodes and a second resistor, one output of which is connected to a common point on the RC circuit, the second outputs of both resistors are connected through an on-board diode to the input bus, to which the first inputs of two additional EXCLUSIVE OR elements are connected, between the second the inputs of which an inverter is connected, connected additionally by its input to the input second input bus for controlling the type of pulses (even or odd) on the first two output buses, and the outputs of the elements are EXCLUSIVE SCREEN OR connected to the second inputs, respectively, of elements I. 2. The pulse shaper according to claim 1, characterized in that the logic elements AND are applied to the ZI elements, the third inputs of which are both connected together or separately either to the power bus or to the additional input buses to supply modulating pulses to them to form the first output buses of bursts of pulses with a given number of pulses in each burst. 3. The pulse shaper according to claim 1, characterized in that the fourth element is EXCLUSIVE OR, the second input of which is either connected to the power bus (inverter mode) or to an additional input bus, the supply of a "zero" signal to which both element And into the transmission mode on the first two output buses of identical pulses to each other (even or odd). 4. The pulse shaper according to claim 1, characterized in that potentiometers are used as resistors.

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