RU2036550C1 - Pulse shaper - Google Patents

Abstract

FIELD: pulse technique. SUBSTANCE: pulse shaper has reference-frequency generator 1, frequency divider 2, clearing bus 5, output bus 6, majority elements 7, 8 one-shot multivibrator 9. EFFECT: improved design. 2 cl, 1 dwg

Description

 The invention relates to a pulse technique and can be used in computer technology and control systems.

 Known self-correcting frequency divider, which can be used as a device for generating pulses (ed. St. USSR N 1156570, CL N 03 K 23/00, 1984), containing the first and second frequency dividers, the counting inputs and outputs of which are connected to corresponding input and output buses, a memory element, the first and second coincidence elements, an EXCLUSIVE OR element, and the first and second pulse shapers. The inputs of the first and second pulse shapers are connected to the output of the first and second frequency dividers, the first outputs, respectively, with the first and second inputs of the memory element, the second outputs, respectively, with the first and second inputs of the EXCLUSIVE OR element. The output of the EXCLUSIVE OR element is connected to the first inputs of the first and second coincidence elements, the second inputs of which are connected to the corresponding outputs of the memory element, and the outputs to the control inputs of the respective frequency dividers.

 The disadvantages of this device are the complexity and high power consumption, especially when received on the input bus pulses with a high repetition rate, which is associated with the presence of two frequency division channels in the device.

 Known redundant frequency divider, which can be used as a device for generating pulses (ed. St. USSR N 1579423, class N 03 K 23/00, 1989), containing the first and second frequency dividers, the clock inputs of which are connected to the input bus , a pulse shaper and an output bus, first and second majority elements, the first inputs of which are connected to the output of the first, and second inputs with the output of a second frequency divider, the control inputs of which are connected to the first output of the pulse shaper, the second output of which is connected to tim input of a first majority element, whose output is connected to the input of the pulse shaper, the third output is connected to a third input of the second majority element, whose output is connected to the output bus.

 The disadvantages of this device are the complexity and high power consumption, especially at a high pulse repetition rate on the input bus, due to the presence of two frequency division channels in the device.

 Closest to the claimed device in technical essence is a pulse shaper (ed. St. USSR N 978334, class N 03 K 5/00, 1981), containing a reference frequency generator, frequency divider, gating unit, counting trigger and counting trigger and D-trigger. The output of the reference frequency generator is connected to the input of the frequency divider. The output of the counting trigger is connected to one of the inputs of the gating block. The D-input of the D-flip-flop is connected to the output of the frequency divider, the direct output with the input to the zero of the final discharge of the frequency divider, and the inverse output with the counting input of the counting trigger, the input to the unit of which is connected to the output of the frequency divider. The other input of the strobe block is connected to the control output of the frequency divider, and the output of the strobe block with the C-input of the D-trigger.

 The disadvantage of this device is the low reliability. This is due to the presence of single failures in the pulse shaper circuit, leading to the premature appearance of pulses at the shaper output. A single failure of any of the bits of the "miscalculation" frequency divider (repetition of the pulses acting at its input at the output of the discharge) leads to a doubling of the pulse frequency at the output of the frequency divider, and, consequently, at the output of the pulse shaper.

 The aim of the invention is to increase the reliability of the pulse shaper by eliminating the increase in the frequency of the generated pulses for any single element failures.

 This goal is achieved by the fact that in the pulse shaper containing the reference frequency generator connected to the clock input of the frequency divider, the zeroing input of which is connected to the zeroing bus, and the output bus, the first and second majority elements and a single-shot are introduced, the output of which is connected to the first input of the first majority element, the second input of which is connected to its output and the output bus, the third input with the main output of the frequency divider and the first input of the second majority element, the second input of which of the connections to the control output of the frequency divider, a third input to its output, the reset input terminal of the discharge frequency divider and the first input of the monostable trigger, the second trigger input of which is connected to the bus reset. In addition, the single-shot contains three OR-NOT elements, an integrating RC circuit and a diode, the anode of which is connected to the output of the integrating RC circuit and to the first input of the first OR-NOT element, a cathode to the input of the integrating RC circuit and to the output of the second OR element -NOT, the first and second inputs of which are, respectively, the first and second inputs of the start of the one-shot and are connected respectively to the first and second inputs of the third OR-NOT element, the output of which is the output of the one-shot and connected to the third input of the second OR-NOT element and the second input a first OR-NO element whose output is connected to a third input of the third OR-NO element.

 The specified set of features allows to increase the reliability of the pulse shaper by eliminating the increase in the frequency of the generated pulses in case of single element failures.

 A technical solution is known (ed. St. USSR N 1455980, class N 03 K 23/00, 1986), in which the following distinguishing feature is found: the output of the majority element is connected to one of its inputs.

 The properties of the claimed and known technical solutions, due to the presence of this feature, are the same, namely: the majority element is switched to any state only if there are corresponding signals at the other two inputs, which eliminates the increase in the output frequency as a result of single element failures.

 Known technical solutions containing the remaining essential features distinctive from the prototype were not found, which allows us to conclude that the claimed device meets the criterion of "Significant differences".

 The drawing shows a diagram of a pulse shaper.

 The pulse generator comprises a reference frequency generator 1, a frequency divider 2 with a main 3 and control 4 outputs, a zeroing bus 5, an output bus 6, the first 7 and second 8 major elements and a single-shot 9. The output of the reference frequency generator 1 is connected to the clock input of the frequency divider 2 , the zeroing input of which is connected to the zeroing bus 5 and one of the start inputs of the one-shot 9, the output of which is connected to the first input of the majority element 7. The second input of the majority element 7 is connected to the output bus 6 and the output of the majority element ententa 7, and the third input with the main output 3 of the frequency divider 2 and the first input of the majority element 8. The second input of the majority element 8 is connected to the control output 4 of the frequency divider 2, and the third input with the output of the majority element 8, the input of zeroing the final discharge 2.n frequency divider 2 and another start-up input of a single-shot 9. The control input 4 of frequency divider 2 is the output of one of the bits 2.i of frequency divider 2, except for the last 2.n (where i1,2, n-1). The one-shot 9 contains the first 10, second 11 and third 12 OR-NOT elements, the integrating RC circuit 13 and the diode 14. The anode of the diode 14 is connected to the output of the integrating RC circuit 13 and to the first input of the OR-NOT 10 element, and the cathode to the input integrating RC-circuit 13 and to the output of the element OR NOT 11. The first and second inputs of the element OR NOT 11 are respectively the first and second inputs of the start of the one-shot 9 and are connected respectively to the first and second inputs of the element OR NOT 12. The output of the element OR- NOT 12 is the output of a single-shot 9 and is connected to the third input of the element OR NOT 11 and the second input of the OR-NOT 10 element, the output of which is connected to the third input of the OR-NOT 12 element.

 The reference frequency generator 1 is made according to the multivibrator scheme on inverters with quartz frequency stabilization (B. Altshuller et al. Quartz oscillators. Reference manual. M. Radio and communications, 1984, p. 63, Fig. 5.6 b).). In generator 1, elements of the 564LN2 microcircuit were used as inverters, as a quartz resonator PE1, a quartz resonator RG-27 with a resonant frequency of 500 kHz, as a resistor R1 resistor C2-33N-0, 125-1 MΩ ± 5%. The frequency divider 2 is made flip-flops of the 564TV1 chip with the extension of the R-input in the last category using the EXCLUSIVE OR element of the 564LP2 chip. The majority elements 7, 8 are made on the 564LP13 chip. The OR-NOT 11,12 elements are made on the 564LE10 microcircuit, the OR-NOT 10 elements on the 564LE5 microcircuit. The integrating RC circuit 13 is made on a resistor C2-33H-0.125-510 kOhm ± ± 5% and a capacitor K10-17s-a-H50-2.2 nF ± 5%. As a diode 14, a 2D522B diode is used.

 The generator 1 of the reference frequency can be performed as in ed. USSR N 1450711, class H 03 K 3/02, 1987. Frequency divider 2, majority elements 7.8, OR-NOT elements 10,11,12 can be performed on CMOS chips of other series, for example K561, 1526. As a resistor of an integrating RC circuit 13, resistors of type C2-23 and others can be used. Capacitors of type K10-47 and others as a capacitor. As a diode 14, a diode 2D510A and others can be used.

 The pulse generator operates as follows.

 In the initial state, the logical “1” level is present on the zeroing bus 5, which keeps the triggers of the bits of the frequency divider 2 and the OR-NOT 11 and 12 elements in the logical “0” state, which ensures that the majority elements 7.8 are set to the logical “0” state. The OR-NOT element 10 is in the logical "1" state, the capacitor of the integrating RC circuit 13 is discharged. The output pulses of the reference frequency generator 1 are supplied to the clock input of the frequency divider 2, but do not change its state.

 When the logic level “0” is zeroed to the bus 5, the pulses of the reference frequency generator 1 begin to change the state of the frequency divider 2. At the control output 4 of the frequency divider 2, pulses of positive polarity will appear, which are fed to the second input of the majority element 8, but cannot change its state.

 When the logic level “0” is reset to bus 5, which passes to the first inputs of the OR-NOT 11 and 12 elements, the OR-NOT 11 element switches to the logical “1” state and the capacitor starts to charge slowly on the integrating RC circuit 13. The voltage at the output of the integrating RC circuit 13, and therefore, at the first input of the OR-NOT 10 element increases. When the specified voltage reaches the threshold, the OR-NOT 10 element switches to the logical "0" state and causes the OR-NOT 12 element to switch to the logical "1" state, from the output of which the logical "1" level goes to the second input of the OR-NOT 10 element , confirming its state of logic "0", and at the first input of the majority element 7, but does not change its state.

 When switching the trigger of the final discharge 2n of the frequency divider 2, the logic level "1" goes to the main output 3 of the frequency divider 2 and then to the third input of the majority element 7 and to the first input of the majority element 8. At the same time, the logic level 4 is present on the control output 4 "0". Therefore, the majority element 8 remains in the logical "0" state, and the majority element 7 switches to the logical "1" state, forming a positive polarity pulse on the output bus 6.

 When the next pulse of positive polarity arrives at the control output 4 of the frequency divider 2, the majority element 8 switches to the logical "1" state and sets the initial state of the logical "0" to the final discharge of the frequency divider 2, as well as the OR-NOT 11 and 12 elements, which causes initialization of the logical "0" of the majority element 7 and the end of the pulse on the output bus 6. At the same time, the level of the logical "0" at the output of the OR-NOT 11 element causes a fast discharge of the capacitor of the integrating RC circuit 13 through the diode 14 and setting the logical "1" state of the element OR NOT 10. The one-shot 9 is set to the initial state. After that, the positive pulse at the control output 4 of the frequency divider 2 ends, the majority element 8 is set to the logical state "0" and starts the one-shot 9. Further, the work continues in a similar way.

 With single failures of the discharges of the frequency divider 2, causing a decrease in the period of the output pulses, the switching of the final discharge 2n to the logical state “1” will occur before the operation of the one-shot 9. Therefore, the majority element 7 will not switch and the output pulse on the bus 6 will not be formed. When the next pulse of positive polarity arrives at the control output 4, the majority element 8 switches and causes the final discharge 2 to be set to the initial state 2 of the frequency divider 2 and the one-shot 9. At the end of the pulse, the one-shot will start again at the control output 4.

 The description of the work confirms the normal functioning of the driver in the absence of element failures and the exclusion of the possibility of increasing the frequency of output pulses in case of failures of the frequency divider. The exception to the increase in the frequency of output pulses is achieved by threshold control of the period of the generated pulses using a single vibrator and blocking their passage to the output of the shaper when the period of the generated pulses is less than the pulse duration of the single vibrator.

 Thus, from the description of the work it is clear that the claimed object in comparison with the prototype has increased reliability due to the exclusion of an increase in the frequency of the generated pulses in case of single element failures.

 In this case, the duration of the single-shot pulse is set equal to 75% of the period of the generated pulses. The tolerance on the stability of a single-vibrator pulse should not exceed 30%. With a generator frequency of 500 kHz and a number of divider bits of 10, the final discharge will switch after 1024 μs. Therefore, the pulse duration of a single-shot should be equal to 768 ± ± 230 μs. With the response threshold of the first OR-NOT element equal to half the supply voltage, the time constant of the integrating RC circuit should be equal to 1100 μs.

 A laboratory model of a pulse shaper was made at the institute, tests of which confirmed the feasibility and practical value of the claimed facility.

Claims (2)

 1. The pulse generator, containing a reference frequency generator, the output of which is connected to the clock input of the frequency divider, the zeroing input of which is connected to the zeroing bus, and an output bus, characterized in that, in order to increase reliability, the first and second majority elements are introduced into it and one-shot, the output of which is connected to the first input of the first majority element, the second input of which is connected to its output and the output bus, the third input with the main output of the frequency divider and the first input of the second majority element ment, the second input of which is connected to the control output of the frequency divider, the third input is with its output, the zeroing input of the final discharge of the frequency divider and with the first input of the one-shot trigger, the second launch input of which is connected to the zeroing bus.  2. The pulse shaper according to claim 1, characterized in that the single-shot contains three elements OR NOT integrating an RC circuit and a diode, the anode of which is connected to the output of the integrating RC circuit and with the first input of the first element OR, NOT, the cathode with the input of the integrating RC circuits and the output of the second element OR NOT, the first and second inputs of which are respectively the first and second inputs of the start of the one-shot and connected respectively to the first and second inputs of the third element OR NOT, the output of which is the output of the one-shot and connected to the third the course of the second element OR-NOT and the second input of the first element OR NOT, the output of which is connected to the third input of the third element OR NOT.