RU182313U1 - DIGITAL SIGMA DELTA MODULATOR FOR POWER TRANSISTOR CONTROL - Google Patents

Abstract

The invention relates to pulse modulators, namely to a digital sigma-delta modulator for controlling power transistors, which includes a digital negative adder connected to an integrator digital adder, which is connected to a memory element, whose resolution input is connected to a truth table connected to two the high bits of the output of the memory element and the high bit of the result of the digital negative adder, and the output of the memory element is connected to a digital quantizer, the output of which is connected to eye of correction whose input is also connected to the pulse counter, the output correction unit is an output of the digital sigma-delta modulator for controlling the power transistors and the negative connected to the digital adder. The utility model provides increased accuracy in the formation of pulsed signals at the output of half-bridge power transistors controlled by a digital sigma-delta modulator.

Description

The utility model relates to pulse modulators and can be used in various fields of science and industry to create devices for controlling electric drives and other inductive-resistive loads.

First-order digital sigma-delta modulator is known from the prior art [Fujisaka N. et al. Bit-stream signal processing and its application to communication systems // IEE Proceedings-Circuits, Devices and Systems. - 2002. - T. 149. - No. 3. - C. 159-166.]. Such a device contains two adders, a memory element and a digital quantizer.

This device uses a single time slicing frequency for both input and output signals. Thus, when controlling power transistors having a maximum switching frequency of less than 100 kHz, the frequency of the input signal of the modulator should also not exceed 100 kHz. For systems using direct processing of pulsed signals [Fujisaka N. et al. Bit-stream signal processing and its application to communication systems // IEE Proceedings-Circuits, Devices and Systems. - 2002. - T. 149. - No. 3. - C. 159-166.], This leads to a significant decrease in the accuracy of the formation of the pulse signal at the output of the power transistor, which is a significant drawback of this device. Also, when controlling with this device semi-bridge and bridge circuits based on IGBT transistors, it is not possible to set a limit on the maximum opening time of the upper semi-bridge transistor, which in some cases can lead to spontaneous closing of the transistor and also reduce the accuracy of the output power formation signal.

The proposed utility model is aimed at solving a technical problem to eliminate these drawbacks.

The technical result achieved in this case consists in increasing the accuracy of generating pulse signals at the output of the half-bridge of power transistors controlled by a digital sigma-delta modulator.

The technical result is achieved by the fact that the digital sigma-delta modulator for controlling power transistors includes a digital negative adder connected to an integrator digital adder that is connected to a memory element, whose resolution input is connected to a truth table connected to the two high-order bits of the memory element output and the high bit of the result of the digital negative adder, and the output of the memory element is connected to a digital quantizer, the output of which is connected to the correction unit, to the input to orogo also connected a pulse counter, the output correction unit is an output of the digital sigma-delta modulator for controlling the power transistors and the negative connected to the digital adder.

These features of the utility model are significant and the combination of these features is sufficient to obtain the desired technical result.

The utility model is illustrated by drawings.

In FIG. 1 shows a block diagram of the claimed utility model. It contains a pulse counter 1, a digital negative adder 2, a digital integrator 3 adder, a memory element 4 with a recording enable input, a digital quantizer 5, a correction unit 6, and a truth table 7.

The device operates as follows. It receives a pulse stream encoded in such a way that a pulse with an amplitude of -1 corresponds to a two-bit code 11, a pulse with an amplitude of 1 corresponds to a two-bit code 01, and the absence of a pulse corresponds to a code 00. The codes of the input pulse flows go to the input of the digital negative adder 2, where without loss of accuracy, the digital sigma-delta modulator output for controlling power transistors obtained at the previous calculation step is subtracted from it. The result of the digital negative adder 2 is supplemented with an N-1 sign bit and fed to the first input of the digital adder of the integrator 3, to the second input of which the output of the memory element 4 is connected. The output of the digital adder of the integrator 3 is written to the memory element 4 in the presence of a write enable signal. The write enable signal is generated using the truth table 7, the input of which receives the two most significant bits of the output of the memory element and the most significant bit of the output of the digital negative adder 2. The output of the truth table 7 is generated according to table 1. The output of the memory element 4 is fed to a symmetric digital quantizer 5, which forms a two-bit code on its basis, which is transmitted to the correction unit 6. The dependence of the output of the digital quantizer 5 on its input is shown in FIG. 2. Also, the correction block 6 receives signals min_st and max_st from pulse counter 1. Pulse counter 1 calculates the number of consecutive pulses of the same name at the output of a digital sigma-delta modulator for controlling power transistors and comparing them with thresholds Nt and Nm. The threshold Nt determines the minimum period between switching the output that controls the power transistors. As soon as the pulse counter 1 exceeds the threshold Nt, a signal min_st is generated at its output. The threshold Nm determines the maximum period duration without switching the output signal. As soon as the pulse counter 1 exceeds the threshold Nt, a signal max_st is generated at its output. With any change in the output signal of the utility model, the pulse counter 1 and both of its outputs are reset to 0. Until the min_st signal appears, the output of the correction unit 6 remains unchanged regardless of the output of the digital quantizer 5. This ensures the necessary switching frequency of the power transistors different from the clock frequency of the elements 1-6 utility model. In the presence of the min_st signal, before the max_st signal appears, the output of the correction block 6 is equal to the output of the digital quantizer 5. When the max_st signal appears, the output of the correction block 6 is reversed. Thus, protection is provided against spontaneous switching of power IGBT transistors in bridge and semi-bridge circuits. Compensation of errors in the formation of the output signal of the utility model associated with the operation of the correction unit 6 is carried out due to negative feedback through the digital negative adder 2. Elements 1-6 change their outputs synchronously along the front of the common clock signal.

The performance of the proposed device was tested on the layout, which clearly demonstrated the receipt of the required technical result.

A digital sigma-delta modulator for controlling power transistors with parameters Nm = 1400 (corresponds to the maximum switching frequency of the output signal no higher than 71.429 kHz) and Nt = 30000 (corresponds to the maximum pulse width at the output of the modulator no more than 300 μs) was implemented on the basis of the Xilinx FPGA chip XC7A100T-1CSG324C, which was clocked by a generator with a frequency of 100 MHz. On the same FPGA, a well-known first-order digital sigma-delta modulator was implemented, the registers of which were clocked by the clk1 signal with a frequency of 71.429 kHz, generated using logic that changes the state of clk1 every 1400 FPGA clock cycles. The output of each of the modulators was connected to the IR21834S half-bridge driver, which in turn controlled two F2807S transistors. Using each modulator and a half-bridge connected to it in an inductive-resistive load with an electric time constant of 650 μs, a current was generated, which was measured using an ACS712T ELC-20A sensor, the output of which was digitized using a 12-bit ADC. During each experiment, a pulsed stream with a frequency of 100 MHz corresponding to the desired current level in the inductive-resistive load was applied to a digital sigma-delta modulator for controlling power transistors and a well-known first-order digital sigma-delta modulator operating at 71.429 kHz. Using a current sensor and ADC, a current change was recorded for 5 ms. According to the last 2.5 ms of measurements, the standard deviation (RMS) of the current from the desired was calculated. According to the results of 200 experiments, the standard deviation of the current generated by the utility model in the range of the desired current change - 10 ... 10A, was no more than 280 mA, which indicates the operability of the proposed digital sigma-delta modulator for controlling power transistors. In all experiments, the standard deviation of the current generated by the well-known digital sigma-delta modulator of the 1st order was not lower than the standard deviation of the current generated by the proposed utility model, and in 77 out of 200 experiments, the standard deviation of the current generated by the known digital sigma-delta modulator of 1st order, was from 2 to 10 times higher than the standard deviation of the digital sigma-delta modulator for controlling power transistors, which indicates the achievement of the claimed technical result.

Claims (1)

A digital sigma-delta modulator for controlling power transistors, including a digital negative adder connected to an integrator digital adder, which is connected to a memory element, whose resolution input is connected to a truth table connected to the two highest bits of the memory element output and the high bit of the digital result negative adder, and the output of the memory element is connected to a digital quantizer, the output of which is connected to the correction unit, the input of which is also connected to a pulse counter , the output of the correction unit is the output of a digital sigma-delta modulator for controlling power transistors, and is also connected to a digital negative adder.

Images