RU1793543C - Tuneable divider of pulse sequence frequency - Google Patents

Abstract

SUMMARY OF THE INVENTION; The controllable pulse repetition rate divider comprises two triggers, a pulse counter, a control input, a reference frequency input, and code inputs connected to the information inputs of the pulse counter. The introduction of an AND-NOT element and two inverters into the controlled divider increases the functional reliability of the device by eliminating the violation of the operation algorithm upon receipt of the control signal at the moment of the operation of the reference frequency pulse. 2 ill.

Description

The invention relates to a pulse technique and can be used as a controlled pulse repetition rate divider.

Known divider pulse repetition frequency No. 993439, class H 03 KZ / 281, comprising a control bus, two inverters, an I element, a comparator, an RC timing driver, and a voltage divider. The known divider in the absence of a control signal generates a sequence of pulses of a certain frequency, and when a control signal (high potential) is applied, it provides a discrete change in the repetition rate of the output pulses. A disadvantage of the known divider is a narrow range of output pulse repetition rates, since upon receipt of a control signal (high potential), the output pulse repetition rate can be no more than 4 times different from a certain frequency generated by a known divider in the absence of a control signal.

Closest to the technical nature of the proposed divider is a controlled divider of the pulse repetition rate by a.s. No. 1211878, class H 03 K 23/40. This divider contains an EXCLUSIVE OR element connected in series, a pulse counter by N, a first T-trigger whose output is connected to the first input of the EXCLUSIVE ALSO OR element, the second input of which is connected to the input bus, AND element, whose first input is connected to the output EXCLUSIVE OR, and the output is to the C-input of the first T-flip-flop, the division factor control bus and the fractional division control bus, and the information inputs of the pulse counter by N are connected to the division coefficient control bus , Parallel to the code pulse counter write enable input to N connected to the output of the AND C-input of the first T-flip-flop - an output bus inverse output borrow pulse counter on N is connected to the inverse input of the second R-T-flip-flop inverse vyel

WITH

V y

03 SL

N

Cj

the stroke of which is connected to the second input of the And element, and the inverse R-input of the first T-trigger is connected to the control bus by a fractional division coefficient. A disadvantage of the known controlled divider is the low functional reliability. The control signal is asynchronous with respect to the pulses of the reference frequency. Therefore, it is equally likely that the fractional coefficient of division of the control signal (low potential) arrives on the control bus 6 at the time when a pulse or a pause between pulses of the reference frequency acts on the input bus 8. However, the normal functioning of a known divider, i.e. the operation algorithm is violated every time a control signal arrives at the moment the reference frequency pulse acts. Moreover, the violation of the operation algorithm can be of a different nature. In one case, due to a premature change in the phase of the pulse at the output of the EXCLUSIVE OR 2 element, the last pulse repetition period of the output pulses decreases relative to the time set by 0.5 Tb, where Ton is the pulse repetition period of the reference frequency on the input bus 8. In another case, due to a decrease in the duration of the output pulse relative to the nominal value, reliable writing of the code to the counter 1 is not provided, as a result, the next output pulse is generated after a random period of time. In the third case, also due to a decrease in the duration of the output pulse relative to the nominal value, it may not be possible to switch to the single state of trigger 5, as a result of which a pulse train with a period of Top will arrive through output element 3 to output bus 7. Thus, a violation of the operating algorithm of the known divider upon receipt of a control signal at the instant of operation of the reference frequency pulse reduces functional reliability.

The purpose of the invention is to increase functional reliability by eliminating the violation of the operating algorithm upon receipt of a control signal at the time of the reference pulse.

This goal is achieved by the fact that in the controllable pulse repetition rate divider comprising two triggers, a pulse counter, a control input, a reference frequency input and code inputs connected to the information inputs of the pulse counter, an NAND element, the first and second inverters are introduced, and the first

the input of the AND gate is connected to the input of the reference frequency of the divider and to the clock input of the pulse counter, the output of which is connected to the clock input of the first trigger and through the first inverter is connected to the clock input of the second trigger, the output of which is connected to the reset input of the pulse counter, with inputs I and To the first trigger, the installation input of which is connected to the output of the AND-NOT element, the second input of which is connected to the recording enable input of the pulse counter and to the output of the first trigger, the control input of the divider is connected to input I and through the second inverter is connected to the input K of the second trigger.

The introduction of an AND-NOT element and two inverters with associated connections into the controlled divider increased functional reliability by eliminating the violation of the operation algorithm upon receipt of the control signal at the instant of operation of the reference frequency pulse. In the proposed divider on the second trigger

5, the moments of arrival and termination of the control signal (high potential) are linked to the pulse front of the reference frequency, i.e. phase locking of the control signal by reference frequency pulses. Thus, the proposed divider eliminates disturbances inherent in the prototype and is associated with the asynchrony of the control signal relative to the pulses of the reference frequency.

Technical solutions known to the applicant and authors do not distinguish the proposed divider from the prototype divider. Therefore, it can be assumed that the proposed divider has significant differences from the known divisors.

In FIG. 1 shows a functional diagram of a divider; in FIG. 2 - time diagrams of his work.

The controlled divider contains an AND-1 element, the first and second inverters 2 and 3, the first and second triggers 4 and 5, the counter

6 pulses, reference frequency input 7, control input 8, code inputs 9 and output 10. Code inputs 9 are connected to information inputs of a pulse counter 6. The first input of the AND-NOT 1 element is connected to the input 7 of the reference frequency of the divider and to the clock input of the counter 6 pulses. The output 5 of the counter 6 pulses is connected to the clock input of the first trigger 4 and through the first inverter 2 is connected to the clock input of the second trigger 5. The output of the second trigger 5 is connected to the reset input of the counter 6 pulses, connected to the inputs I and K of the first

0

5

0

5

0

5

0

5

0

trigger 4, the installation input of which is connected to the output of the AND-NOT element 1. The second input of the AND-NOT element 1 is connected to the write enable input of the counter 6 pulses and to the output of the first trigger 4. The control input 8 of the divider is connected to the input I and through the second the inverter 3 is connected to the input K of the second trigger 5. The output 10 of the divider is connected to the output of the counter 6 pulses.

The controlled divider can be implemented both in the integrated version as a separate microcircuit, and on discrete elements, for example, 1533 series microcircuits (AND-1 element - 1/4 ms 1533LAZ, inverters 2.3-1 / 3 ms 1533 TL2. Triggers 4 5 - ms 1533 TB1, counter 6 - ms 1533 IE7 -t2 / 3 ms 1533ТЛ2).

The output of trigger 4 is an inverse output. The clock input of the pulse counter 6 is subtracting. The output of pulse counter 6 is the reverse transfer output.

In FIG. 2, designations of voltage diagrams are introduced, corresponding to the position numbers of circuit elements (Fig. 1). The reference frequency pulses at the respective time intervals in FIG. 2 are numbered starting at. 1 by K + 1 (K is the number set on the code inputs of the 9 divider).

A controllable pulse rate divider operates as follows.

In the initial state, until a control signal is received, a low voltage level (level O) is applied to the control input 8 of the divider.

In this case, the reference frequency input 7 continuously receives pulses of the reference frequency Fon.

Trigger 4 is set to a single initial state, i.e. level O acts on its inverse output, and trigger 5 - to zero, level O acts on its direct output.

The level O from the inverted output of trigger 4 maintains the I-NO 1 element in the closed state and simultaneously enters the input of information recording from counter 6.

At the code inputs 9 of the divider, the code of the number K, which determines the frequency division coefficient F0n, is constantly set. Counter 6 is reset to zero. In this case, the pulses of the frequency F0n, arriving at the subtracting input of counter 6, freely pass to the reverse transfer output BR of counter 6 and to the output 10 of the divider, i.e. .

At time ti (see Fig. 2), the leading edge of the control signal, i.e. at input 8, a high voltage level begins to operate (level 1). The state of the trigger 5 does not change. At time t2, on the leading edge of the reverse transfer pulse coming from the output of counter 6, trigger 5 switches to the single state, and level 1 is set at its forward output. The lock is removed from input R of counter 6. At time ts, on the trailing edge pulse from the output of counter 6 due to the action of levels

 1 at inputs I and K of trigger 4, it switches to the zero state. At the inverted output of flip-flop 4, a level Г appears, which ensures the recording of the number K from the code inputs 9 of the divider into counter 6.

At time t4, on the leading edge of the 1st pulse of the reference frequency, which is counted by the counter 6. The NAND element 1 switches to the zero state, and trigger 4 is set at the input S to

initial single state. In this case, the O level from the inverted output of the trigger 4 closes the AND-NOT 1 element and transfers the counter 6 from the recording mode to the counting mode of the reference frequency pulses. Gradually, as pulses of frequency Fon arrive at the subtracting input of counter 6, the number K written in it starts to decrease.

When the Kth pulse of the reference frequency arrives at its trailing edge, a number is set in counter 6.

At the next time moment ts (see, Fig. 2), when the counter of the 6th (K + 1) th reference pulse is received at the subtractive input

frequency, at its output and output 10 of the divider, a leading edge begins to form

g- OP

output pulse with a frequency of

where the division ratio of the reference

frequencies

At time ts, the output of trigger 5 still has the level G.

The trailing edge of the output pulse at the output 10 is formed at a time

ts. In this case, the trigger 4 switches to the zero state. Level 1, with its inverse output, allows the number K to be written back to counter 6. Then, at time:, trigger 4 switches again

to a single state, and the whole process described above is repeated in a similar way,

At time ts, the action of the control signal at input 8 ends.

At time tg, when the (K + 1) th pulse of the reference frequency arrives at the subtracting input of the counter 6, the last pulse with the frequency

 where, on the leading edge

which trigger 5 switches to the initial zero state. By level O from its output, counter 6 is again blocked at input R in the zero state.

Further, starting at time tg, pulses with a frequency are generated again at output 10.

Thus, in the absence of a control signal at input 8 of the divider, i.e. at level O, a pulse train with a frequency ..- is formed at the output 10.

When a control signal is input to input 8 in the form of level 1, it is formed at output 10. pulse sequence with

frequency Pout -., where is the frequency division coefficient F0n.

The division coefficient n can be selected due to the code of the number K, which is recorded in the counter 6, which provides the divider with a wide range of changes in the frequency of the output pulses with respect to the frequency FOR.

In the event that it becomes necessary to form a sequence of output pulses with a duty cycle, an additional counting trigger can be connected to the output of the divider (to output 10), at the output of which a specified sequence is generated. The frequency F0n should be increased by a factor of 2.

The proposed technical solution provides increased functional reliability.

In addition, in the proposed divider at the output of trigger 4, which can be used as an additional output of the controlled divider, a pulse train with a frequency of Rout is formed during the duration of the control pulse

. Consequently, the proposed deK. t

a suppressor can be used to form a burst of pulses during the duration of the control pulse, i.e. as a shaper of the pulse train. The advantage of the proposed divider is also the possibility of using it for the frequency manipulation of the frequency Pvyh, because when a control signal is applied, the frequency of the Pout may change from F0n to

0

5

0

5

0

5

0

5

0

5

REAR

tg-rV. the proposed divisor may

1 h t I

be used as a frequency manipulator.

Thus, the proposed divider can be additionally used as a frequency manipulator, as well as a pulse train driver, which expands the functionality of the proposed divider in comparison with the prototype.

The disadvantage of the divider -prototype by A. with. No. 1211878 is its low functional reliability due to various factors. The normal functioning of the prototype, i.e. the operation algorithm is violated every time a control signal arrives at the moment the reference frequency pulse acts. In this case, the leading edge of the low potential control signal, i.e.: a signal drop from 1 to O is formed on bus 6, and a reference frequency pulse acts on bus 8.

For example, in the absence of a control signal and a fractional division coefficient equal to 2.5, there should be:; Fon 1 2,5 2,5 Top

(Thy 2.5 Top)

In this case, in the presence of a control signal of low potential, the division coefficient should be equal to 3 and should be:

s - op 1

hvy V - o about I op

where FBbix is the pulse repetition rate on the bus 7;

Fon is the reference pulse repetition rate of the input pulses on bus 8;

Thy Top - respectively their periods of succession.

However, due to the asynchronous arrival of the control signal on the bus 6 relative to the input pulses of the reference frequency on the bus 8, the specified prototype operation algorithm is violated. Moreover, the violation of the algorithm of work may have a different nature.

In one case, if the leading edge of the control signal arrives at the point in time when trigger 4 is in a single state and before the appearance of the output pulse on bus 7, trigger 4 will be reset to the zero state ahead of time, because it must switch to the zero state (at the counting input) along the trailing edge of the pulse on bus 7 (see Fig. 2 of the prototype description). This will lead to the reverse phase change of the pulses at the output of the EXCLUSIVE OR 2 element prematurely, i.e. the time interval until the occurrence of a loan pulse at the output of counter 1 is reduced by 0.5 Top. In this case, trigger 5 is reset to the zero state and element 3 passes an output pulse to bus 7 ahead of time by 0.5 T0p, i.e. Instead of a period, 5 Top will be Top.

In another case, if the leading edge of the control signal on bus 6, when the trigger 4 is in a single state, arrives at the moment the output pulse acts on bus 7, trigger 4 is reset to zero, and the output of the EXCLUSIVE OR 2 level is O , closing element AND 3. On the bus 7, an output pulse is thus generated, randomly shortened in duration relative to a predetermined nominal value. So the duration of the output pulse on bus 7 may be less than the response time of the logic elements used in the prototype or in an external device. This can lead to unreliable operation of both an external device that receives signals from bus 7 and may not work out too short a signal, as well as the prototype itself, because a short pulse in duration on bus 7 does not provide a reliable record of the number in counter 1. As a result, in counter-1 randomly, since the triggers (bits) of the counter 1 may have different response times, an arbitrary number will be set. That is, on the bus 7, the next output pulse is generated with the period of your TTZ, which does not correspond to the established algorithm of operation

prototype, according to which should be (as described above).

There may also be a case where a shortened output pulse on bus 7 does not provide switching

to the single state of trigger 5. Therefore, at the input of the And 3 element, there will be a high potential allowing the passage of the sequence of pulses of the reference frequency through the And 3 element to the output

bus 7. In this case, the prototype operation algorithm is also violated, as a result of which Thy / ZT0p.

Thus, the described violations of the prototype operation algorithm upon receipt of a control signal at the moment of the action of the reference frequency pulse reduce the functional reliability of the prototype.

In the proposed divider, at the second trigger 5, the moments of arrival and termination of the control signal (high potential) are linked to the pulse front of the reference frequency, i.e. phase locking of the control signal by reference frequency pulses. Thus, the proposed divider eliminates disturbances inherent in the prototype and associated with the asynchrony of the control signal relative to the pulses of the reference frequency.

Claims (1)

SUMMARY OF THE INVENTION A controllable pulse repetition rate divider comprising two triggers, a pulse counter, a control input, a reference frequency input, and code inputs connected to information inputs of a pulse counter, characterized in that, in order to increase reliability, an NAND element is introduced. the first and second inverters, the first input of the AND-NOT element being connected to the input of the reference frequency of the divider and to the clock input of the pulse counter; the output of which is connected to the clock input of the first trigger and through the first inverter is connected to the clock input of the second trigger, the output of which is connected to the reset input of the pulse counter and to the inputs I and K of the first trigger, the installation input of which is connected to the output of the NAND element, the second input of which connected to the recording enable input of the pulse counter and to the output of the first trigger, the control input of the divider is connected to input I and through the second inverter to input K of the second trigger. FCG. i , 1 # / f V V, / / ". 1K K + 1 LTU1J1LL LJ1J1-:: LJ1GJU 1.L; .LLGLLGSh