RU1774353C - Graph solver - Google Patents

Abstract

The invention relates to computer technology and can be used to analyze the connectivity of the vertices of a graph. The aim of the invention is to expand the functionality of the device by listing internally stable subsets of the vertices of the graph. The device comprises a synchronization unit 1, a vertex enumeration unit 2, an internally stable subset of graph vertices determination unit 3, a registration unit 4, an adjacency matrix definition unit 5, an initial installation input 6, a start input 7, and first through third outputs 8-10 of the synchronization unit 1 . Before starting work, the registration block 4 is reset, the vertex enumeration block 2 is reset, and the graph topology information is entered into the adjacency matrix block 5. At the input 7 of the start of the device, a pulse of the level of a logical unit is supplied. In this case, synchronization unit 1 generates a signal sequence at its outputs 8-10, under the control of which information about all possible internally stable subsets of graph vertices is entered into registration unit 4. 4 ill. & fe

Description

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The invention relates to computer technology and can be used to analyze the connectivity of the vertices of a graph.

The purpose of the invention is to expand the functionality of the device by listing internally stable subsets of graph vertices.

In FIG. 1 shows a functional diagram of a device; in FIG. 2 is a timing diagram of a synchronization unit; Fig. 3 is a functional block diagram for determining internally stable subsets of graph vertices; in FIG. 4 is a timing diagram of a synchronization node.

The device comprises a synchronization unit 1, a vertex enumeration unit 2, an internally stable subset of graph vertices determination unit 3, a registration unit 4, an adjacency matrix task unit 5, an initial installation input 6, a start input 7, and first through third outputs 8-10 of the block 1 sync.

The block for determining internally stable subsets of graph vertices contains a synchronization node 11, a node listing node 12, a logical addition node 13, an adjacent vertex determination node 14, a switching node 15, a registration node 16, a bitwise comparison node 17, the input 18 of the start of block 3 connected to the start input of the synchronization unit 11, the first output 19 of the synchronization unit 11 is connected to the installation input to the bit unit of the registration unit 16, the second output 20 of the synchronization unit 11 is connected to the connection input of the first information direction of the node 1 5 switching, the third output 21 of the synchronization node 11 is connected to the clock input of the node listing node 12, the outputs of the Mth digit of the position of the vertex code of which

(B, where B is the number of vertices in

column) is connected to the Mth bit of the second information input of the switching unit 15 and to the Mth bit of the second information input of the logical addition node 13, the Mth bit of the information output of which is connected to the polling input of the Mth vertex of the node 14 for determining adjacent vertices, the output of the sign of belonging to the Kth vertex to the set of adjacent vertices () is connected to the Kth bit of the first information input of the node 17 bitwise comparison and to the Kth bit of the first information input of the switching node 15, the Kth bit of information exit to which is connected to the input of the installation in the K-ro culture of the bit of the registration node 16, the K-th bit of the information output of which is the output 22 of the sign of belonging to the K-th vertex to a subset of block 3 and connected to the K-th polling permission input of the node 14 and The kth bit of the second information input of the bitwise comparison node 17, the output of the equal sign of which is connected to the input of the second information direction of the switching node 15, the input 23 of the presence of the (K, M) -th arc of block 3 is connected to the node input of the same name 14 cm definition nodes, the output of the end sign of the node listing node 12 is the output 24 of the information output flag of unit 3 and is connected to the stop input of the synchronization node 11, the Mth input 25 of the central vertex of the block 3 is connected to the Mth bit of the first information input of the node logical addition 13.

The device operates as follows.

Before starting work, the registration block 4 is reset, the vertex enumeration block 2 is reset, and the graph topology information is entered into the adjacency matrix block 5.

At the input 7 of the start of the device, a pulse of the level of a logical unit is supplied. In this case, the synchronization unit 1 generates at its outputs 8-10 a sequence of signals provided by the time diagram of its operation. Pulses of the logic unit level appear at outputs 10 and 8 of synchronization unit 1. In this case, the registration unit 4 forms the next address for recording information, and the vertex listing unit 2 - the number of the next (in the first measure, first, etc.) vertex (thereby setting the central vertex relative to which the internal stable subset is determined). After a time sufficient to perform the indicated operations, the synchronization unit 1 generates a logic level level pulse at its output 9. At the same time, the unit 3 for determining internally stable subsets of graph vertices (after the time determined by its design) gives out the composition of the vertices of the subset his signal sign of the issuance of information. In this case, the registration unit 4 forms the information received at its input, and the synchronization unit 1 repeats the output of signals provided by the time diagram of its operation. The operation of the device continues in the same way until the next clock pulse of the vertex listing unit 2 produces a signal of the level of a logical unit at the output of the sign of the end of the list. In this case, the synchronization unit 1 is based on the power supply and does not generate a start signal for the unit 3.

Block 3 for determining internally stable subsets of graph vertices works as follows.

Before starting work on inputs 23, specify the graph topology, and on inputs 25, the central vertex of the current internally stable set.

The input 18 start block 3 serves as a pulse level logical unit. In this case, the synchronization unit 11 generates at its outputs 19-21 a sequence of signals provided by the time diagram of its operation. The pulse of the level of the logical unit appears at the output 19 of the synchronization unit 11, while all the bits of the registration unit 16 are set to unity. After a time sufficient to perform the indicated operation, the synchronization unit 11 generates a pulse of a logical unit at its output 20. In this case, its first information input is connected to the output of the switching unit 15, and the node 16 sets its bits to which the signals correspond level of a logical unit at its input (thereby excluding vertices adjacent to the central one from the composition of an internally stable subset). After a sufficient time to complete the indicated operation, the synchronization unit 11 generates a pulse at its output 21. In this case, the node listing node 12 issues the number of the next vertex (the first one) in its output. In this case, the node 14 for determining adjacent vertices gives out signs of belonging to the composition of vertices adjacent to the current one (if its polling is allowed). In this case, the node 17 (if the information received at its information inputs coincided at least in one bit) generates a signal of the level of a logical unit at its output of the sign of equality. In this case, the switching unit 15 connects a second information input to its information output. In this case, the registration unit 16 sets its bits in the panel (if they were not installed earlier), which correspond to unit potentials at its input (thereby, if the vertex with the number formed by the node 12 is adjacent to at least one of the vertices not adjacent to the central one, it is excluded from the internally stable subset). After enough time

to perform these operations, the synchronization unit 11 again generates a pulse at its output 21, and the operation of the device is repeated. After the node 12 lists all the vertices of the graph, it generates a logic level signal at its output of the end of the list indicator, which is also a sign of the output of information from block 3. In this case, the synchronization unit 11 stops generating clock signals and switches to the waiting mode for the next start pulse.

Claims (1)

SUMMARY OF THE INVENTION A device for solving problems on graphs, comprising a synchronization unit, a vertex enumeration unit, and an adjacency matrix task unit, wherein the start input of the device is connected to the start input of the synchronization unit, the first output of which is connected to the clock input of the vertex enumeration unit, characterized in that, In order to expand the functionality of the device by listing internally stable subsets of graph vertices, the unit for determining internally stable subsets of graph vertices and the block p recording is the, in a set input of which is input to the initial installation of the device, and the Mth bit of the positional code numbers vertices block listing perks (. where B is the number of vertices in the graph) is connected to the Mth input of the task of the central vertex of the unit for determining internally stable subsets of the vertices of the graph, the output of the sign of belonging to the K and vertices of the subset of which (B) is connected to the Kth bit of the information input of the registration block, the output of the value (K, M) of the element of the adjacency matrix specifying block is connected to the input of the sign of the presence of the (K, M) th arc of the block for determining internally stable subsets of graph vertices, the output of the sign of the end of the list of vertex listing block is connected to the stop input of the synchronization unit, the second output of the synchronization unit is connected to the start input of the unit for determining internally stable subsets of graph vertices, the output of the sign of information output of which is connected to the input of the sign of recording and registration and to the input of the restart of the synchronization unit, the third output of which is connected to the input of the sign of changing the address of the registration unit.