OA1466A - Arrangement for the analysis of printed characters. - Google Patents

Arrangement for the analysis of printed characters. Download PDF


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OA1466A OA52006A OA52006A OA1466A OA 1466 A OA1466 A OA 1466A OA 52006 A OA52006 A OA 52006A OA 52006 A OA52006 A OA 52006A OA 1466 A OA1466 A OA 1466A
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OA01466A (en
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Bull Sa Machines
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Priority to FR834008A priority Critical patent/FR1271150A/en
Priority to FR854343A priority patent/FR79378E/en
Application filed by Bull Sa Machines filed Critical Bull Sa Machines
Publication of OA01466A publication Critical patent/OA01466A/en
Publication of OA1466A publication Critical patent/OA1466A/en



    • G06K9/00Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
    • G06K9/18Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints using printed characters having additional code marks or containing code marks, e.g. the character being composed of individual strokes of different shape, each representing a different code value
    • G06K9/183Characters composed of bars, e.g. CMC-7


915,344. Automatic character-reading. COMPAGNIE DES MACHINES BULL. April 19, 1961 [July 26, 1960; March 2, 1961], No. 14203/61. Class 106 (1). Characters consisting of a series of vertical bars, Fig. 1, arranged so that their leading edges are separated by long or short intervals A-F forming a code identifying the character, are scanned by a magnetic sensing head to produce pulses at the leading edges of the bars, means being provided to detect long and short intervals and to register binary signals corresponding to the successive intervals of a character. In the form of Figs. 2a, and 2b the interval duration is measured by counting pulses from a generator 24. Pulse shaper 22 produces a sharp pulse for the leading edge of each bar which is applied to each stage of counter 23 to stop the counting. The counter is of the parallel type, the incoming pulses being applied to each stage. The value standing in the counter when it is reset by the following pulse indicates the length of the interval. The stages of the counter are connected to gates in a matrix 25a the outputs of which indicate the range within which the interval count lies. These outputs are stored in five elements 25c the outputs of which are gated together in 27 to produce markings on the " long " interval lead J. The long signal enters a "1." in the first stage F of shift register 28. The lead K produces a pulse for each interval, long or short, and these pulses are applied to shift the pattern through the register. When seven bar signals are counted in counter 31 the contents of register 28 are read out into buffer store 30. There should be two long intervals. An elementary counter which receives the output J of unit 27 gives an error signal if the number of long intervals is greater or less than two. The space between characters, which is much greater than the long interval is detected and used to reset the apparatus. In the form of Figs. 6a and 6b the detection of pulse lengths is by comparison with standard pulse lengths derived from time base circuits 70, 73, 76 which emit ramp voltages for application to threshold circuits 71, 74, 77. A single time-base circuit may be used. The standard pulse lengths are applied to the set input of binary stages 72, 76, 78. The time base circuits are triggered by the signal from the scanner delayed at terminal t2 of circuit 26 and the stages 72, 75, 78 receive the same pulses on their reset inputs. Whether or not these stages become set depends upon whether the scanner signal is longer or shorter than the standard pulses. When stage 72 is set an interval is indicated which is long enough to be the gap between characters. The delayed bar signals at terminal t2 are applied to each stage of the shift register to shift the contents to the right. The first bit entered on lead 86b is always a " 1 " since the inter-character gap also produces an output on the " long interval " lead 86a. Following long intervals also enter " 1's." When the initial " 1 " reaches the end stage D1<SP>1</SP> a signal is produced on lead 92 indicating that all seven bars have been scanned. This is used to open gates 29 and allow the contents of register 28 to enter the store 30. The number of long pulses is counted at 43 and the output used to enable gate 41. Another input to this gate is from error store 79, which is set if a too-short interval is detected, to prevent read-out of the register 28. Specification 910,228 is referred to.





International Classification: B 41 - G 06 No. 01466

REQUESTED DECEMBER 31, 1964 at 6:36 pm in ΙΌ.Α. Mr. P. I. (P.V. No. 52.006) by the Compagnie des Machines Bull, resident in France. ISSUED JULY 21, 1969, published in Official Bulletin No. 2 of 1969. PRIORITY: Patent application filed in France under No. 834,008 on July 26, 1960 in the name of the plaintiff.

Arrangement for the analysis of printed characters.

The present invention relates to arrangements by means of which documents bearing visually identifiable characters can be analyzed by a machine. More particularly, this invention is amenable to an arrangement for automatically analyzing visually identifiable information elements. Especially, the arrangement according to the invention is suitable for the analysis of characters composed of vertical debars such as those described in French Patent No. 1,225,428 filed May 26, 1959. According to an example given in this patent, the The record carrier to be analyzed may be a bank check and figures are printed thereon using a magnetisable ink.

In the type of character described in the above-mentioned patent, the width of the characters is uniform, being given that each comprises the same number of debars, the same number of short intervals and the same number of long intervals. The distance between the anterior edges of two neighboring bars is called interval. If we arbitrarily assign the value 1 to a long interval and the value 0 to allinterval short, it is easy to distinguish the different characters, for the purpose of mechanical analysis by means of a combination coding system. two out of 5 positions "provides enough combinations to distinguish the digits from 0 to 9. However, since one needs in addition to distinguish between the framing symbols, or the beginning signs and the word defin, one has adopted a code called" 2 out of 6 "that provides 15 coded combinations in all, that is, special symbols in addition to numbers. That is why the number of bars chosen is 7. If we reserve a particular position for an intervallelong in any of the framing symbols, this position can be used to distinguish them from any digit from 0 to 9.

This codified mode of representation is extremely advantageous in that it accommodates irregularities in printed characters. It allows the use of a relatively simple analysis system as well as equally simple error control algorithms. Given that it is only a determined edge of a bar that has a significance for mechanized reading, irregularities from different thicknesses of bars barely affect the intervals between reading pulses, as long as they do not exceed a certain tolerance. In the case where several neighboring bars are thick enough to confound, the character would be read as having, for example, one bar less than the number of normal bars. A simple pulse counter can be used for this control. The "character" entity can also be easily recognized because the analysis devices can distinguish a "very long" bar interval, in addition to the "short" and "long" intervals already mentioned. This very long interval is that which separates two successive characters. It corresponds normally to a spacing between two consecutive characters and is always much larger than a long interval that is part of a character.

A first object of the invention is to provide a simple construction and implementation analysis arrangement, capable of performing serial-time conversion in parallel-space of the distinctive parameters attributed to the different characters formed according to the coding system defined above.

Another object of the invention is to provide a positive character analysis analysis of the genredefinite above, which is very simple to modify or adjust to adapt it to a codification system modified, for example in the sense the reduction or extension of the number of characters to be distinguished.

Another object of the invention is to provide a character analysis arrangement as defined above, adapted to detect printed defects and malformations and to prevent the transmission of erroneous output signals.

Another object of the invention is to provide an analysis arrangement capable of converting a stream of read impulses differently tuned in time according to a determined code into a group of signals available in parallel over a number of paths. output according to said code.

According to a first aspect of the invention, the above goals are achieved by implementing a time interval value discrimination process, a process of comparing these values with predetermined limits and a process. serial deconversion in parallel controlled by the results of this comparison.

Accordingly, the inventive analysis arrangement, for analyzing vertically spaced bar characters according to a combinatorial code, is composed of a pulse counter which is reset at each bar reading signal, a logic comparator discriminating the values counted the dependence of limit values in the preconsulted relation with the short, long, and very long intervals, and finally a shift register which receives, on each signal of reading of a bar, a pulse of deca-lage, and an introduction pulse of one, upon detection of a long interval by the comparator. Other particularities as well as the implementation of the invention will appear in the description which is given by way of example, in conjunction with the appended drawings, which show:

Figure 1, some of the characters to be analyzed;

Figures 2a and 2b, a block diagram (functional) of the analysis arrangement according to the invention;

FIG. 3, a block diagram of the comparison matricelogy;

FIG. 4 is a circuit diagram of circuits for controlling the shift register;

Figure 5 is a block diagram of a non-error detection device.

The registration holder to be analyzed may be a bank check as described in the aforementioned French patent. Figure 1 shows some of the numbers from 0 to 9 and on the far right a number framing dessymboles. The characters are aligned on the same horizontal line and are formed of vertical bars or portions of bars. It will be noted that even the very short bars of chif-fre 1, for example, are capable of being read correctly by the reading device. magnetic.

If we refer to the enlarged representation of chif-fre 2, we see that it includes, like all the others, seven bars and six intervals between bars. As we assume that the recording carrier is moved from right to left during playback, the front edges of the bars are left on the drawing. Since only the reading pulse resulting from the reading of an anterior edge is used, the information carrying parameters are the intervals between these consecutive leading edges. In each character, on the six intervals, there are four short and two long ones. As mentioned above, if a short interval is 0 and if a long interval is 1, then the following coding table can be drawn up: AB c DEF 0 0 0 0 1 1 0 1 1 0 0 0 1 0 2 0 1 1 0 0 0 3 0 1 0 0 1 0 4 1 0 0 1 0 0 5 1 0 1 0 0 0 6 0 0 1 0 1 0 7 1 1 0 0 0 0 8 0 0 1 1 0 0 9 0 1 0 1 0 0 X 0 0 0 0 1 1 Y 0 0 1 0 0 1 Z 1 1 0 1 0 0 0 t

The letters A to F correspond to the significant intervals of the characters and the 0s and 1s indicate the respective positions of the short intervals and the long intervals. Thus according to the table above, in the number 2, the intervals B and C are long.

In practice, for the widths of a long interval and a short interval, the ratio 1.67 to 1 has been adopted, which is sufficient for good discrimination and saves space. The smallest spacings between digits each constitute a "very long" interval. The ratio between a very long interval and a long interval is at least 1.45 to 1. In the table above, the letters X, Y and Z relate to the codified com-binations assigned to the zone symbols. symbol X which is shown in Figure 1 to the right.

Although characters of the kind shown in FIG. 1 can be read by photoelectric or optical reading means, it will be assumed in the following that the rods constituting the characters are bars or portions of bars printed with a magnetizable ink. In this case, after magnetization of the magnetic material by any appropriate means, each bar can be read by a magnetic transducer, whose gap extends over the height of the character, and perpendicular to the direction of advance of the line of characters.

In FIG. 2a, the character reading transducer is shown diagrammatically at 21. It can be assumed that it is a magnetic read head that provides a positive direction pulse, then a negative direction pulse when a front edge then a rear edge of a magnetic bar passes successively under the gap of the read head. Reading signals are transmitted to a device 22 generically called "pulse trainer". Cedispositif is composed of differentiating members, rectifiers and limiters adapted to provide the output of the device a pulse of polarity, amplitude and duration determined for any positive pulse received at the input. Optionally, a pulse generator 24 exerts an influence on the dis-positive former 22 so that any pulse at the output thereof has a fixed duration and a predetermined time relationship with a timing pulse supplied by the generator. 24. These rhythm pulses are, for example, a duration of one microsecond and a repetition rate of 200,000 per second.

The device for discriminating time intervals between successive read pulses is shown here as a pulse counter 23. This counter is of the parallel type. It is composed of a number of interconnected bistable stages, which can be of any known type appropriate. Each floor has a "1" input and an "0" input. The inputs "1" simultaneously receive the pulse pulses constantly transmitted at the output of the generator 24. The "0" inputs of the counter receive in parallel each read pulse coming from the output of the former 22 by the drivers 61a, 615. The counter must provide quickly the quantized value of the elapsed time since the last received read signal.

In relation to each of the short, long and very long intervals, three counted pulse values I were selected which are 25, 41 and 60, respectively, in accordance with the interval ratios indicated previously. As the analysis system must allow great flexibility of use, these intervals may vary with relatively wide tolerances. However, for character correction checks, these tolerances must also be determined accurately. Thus the number of pulses during a short interval is between 20 and 30 inclusive. The NZ number of pulses during a long interval is between 36 and 46 inclusive. A very long interval corresponds to at least 60 pulses counted.

The counter 23 comprises six stages respectively assigned to the binary values 1 to 32. Its capacity is therefore in principle 63.

It should be understood that this capacity has been chosen arbitrarily according to several factors, such as the speed of translation of the recording wearer and the repetition frequency of the counting pulses (or rhythm pulses). Nothing would preclude the choice of counted values reduced by half, which would make it possible to suppress the value stage 32 of the meter. Likewise, a counter of the parallel type is by no means indispensable. In the case of a slower operating speed, one could use a series type meter, or cascade, which has the disadvantage of requiring a longer time for the cascading transmission of the binary reports. In this case, the timing pulses to be counted would only be applied to the "1" input of stage 1.

In any case, we know that we have at least one significant value output in each stage. For example, a high voltage at this output can mean a "true" value or 1, and a lower voltage can mean a value. "False" or 0.

The gap comparator is shown here as being composed of three elements: a logic matrix 25a, a series of amplifiers 255, and a comparison memory 25c. The logic matrix is shown in greater detail in Figure 3. It consists of five coincident circuits or ET circuits 32 to 36. Each circuit-ET is composed of crystal diodes and resis-tances. They each have an output and several inputs which are connected to the outputs of the bistable stages of the counter as shown by the drawing in the case where the comparison limits are predefined.

The AND-circuit 32 outputs a significant voltage when the contents of the counter reach 20. In effect, its inputs are connected to the value outputs 16 and 4 of the counter. Similarly, the AND circuits 33, 34, 35 and 36 provide a significant output when the counter counts reach the respective values of 31, 36, 47 and 60.

The five output amplifiers 255 may be simple non-inverting amplifiers or pulse regenerators. From a logical point of view, they are not indispensable. They can be useful for adjusting voltage levels. In any case, they transmit an impulse of appropriate duration and amplitude whenever a corresponding limit has been crossed by the contents of the meter. It is clear that if a long gap has been detected between two bars, the amps connected to AND circuits 32,33 and 34 will have each provided a pulse.

The memory 25c is composed of five bi-stable elements, each with an "0" input and an "1" input. Their role is to store the information formed by the output signals of the comparator until the next reset of the counter. Each bistable element has a true output and a complementary output. Thus, the left element has an output I and an output I. A significant voltage is available at output I when the element has been reset. Significant is available at the output when the element has received a pulse on the input 1, i.e. when the limit 20 has been crossed by the meter content.

There is provided a delay device 26 (Fig. 2a) which reads the read signals formed by the dis-positive former 22 and which has three outputs G1, G2 and H. Any known delay elements can be used here. The output H is connected by the driver 62 to the reset inputs of the bi-stable elements of the comparison memory 25c. The signal at the output H is delayed with respect to the playback pulse and may or may not be inverted depending on the bistable element structure of the memory 25c. In any case, its role is to bring them back to state 0.

The control device 27 comprises two sections, each comprising one or more logic circuits. It is connected on the one hand to the outputs of the elements of the comparison memory and on the other hand to the output G1 of the delay device 26 by the symbolic channels 63a and 635. Its logic circuits are shown in detail in FIG. 4. There are three circuits-AND 37, 38 and 40 and an OR circuit 39. The signal G1 from the leads 63a, 635, and applied to an input of each of the AND-circuits, is simply a delayed read signal to correspond to the necessary transmission time between the The inputs of the other inputs with the outputs of the elements of the comparison memory are such that the circuit 34 supplies the output K with a shift signalwhen the contents of the counter are passed through 20 and paspar 31 (L_II = short interval) or by 36 and not par47 (III.IV = long interval). The circuit 40 provides an input signal of 1 when the counter reading is passed through 36 and not by 47 during a bar reading signal.

The shift register 28 is composed of six interconnected ladder stages identified from A to F in correspondence with the intervals of a character. The input of 1 of the stage F is connected by the conductor 64 to the output J of the device 27. The offset inputs of all the stages are connected by the conductor 65 to the output K of the device 27. It is known that any pulse applied to the offset inputs has the effect of progressing one step to the right any configuration of 1 and 0 introduced or found in the shift register, while a pulse applied to the input 1 of the F stage introduced a new 1. Each floor is provided with an outlet from which the information contained in the shift register can be extracted at the desired time. The outputs of stages A to E are connected to the inputs of five ET circuits such as 29, the outputs of which are connected to a buffer memory 30. This is composed of five bankable elements A to E, simply having a static memory function.

The transfer of the information contained in the shift register 28 to the buffer store 30 is controlled in part by the bar counter 31 (Fig. 26) .This is shown as being of the parallel type, composed of three interconnected bistable stages and assigned to binary values 1, 2 and 4. Its capacity corresponds to the number of bars of a character. Since the counting rate is much slower than that of the counter 23, it could be of the cascade type, that is to say, of the series type. The binary output bits are connected to three inputs of an AND circuit 41. The fourth input of the AND circuit 41 receives by the driver 66 each delayed read signal G2. One of these pulses may appear at the output of 41 only when the counter 31 has counted the seven bars of a character. This pulse is then transmitted to an input of each of the AND-circuits such as 29.

The reset inputs of the bistable stages of the counter 31 are connected by the conductor 67 to the true output V of the comparison memory. This provides a reset pulse when the comparator has detected a very long interval. that is, when the contents of the counter 23 have reached and exceeded 60.

A conductor 68 connects other inputs of the circuits ET 29 to the complementary output terminal V of the comparison memory 25c. This output terminal provides a permit voltage as long as the comparator has not detected a very long interval. Finally, an inverter or complementor device 42relies other inputs of the AND circuits 29 to the true output of the F stage of the shift register 28. This arrangement is such that an authorization voltage is supplied to these latter inputs only if the stage F has remained at state 0, when seven bars of one character have been eluted. The presence of a 1 in this floor at this time would mean that the character being read is a zone symbol (see code table). However, the representation of such a symbol must not be transmitted to the buffer store. To summarize, it can be said that the configuration of 1 and 0 contained in the shift register is only transferred to the buffer store during the reading of the buffer. the seventh and last bar of a character, before the detection of a very long interval and provided that this configuration corresponds to one of the digits from 0 to 9.

It will be observed that if the stage F of the shift register has a complementary output, it could be connected directly to the left inputs of the circuits 29, the inverter device or complement-42 can then be deleted. By way of example, if it is assumed that the time required for the state of the comparison memory 25c to have stabilized is a pulse period or a cycle of the generator 24, ie 5 microseconds, the signal G1 at the exit of 26 may be delayed by an equivalent time. The signal G2 may be delayed, compared with the signal G1 of the duration of the pulse, that is 1 or 2 microseconds. The signal H will have to be overwritten with respect to the signal G2 by 1 or 2 microseconds so that the compare memory is reset after the transfer of the shift register 28 to the buffer register 30.

Figure 5 shows a device whose role is to check that any character read includes two long intervals. The input 1 of a bistable element 43 is connected to the output J of the control device27. The output 0 of the bistable element 43 is connected to an input of the AND circuit 44. The other input thereof is connected to the output of the AND circuit 41 (FIG 26). binary counter.

Its output 0 will provide an authorization voltage if it has been reset to zero by two successive pulses each indicative of a long interval. The pro-41 pulse will then be transmitted by the AND-circuit 44 to a non-error detecting device. In the case where the number of long intervals detected in a character would be odd, ie 1 or 3, it is clear that the output 0 of the rocker 43 would not provide the voltage of authorization and would prevent the non-error pulse from being transmitted by 44.

Since the structure of the bistable counting and storage elements may vary depending on the application, it may be necessary to apply certain additional sync signals to them. It will not be difficult for one skilled in the art to apply such signals, which may be derived from the generator 24, to appropriate locations.

It is possible to briefly summarize the operation of the analysis arrangement in relation to reading a number, for example the number 2 shown in FIG. It is assumed that the bars or bar portions of the digit have been properly magnetized before the digit 2 passes under the read head when the recording carrier moves. It is also assumed that the bar counter 31 and the magazine 30 have been reset.

The first read signal applied to the inputs 0 of the counter 23 has the effect of resetting all the stages of the counter. It should be noted that with certain counter types, the read signal can be simultaneously present with a pulse from the generator 24. In other types of counters, it is often necessary for the reset pulse to be applied to the inputs 0 is interpolated in time between two counting pulses applied to the inputs 1.

The content of the counter 23 progresses at each counting pulse received. As soon as it reaches 20, the logic circuit 32 (FIG 3) becomes on and a pulse is transmitted to the input 1 of the memory element Ml 25c. The latter then remains in the state 1. When the second bar of the character is read at the end of the interval A, the resulting read signal arriving by the driver 616 resets the counter 23. If the magnetic bars are correct, its content was at this moment of 25. When the delayed signal G1 arrives by 636 on the inputs of the control device 27 (Fig. 26, 4) only the circuit-ET 37 is passed through its two inputs connected to the outputs I and They receive an authorization voltage. Thus the output K provides a pulse to the offset inputs of the shift register 28, as a result of detecting a short interval.

If, theoretically, the shift register has not been in state 1 at this time, it does not really matter whether some stages contain a 1, because in any case if any configuration of 1 and 0 is found there, will normally be shifted six floors before the next transfer. This is why the systematic reset of the shift register is not | necessary. The delayed signal G1 will have the effect of

Claims (10)

  1. [01466] to produce a 1 in the bar counter 31, and after one instant, the signal H resets the stage Ml of the comparison memory. The contents of the counter 23 have begun to progress again since the beginning of the interval B. This is a long interval. During this progression, some of the logic circuits of the comparator will become passers-by. These are the AND circuits 32, 33 and 34 (FIG 3) detecting the values 20, 31 and 36 respectively. The elements Ml, M2, M3 pass successively to the state 1. It may be supposed that at the end of the interval B, when reading the left edge of the third bar of the number 2, the contents of the counter 23 were at the same time of 42, correct average value. At this time, in the controller 27, the AND circuits 38 and 40 are on and the two outputs K and J transmit a pulse resulting from the delayed read signal G1, on one side to the offset inputs, and from -part part of the input 1 of the F stage of the shift register. Some types of registers accommodate the simultaneous application of these pulses. With other types, it may be necessary to delay pulses from output K that cause the information to be shifted. It can be seen that the detection of a long interval results in the introduction of a 1 in the F-stage and in the shift of a step towards the right of the previously stored information. The interval detection, offset, and introduction processes of 1 will continue analogously if the character is properly printed. When the last bar of the digit 2 is read, the outputs of the stages B and C of the offset register show the presence of a 1, the outputs of the other stages showing 0. It is this configuration of 1 and 0. , characterizing the number 2 which is transferred to the buffer store 30 as previously indicated. The defects that can occur in printed characters are of two kinds. For example, a magnetic material bar may be so thick that it merges with a neighboring bar. The reading device sees these two bars practically as one bar. The bar counter 31 will only reach the count of 6 at the end of the digit analysis and will prohibit the transfer of the coded combination to the buffer store. This kind of defect will also probably result in the detection of a very long interval in the course of the defective character. It is the same in case a bar is missing altogether in a character. Not only the transfer to the buffer store will be prevented, but the logic circuit 41 will remain blocking and the non-error signal can not be transmitted by the logic circuit 44. It could have been content with three limits of compa-reason corresponding for example to minimum widths affected in principle at short, long, and very long intervals respectively. The comparator would only have three logic circuits loaded to detect, for example, the counted values 24, 40 and 60. It is obvious that one could not control the correction of characters with as much rigor and precision as one can do by using five comparison limits. With the arrangement described, if one wants to perfect the verification of the interval values, one can add some logic circuits responsible for the detection of intakes. incorrect times. For example, by associating the inputs of an AND circuit with the outputs II of M2 and III of M3 (FIG 2b), it is possible to detect anyinterrupted interval between the upper limit of a shortinterval (31) and the limit lower than an intervallelong (35). By associating the inputs of another circuit-AND with the outputs IV of M4 and V of M5, it is possible to detect any erroneous interval between the upper limit of a long interval (47) and the lower limit of a very long interval. (59). With the circuit arrangement described so far, the comparison limits are predetermined and their choice has determined the connections of the compare matrix. One of the advantageous aspects of the invention is that the arrangement can be easily adapted to the use of comparison limits that can be modified in accordance with the kind of characters that are to be analyzed. In this case, the circuitry of Figure 3 should be modified as follows. The five circuits AND 32 to 36 would be replaced by five OR circuits with 6 inputs each, each circuit-OR being assigned to a comparison limit. The inputs of each OR-circuit receive the outputs of six cir-cuits-AND with two inputs each. The outputs of the bistable elements of the counter 23 separately supply an input of each of the AND circuits in each of the five groups thus formed. In each group of these six AND-circuits, the other input is connected to the medial contact of an inverter at one pole and two positions. By the prior positioning of the inverters associated with each group, some of the AND-circuits can be inhibited, the others being selected by an authorization voltage in correspondence with the binary components of the limit chosen for this group. Thus the arrangement according to the invention can analyze characters of different types either by the width, or by the number or the proportions of the intervals, and this by means of the prior positioning of the manual inverter reversers as mentioned above. It goes without saying that it is simply as an example that we have spoken in the foregoing of signi-fictive voltage of binary values. Since the bistable counting and storage elements can come out of the technology of vacuum tubes, semiconductors or transistors, or even satu-rable magnetic cores, all that has been said when speaking of voltages can be transposed into currents of current or demagnetization states, according to the structure of the elements employed. SUMMARY An analysis arrangement for analyzing on a machine visually identifiable characters, such as those consisting of vertical bars whose spacing is subject to a "n on N" combination code as described in French Patent No. 1,225,428. . For example, the check-holder, being a bank check, being moved in front of a readout transducer to generate an effected bar read read signal, the arrangement is intended to operate the serial-to-parallel conversion of the encoded signature combination representing each character before the transmission to the organs of use. The arrangement is further characterized by the following features: 1 ° A binary pulse counter receives constant pulses from a generator and [01466] 6 also receives the series of read signals, each of which resetting.
  2. 2 ° The (Nn) short intervals, the n long intervals of a character and the very long interval between characters each having a quantified mean value, the numerical binary capacity of the counter is at least equal to the minimum quantified value of a very large interval. long.
  3. 3 "When the contents of the counter pass through the limit values assigned to the short, long or very long intervals, a logical comparator provides a signal indicative of this passage.
  4. 4 ° The comparator's memory section temporarily stores in separate memory elements the fact that the comparator has detected a short, long or very long inter-valle between two successive read signals.
  5. 5. A logic circuit control device controlled by the comparison memory serves to control the transmission of a control signal from a read signal to a shift register.
  6. 6. The shift register is composed of a number N of interconnected bistable stages, with offset inputs and an input of 1.
  7. 7 ° The control device applies to the shift register an offset pulse when the comparator has detected a short interval or intervallelong, and an insertion pulse of 1 only when the comparator has detected an intervallelong.
  8. 8 ° A bar counter receives the read signals and has a binary digital capacity equivalent to the number N + 1.
  9. 9 ° Logic circuits are inserted between the outputs of the shift register and a buffer store. They are controlled both by the bar counter and by the comparison memory and allow the transfer of the configuration of 1 and 0 to the buffer register when the bar counter has counted N + 1 bars.
  10. 10. In order to admit rather wide tolerances, well defined in the spacing of the reading signals, the comparator logic circuits are arranged to monitor a lower limit and an upper limit for each of the short and long intervals in a character. Company known as: COMPAGNIE DES MACHINES BULLPar power of attorney: Robert Pucheu
OA52006A 1960-07-26 1964-12-31 Arrangement of analysis of printed characters. OA01466A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR834008A FR1271150A (en) 1960-07-26 1960-07-26 Printed character analysis arrangement
FR854343A FR79378E (en) 1960-07-26 1961-03-02 Arrangement for analyzing printed characters

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US (1) US3309667A (en)
BE (1) BE603171A (en)
DE (1) DE1177384B (en)
FR (1) FR79378E (en)
GB (1) GB915344A (en)
NL (2) NL263982A (en)
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US3278900A (en) * 1963-04-01 1966-10-11 Ibm Character recognition system employing pulse time interval measurement
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BE603171A (en) 1961-08-16
NL127547C (en)
US3309667A (en) 1967-03-14
NL263982A (en)
FR79378E (en) 1962-11-23
GB915344A (en) 1963-01-09
DE1177384B (en) 1964-09-03
OA01466A (en) 1969-07-21
BE603171A1 (en)

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