NO20023986L - Fremgangsmåte og arrangement for data og klokke gjenvinning i et bifase-kodet datasignal - Google Patents

Fremgangsmåte og arrangement for data og klokke gjenvinning i et bifase-kodet datasignal

Info

Publication number
NO20023986L
NO20023986L NO20023986A NO20023986A NO20023986L NO 20023986 L NO20023986 L NO 20023986L NO 20023986 A NO20023986 A NO 20023986A NO 20023986 A NO20023986 A NO 20023986A NO 20023986 L NO20023986 L NO 20023986L
Authority
NO
Norway
Prior art keywords
data signal
data
clock recovery
biphasic
arrangement
Prior art date
Application number
NO20023986A
Other languages
English (en)
Other versions
NO20023986D0 (no
Inventor
Peter Schmidt
Original Assignee
Rohde & Schwarz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohde & Schwarz filed Critical Rohde & Schwarz
Publication of NO20023986D0 publication Critical patent/NO20023986D0/no
Publication of NO20023986L publication Critical patent/NO20023986L/no

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
NO20023986A 2000-02-21 2002-08-21 Fremgangsmåte og arrangement for data og klokke gjenvinning i et bifase-kodet datasignal NO20023986L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10007783A DE10007783A1 (de) 2000-02-21 2000-02-21 Verfahren und Anordnung zur Daten- und Taktrückgewinnung bei einem biphase-codierten Datensignal
PCT/EP2001/000437 WO2001063865A1 (de) 2000-02-21 2001-01-16 Verfahren und anordnung zur daten- und taktrückgewinnung bei einem biphase-codierten datensignal

Publications (2)

Publication Number Publication Date
NO20023986D0 NO20023986D0 (no) 2002-08-21
NO20023986L true NO20023986L (no) 2002-08-21

Family

ID=7631666

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20023986A NO20023986L (no) 2000-02-21 2002-08-21 Fremgangsmåte og arrangement for data og klokke gjenvinning i et bifase-kodet datasignal

Country Status (11)

Country Link
US (1) US7136446B2 (no)
EP (1) EP1258118B1 (no)
JP (1) JP2003524970A (no)
CN (1) CN1167233C (no)
AT (1) ATE265777T1 (no)
AU (2) AU2001225168B2 (no)
DE (2) DE10007783A1 (no)
DK (1) DK1258118T3 (no)
ES (1) ES2218368T3 (no)
NO (1) NO20023986L (no)
WO (1) WO2001063865A1 (no)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030169742A1 (en) * 2002-03-06 2003-09-11 Twomey John M. Communicating voice payloads between disparate processors
US8023594B1 (en) 2008-07-11 2011-09-20 Integrated Device Technology, Inc. Asynchronous biphase mark signal receivers and methods of operating same
CN111107024B (zh) * 2018-10-25 2022-01-28 航天科工惯性技术有限公司 时间与频率混合编码的防错解码方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4251831A (en) * 1979-10-26 1981-02-17 Kamath Bantval Y Filter and system incorporating the filter for processing discrete samples of composite signals
JPS6037857A (ja) * 1983-08-10 1985-02-27 Nec Corp Ｆｍ伝送方式
JP2613256B2 (ja) * 1988-05-25 1997-05-21 株式会社日立製作所 ディジタル復調装置
US4912730A (en) * 1988-10-03 1990-03-27 Harris Corporation High speed reception of encoded data utilizing dual phase resynchronizing clock recovery
US4992790A (en) * 1989-09-19 1991-02-12 Schlumberger Technology Corporation Digital phase-locked loop biphase demodulating method and apparatus
GB8924202D0 (en) 1989-10-27 1989-12-13 Ncr Co Digital phase lock loop decoder
DE4408963A1 (de) 1994-03-16 1995-09-21 Inst Rundfunktechnik Gmbh Verfahren zum Verarbeiten eines seriellen, digitalen Datensignals
KR970002949B1 (ko) * 1994-05-25 1997-03-13 삼성전자 주식회사 디지탈 통신시스템의 클럭발생방법 및 그 회로
DE4444601C1 (de) * 1994-12-14 1996-07-11 Sgs Thomson Microelectronics Verfahren und Vorrichtung zur empfängerseitigen RDS-Phasensynchronisation
SG52859A1 (en) * 1995-11-13 1998-09-28 Texas Instruments Inc Method and apparatus for decoding noisy intermittent data such as manchester encoded data or the like
US5953386A (en) * 1996-06-20 1999-09-14 Lsi Logic Corporation High speed clock recovery circuit using complimentary dividers
DE69724631D1 (de) * 1997-12-04 2003-10-09 St Microelectronics Srl Dekodierung eines biphasen modulierten Bitstroms und selbstsynchronisierender Frequenzteiler mit nicht-ganzzahligen Verhältnis

Also Published As

Publication number Publication date
DK1258118T3 (da) 2004-07-26
CN1167233C (zh) 2004-09-15
DE50102132D1 (de) 2004-06-03
US20030012323A1 (en) 2003-01-16
JP2003524970A (ja) 2003-08-19
CN1395782A (zh) 2003-02-05
AU2001225168B2 (en) 2004-03-25
EP1258118B1 (de) 2004-04-28
NO20023986D0 (no) 2002-08-21
ES2218368T3 (es) 2004-11-16
DE10007783A1 (de) 2001-08-23
US7136446B2 (en) 2006-11-14
AU2516801A (en) 2001-09-03
WO2001063865A1 (de) 2001-08-30
EP1258118A1 (de) 2002-11-20
ATE265777T1 (de) 2004-05-15

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Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application