NL2010635C2 - Method of manufacturing semiconductor device and semiconductor device. - Google Patents
Method of manufacturing semiconductor device and semiconductor device. Download PDFInfo
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- NL2010635C2 NL2010635C2 NL2010635A NL2010635A NL2010635C2 NL 2010635 C2 NL2010635 C2 NL 2010635C2 NL 2010635 A NL2010635 A NL 2010635A NL 2010635 A NL2010635 A NL 2010635A NL 2010635 C2 NL2010635 C2 NL 2010635C2
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- Prior art keywords
- semiconductor device
- semiconductor
- glass
- manufacturing
- layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 499
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 182
- 239000011521 glass Substances 0.000 claims abstract description 452
- 239000000203 mixture Substances 0.000 claims abstract description 194
- 239000000463 material Substances 0.000 claims abstract description 80
- 239000002994 raw material Substances 0.000 claims abstract description 60
- 229910011255 B2O3 Inorganic materials 0.000 claims abstract description 25
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052745 lead Inorganic materials 0.000 claims abstract description 17
- 229910052744 lithium Inorganic materials 0.000 claims abstract description 17
- 229910052787 antimony Inorganic materials 0.000 claims abstract description 16
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 16
- 229910052708 sodium Inorganic materials 0.000 claims abstract description 16
- 239000000945 filler Substances 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 229910052593 corundum Inorganic materials 0.000 claims abstract 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 67
- 229910052784 alkaline earth metal Inorganic materials 0.000 claims description 23
- 150000001342 alkaline earth metals Chemical class 0.000 claims description 23
- 239000002245 particle Substances 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 229910052700 potassium Inorganic materials 0.000 claims description 15
- 238000001962 electrophoresis Methods 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000002518 antifoaming agent Substances 0.000 claims description 3
- 239000011230 binding agent Substances 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims 8
- 238000000151 deposition Methods 0.000 claims 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 101
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 229910000287 alkaline earth metal oxide Inorganic materials 0.000 abstract 1
- 239000010419 fine particle Substances 0.000 abstract 1
- 239000000155 melt Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 238000005245 sintering Methods 0.000 abstract 1
- 238000011156 evaluation Methods 0.000 description 43
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 37
- 229910052710 silicon Inorganic materials 0.000 description 37
- 239000010703 silicon Substances 0.000 description 37
- 238000009792 diffusion process Methods 0.000 description 30
- 229910000480 nickel oxide Inorganic materials 0.000 description 26
- 239000000758 substrate Substances 0.000 description 26
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 21
- 239000011787 zinc oxide Substances 0.000 description 19
- 229910052796 boron Inorganic materials 0.000 description 17
- 239000000126 substance Substances 0.000 description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 16
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Inorganic materials [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 16
- 239000012535 impurity Substances 0.000 description 16
- 238000002161 passivation Methods 0.000 description 15
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 14
- 230000009471 action Effects 0.000 description 14
- 238000012360 testing method Methods 0.000 description 14
- 238000002425 crystallisation Methods 0.000 description 13
- 230000008025 crystallization Effects 0.000 description 13
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 238000007747 plating Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 229910004009 SiCy Inorganic materials 0.000 description 9
- 238000000465 moulding Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 239000011701 zinc Substances 0.000 description 4
- -1 CaCCg Chemical compound 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 238000004017 vitrification Methods 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000007572 expansion measurement Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N lead(II) oxide Inorganic materials [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
- VTHJTEIRLNZDEV-UHFFFAOYSA-L magnesium dihydroxide Chemical compound [OH-].[OH-].[Mg+2] VTHJTEIRLNZDEV-UHFFFAOYSA-L 0.000 description 1
- 229910001862 magnesium hydroxide Inorganic materials 0.000 description 1
- 235000012254 magnesium hydroxide Nutrition 0.000 description 1
- 239000000347 magnesium hydroxide Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A semiconductor device production method including, in order: a first step in which a semiconductor element having a pn junction-exposed section is prepared; a second step in which an insulation layer is formed so as to cover the pn junction-exposed section; and a third step in which a layer comprising a glass composition for semiconductor junction protection is formed upon the insulation layer, and then a glass layer is formed upon the insulation layer by sintering the layer comprising the glass composition for semiconductor junction protection. The glass composition for semiconductor junction protection comprises glass fine particles prepared from a melt obtained by melting a raw material containing at least two alkali earth metal oxides from among at least SiO2, Al2O3, B2O3, ZnO, CaO, MgO, and BaO, and not substantially containing Pb, As, Sb, Li, Na, or K. In addition none of the raw material components are included as fillers. As a result, a semiconductor device having high pressure resistance similar to conventional semiconductor devices can be obtained using a glass material not including lead.
Description
Description
TITLE OF THE INVENTION
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
TECHNICAL FIELD
[0001]
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device.
BACKGROUND ART
[0002]
There has been known a method of manufacturing a semiconductor device where a glass layer for passivation is formed such that the glass layer covers a pn junction exposure portion in a process of manufacturing a mesa semiconductor device (see patent document 1, for example).
[0003]
Fig. 12(a) to Fig. 12(d) and Fig. 13(a) to Fig. 13(d) are views for explaining such a conventional method of manufacturing a semiconductor device. Fig. 12(a) to Fig. 12(d) and Fig. 13 (a) to Fig. 13(d) are views showing respective steps.
The conventional method of manufacturing a semiconductor device includes, as shown in Fig. 12 and Fig. 13, "semiconductor base body forming step", "trench forming step", "glass layer forming step", "photoresist forming step", "oxide film removing step", "roughened surface region forming step", "electrode forming step", and "semiconductor base body cutting step" in this order. Hereinafter, the conventional method of manufacturing a semiconductor device is explained in order of steps.
[0004] (a) Semiconductor base body forming step
Firstly, a p+ type diffusion layer 912 is formed by diffusion of a p type impurity from one surface of an n~ type semiconductor substrate (n_type silicon substrate) 910, and an n+ type diffusion layer 914 is formed by diffusion of an n type impurity from the other surface of the n~ type semiconductor substrate 910 thus forming a semiconductor base body in which a pn junction arranged parallel to a main surface of the semiconductor base body is formed. Thereafter, oxide films 916, 918 are formed by thermal oxidation on a surface of the p+ type diffusion layer 912 and a surface of the n+ type diffusion layer 914 respectively (see Fig. 12(a)).
[0005] (b) Trench forming step
Next, a predetermined opening portion is formed on the oxide film 916 at a predetermined position by photo etching. After etching the oxide film, subsequently, the semiconductor base body is etched thus forming a trench 920 having a depth exceeding the pn junction from one surface of the semiconductor base body (see Fig. 12(b)).
[0006] (c) Glass layer forming step
Next, a layer made of glass composition for protecting a semiconductor junction is formed on an inner surface of the trench 920 and a surface of the semiconductor base body in the vicinity of the trench 920 by an electrophoresis method, and the layer made of glass composition for protecting a semiconductor junction is baked so that a glass layer 924 for passivation is formed on a surface of the trench 920 (see Fig. 12(c)).
[0007] (d) Photoresist forming step
Next, a photoresist 926 is formed such that the photoresist 926 covers a surface of the glass layer 924 (see Fig. 12(d)).
[0008] (e) Oxide film removing step
Next, the oxide film 916 is etched using the photoresist 926 as a mask so that the oxide film 916 at a portion 930 where a Ni-plating electrode film is to be formed is removed (see Fig. 13(a) ) .
[0009] (f) Roughened surface region forming step
Next, a surface of the semiconductor base body at the portion 930 where a Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 932 for enhancing adhesiveness between a Ni plating electrode and the semiconductor base body (see Fig. 13(b)).
[0010] (g) Electrode forming step
Next, a Ni plating is applied to the semiconductor base body thus forming an anode electrode 934 on the roughened surface region 932 and forming a cathode electrode 936 on the other surface of the semiconductor base body (see Fig. 13(c)). Annealing of the anode electrode 934 and the cathode electrode 936 is performed at a temperature of 600 degrees under a nitrogen atmosphere, for example.
[0011] (h) Semiconductor base body cutting step
Next, the semiconductor base body is cut by dicing or the like at a center portion of the glass layer 924 thus dividing the semiconductor base body into a plurality of chips whereby mesa semiconductor devices (pn diodes) are manufactured (see Fig. 13(d)).
[0012]
As has been explained heretofore, the conventional method of manufacturing a semiconductor device includes the step of forming the trench 920 exceeding the pn junction on one surface of the semiconductor base body where the pn junction arranged parallel to the main surface is formed (see Fig. 12(a) and Fig. 12(b)), and the step of forming the glass layer 924 for passivation in the inside of the trench 920 such that the glass layer 924 covers a pn junction exposure portion (see Fig. 12(c)) . Accordingly, in the conventional method of manufacturing a semiconductor device, by cutting the semiconductor base body after forming the glass layer 924 for passivation in the inside of the trench 920, mesa semiconductor devices having high breakdown strength (breakdown voltage) can be manufactured. [Prior art Document] [Patent document] [0013] [Patent Document 1] JP-A-2004-87955 [Summary of the Invention] [Problems that the Invention is to solve] [0014] A glass material which is used for forming a glass layer for passivation is required to satisfy all of the following conditions (a) to (d), that is, the condition (a) that the glass material can be baked at a proper temperature, the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property. In view of the above, conventionally, "a glass material containing lead silicate as a main component" has been widely used.
[0015]
However, "the glass material containing lead silicate as a main component" contains lead which imposes a large load on an environment and hence, it is thought that the use of "the glass material containing lead silicate as a main component" will be prohibited near future.
[0016]
In view of the above circumstances, the formation of a glass layer for passivation using a glass material containing no lead is considered. However, it is difficult for such a glass material containing no lead to satisfy all of the following conditions (a) to (d), that is, the condition (a) that the glass material can be baked at a proper temperature, the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property. Accordingly, the realities are that the formation of a glass layer for passivation using a glass material containing no lead has not been yet applied to a mass production process of power semiconductor devices.
[0017]
Further, according to the studies carried out by the inventors of the present invention, it is found that in the case where a glass layer for passivation is formed using a glass material containing no lead, depending on the composition of the glass layer and the baking condition of the glass layer, there arises a drawback that bubbles are liable to be generated from a boundary surface between a semiconductor base body and the glass layer in step of forming the glass layer by baking the layer made of glass composition. To overcome such a drawback, it is necessary to add a component having a defoaming action (for example, nickel oxide, zirconium oxide or the like) to the glass composition. However, there may be a case where such a component can not be added to the glass composition depending on the combination of components in the glass composition. Accordingly, the addition of the component having a defoaming action is not desirable.
[0018]
Further, according to the studies carried out by the inventors of the present invention, it is found that in the case where a glass layer for passivation is formed using a glass material containing no lead, depending on the composition of the glass layer and the baking condition of the glass layer (composition of glass: composition containing a large amount of S1O2, baking condition: performed for a short period of time), there arises a drawback that a reverse direction leak current is increased. That is, it is found that a reverse direction leak current is increased unless baking is performed for a long period of time (for example, three hours).
[0019]
The present invention has been made under the above-mentioned circumstances, and it is an object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a semiconductor device having high breakdown strength using a glass material containing no lead in the same manner as a conventional case where "a glass material containing lead silicate as a main component" is used, and such a semiconductor device.
[0020]
It is another object of the present invention to provide a method of manufacturing a semiconductor device where it is possible to suppress the generation of bubbles which may be generated from a boundary surface between a semiconductor base body and a glass layer in step of forming the glass layer by baking a layer made of glass composition regardless of the composition of the glass layer and the baking condition of the glass layer without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added, and such a semiconductor device .
[0021]
It is still another object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a semiconductor device having a low reverse direction leak current in a stable manner regardless of the composition of a glass layer and the baking condition of the glass layer, and such a semiconductor device.
Means for Solving the Task [0022] [1] The present invention is directed to a method of manufacturing a semiconductor device including, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked, wherein the glass composition for protecting a semiconductor junction is a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCg, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, and the glass composition for protecting a semiconductor junction contains none of components which constitute the raw material in the form of a filler.
[0023] [2] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, in the glass composition for protecting a semiconductor junction, the content of S1O2 falls within a range from 41.1 mol% to 61.1 mol%, the content of AI2O3 falls within a range from 7.4 mol% to 17.4 mol%, the content of B2O3 falls within a range from 5.8 mol% to 15.8 mol%, the content of ZnO falls within a range from 3.0 mol% to 24.8 mol%, and the content of oxide of an alkaline earth metal falls within a range from 5.5 mol% to 15.5 mol%.
[0024] [3] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that, in the glass composition for protecting a semiconductor junction, the content of SiCg falls within a range from 49.5 mol% to 64.3 mol%, the content of B2O3 falls within a range from 8.4 mol% to 17.9 mol%, the content of AI2O3 falls within a range from 3.7 mol% to 14.8 mol%, the content of ZnO falls within a range from 3.9 mol% to 14.2 mol%, and the content of oxide of an alkaline earth metal falls within a range from 7.4 mol% to 12.9 mol%.
[0025] [4] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the glass composition for protecting a semiconductor junction substantially contains no multivalent element as a defoaming agent.
[0026] [5] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that none of V, Mn, Sn, Ce, Nb and Ta is contained in the glass composition for protecting a semiconductor junction as the multivalent.
[0027] [6] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the raw material substantially contains no P.
[0028] [7] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the raw material substantially contains no Bi.
[0029] [8] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the glass composition for protecting a semiconductor junction substantially contains no organic binder.
[0030] [9] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the layer made of glass composition for protecting a semiconductor junction is baked at a temperature of 900°C or below in the third step .
[0031] [10] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is made of silicon oxide.
[0032] [11] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed with a thickness which falls within a range from 5nm to lOOnm in the second step.
[0033] [12] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the layer made of glass composition is formed by an electrophoresis method in the third step.
[0034] [13] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed with a thickness which falls within a range from 5nm to 60nm in the second step.
[0035] [14] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first step comprises: a step of preparing a semiconductor base body having a pn junction arranged parallel to a main surface of the semiconductor base body; and a step of forming a trench having a depth which goes beyond the pn junction from one surface of the semiconductor base body thus forming the pn junction exposure portion on an inner surface of the trench, the second step includes a step of forming the insulation layer on the inner surface of the trench such that the insulation layer covers the pn junction exposure portion, and the third step includes a step of forming the glass layer on the insulation layer.
[0036] [15] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed by a thermal oxidation method in the second step.
[0037] [16] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed by a deposit method in the second step.
[0038] [17] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first step includes a step of forming the pn junction exposure portion on a surface of a semiconductor base body, the second step includes a step of forming the insulation layer on the surface of the semiconductor base body such that the insulation layer covers the pn junction exposure portion, and the third step includes a step of forming the glass layer on the insulation layer .
[0039] [18] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed by a thermal oxidation method in the second step.
[0040] [19] In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the insulation layer is formed by a deposit method in the second step.
[0041] [20] The present invention is also directed to a semiconductor device including: a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; an insulation layer which is formed such that the insulation layer covers the pn junction exposure portion; and a glass layer which is formed on the insulation layer, the glass layer being formed such that a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked, wherein the glass composition for protecting a semiconductor junction is a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCh, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, and the glass composition for protecting a semiconductor junction contains none of components which constitute the raw material in the form of a filler.
In Japanese prior art publication no. 01 186 629 (Rohm) a thermal oxide film is formed on an inner surface of a mesa groove by a thermal oxidation method and a glass paste is applied by spinning on the thermal oxide film and then baked. Adhesion between a surface of silicon exposing on an inner surface of the mesa groove and the thermal oxide film is good and the glass paste is applied by spinning, so that the glass paste can be uniformly formed over a PN junction part. As a result, a passivation film is uniformly formed on an inner surface of the mesa groove and predetermined insulation strength can be obtained. In addition, adhesion between the passivation film and the inner surface of the mesa groove is improved, so that it is possible to eliminate clearance. However the present invention differs from the teaching of the document (Japanese prior art publication no. 01 186 629 (Rohm)) and is therefore new and involving an inventive step .
Advantage of the Invention [0042]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, as can be clearly found from examples described later, it becomes possible to provide a semiconductor device having high breakdown strength using a glass material containing no lead in the same manner as a conventional case where "a glass material containing lead silicate as a main component" is used.
[0043]
That is, the method of manufacturing a semiconductor device and such a semiconductor device of the present invention can satisfy all of the following conditions (a) to (d) , that is, the condition (a) that the glass material can be baked at a proper temperature, the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property.
[0044]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, the insulation layer having higher wettability than the semiconductor base body is interposed between the semiconductor base body and the glass layer and hence, it is possible to make bubbles hardly generated from a boundary surface between the semiconductor base body and the glass layer in step of forming the glass layer by baking the layer made of glass composition. Accordingly, it is possible to suppress the generation of bubbles without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added.
[0045]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, the insulation layer is interposed between the semiconductor base body and the glass layer and hence, insulation property is enhanced whereby, as can be clearly found from the examples described later, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner regardless of the composition of the glass layer and the baking condition of the glass layer. That is, even when the content of SiCg is 55 mol% or more or even when a baking time is set to approximately 15 minutes, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0046]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, a glass layer is formed by baking the layer made of glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCg, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K. Accordingly, as can be also clearly found from the examples described later, baking of the glass layer can be performed at a relatively low temperature and hence, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0047]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, the glass layer is formed by baking the layer made of glass composition for protecting a semiconductor junction which contains none of components which constitute the raw material in the form of a filler. Accordingly, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0048]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, it is possible to manufacture a semiconductor device having a glass layer made of lead-free glass (glass containing no Pb) which has a lower dielectric constant than lead-containing glass. Accordingly, when a resin-sealed-type semiconductor device is formed by molding the semiconductor device of the present invention with a resin, there is no possibility that highly concentrated ion is induced on an interface between the mold resin and the glass layer and an interface between the glass layer and the semiconductor layer in the midst of carrying out a high temperature reverse bias test. As a result, the semiconductor device of the present invention can acquire an advantageous effect that resistance against a high temperature reverse bias is increased compared to the conventional resin-sealed-type semiconductor device which is formed by molding a semiconductor device obtained by using "a glass material containing lead silicate as a main component" with a resin.
[0049]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, the glass composition which substantially contains none of Li, Na and K is used and hence, as can be clearly found from examples described later (evaluation aspect 10) , even when the glass composition contains B (boron), there is no possibility that B (boron) is diffused into silicon from the glass layer during baking of the glass composition whereby a highly reliable semiconductor device can be manufactured.
[0050]
In the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, "contains at least specific components (SiCg, AI2O3, B2O3 and the like)" means not only a case where only the specific components are contained but also a case where components which can be usually contained in the glass composition are further contained in addition to the specific components.
[0051]
In the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, "substantially contains none of specific elements (Pb, As, Sb and the like)" means "substantially contains none of specific elements as components" and does not exclude the glass composition where the above-mentioned specific elements are mixed into raw materials for the respective components which constitute glass as impurities.
[0052]
Further, in the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, "substantially contains none of specific elements (Pb, As, Sb and the like)" means "substantially contains none of oxides of the specific elements, nitrides of the specific elements and the like".
[0053]
Further, in the method of manufacturing a semiconductor device and such a semiconductor device of the present invention, "contains none of components which constitute the raw material in the form of a filler" means that when the component is SiCg, for example, the component SiCg is not contained in the form of an embedding material, a packing material, a filling material, an addition material or the like formed of fine SiCg particles.
BRIEF DESCRIPTION OF THE DRAWINGS
[0054]
Fig. 1(a) to Fig. 1(d) are views for explaining a method of manufacturing a semiconductor device according to an embodiment 1.
Fig. 2(a) to Fig. 2(d) are views for explaining the method of manufacturing the semiconductor device of the embodiment 1.
Fig. 3(a) to Fig. 3(d) are views for explaining a method of manufacturing a semiconductor device of an embodiment 2.
Fig. 4(a) to Fig. 4(d) are views for explaining the method of manufacturing the semiconductor device of the embodiment 2.
Fig. 5 is a Table showing conditions and results of examples .
Fig. 6(a) and Fig. 6(b) are views for explaining bubbles b generated in the inside of a glass layer 124 in a preliminary evaluation .
Fig. 7(a) and Fig. 7(b) are photographs for explaining bubbles b generated in the inside of the glass layer 124 in a subsequent evaluation.
Fig. 8 is a TEM photograph showing a cross section of a portion including a boundary between a semiconductor base body and a glass layer.
Fig. 9(a) and Fig. 9(b) are graphs showing a reverse direction current in the examples.
Fig. 10 is a graph showing a result of a high temperature reverse bias test.
Fig. 11 is a graph showing the distribution of impurity concentration in the depth direction from a surface of a silicon substrate .
Fig. 12(a) to Fig. 12(d) are views for explaining a conventional method of manufacturing a semiconductor device.
Fig. 13(a) to Fig. 13(d) are views for explaining the conventional method of manufacturing the semiconductor device.
MODE FOR CARRYING OUT THE INVENTION
[0055]
Hereinafter, a method of manufacturing a semiconductor device, and a semiconductor device according to the present invention are explained in conjunction with embodiments shown in the drawings .
[0056] [Embodiment 1]
The method of manufacturing a semiconductor device of the embodiment lisa method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked. In the method of manufacturing a semiconductor device of the embodiment 1, mesa-type pn diodes are manufactured as semiconductor devices.
[0057]
Fig, 1(a) to Fig. 1(d) and Fig. 2(a) to Fig. 2(d) are views for explaining a method of manufacturing a semiconductor device of the embodiment 1. Fig, 1(a) to Fig. 1(d) and Fig. 2(a) to Fig. 2(d) are views showing respective steps.
In the method of manufacturing a semiconductor device of the embodiment 1, as shown in Fig. 1(a) to Fig. 1(d) and Fig. 2(a) to Fig. 2(d), "semiconductor base body preparing step", "trench forming step", "insulation layer forming step", "glass layer forming step", "photoresist forming step", "oxide film removing step", "roughened surface region forming step", "electrode forming step", and "semiconductor base body cutting step" are carried out in this order. Hereinafter, the method of manufacturing the semiconductor device of the embodiment 1 is explained in order of steps.
[0058] (a) Semiconductor base body preparing step
Firstly, a p+ type diffusion layer 112 is formed by diffusion of a p type impurity from one surface of an n~ type semiconductor substrate (n_type silicon substrate) 110, and an n+ type diffusion layer 114 is formed by diffusion of an n type impurity from the other surface of the n~ type semiconductor substrate 110 thus preparing a semiconductor base body in which a pn junction arranged parallel to a main surface of the semiconductor base body is formed. Thereafter, oxide films 116, 118 are formed by thermal oxidation on a surface of the p+ type diffusion layer 112 and a surface of the n+ type diffusion layer 114 respectively (see Fig. 1(a)).
[0059] (b) Trench forming step
Next, a predetermined opening portion is formed on the oxide film 116 at a predetermined position by a photo etching method. After etching the oxide film, subsequently, the semiconductor base body is etched thus forming a trench 120 having a depth exceeding the pn junction from one surface of the semiconductor base body (see Fig. 1(b)). Here, a pn junction exposure portion A is formed on an inner surface of the trench.
[0060] (c) Insulation layer forming step
Next, an insulation layer 121 formed of a silicon oxide film is formed on an inner surface of the trench 120 by a thermal oxidation method using dry oxygen (DryCg) (see Fig. 1(c)). A thickness of the insulation layer 121 is set to a value which falls within a range from 5nm to 60nm (for example, 20nm) . The insulation layer 121 is formed such that the semiconductor base body is introduced into a diffusion furnace and, thereafter, thermal oxidation treatment is performed at a temperature of 900°C for 10 minutes while supplying an oxygen gas into the diffusion furnace. When the thickness of the insulation layer 121 is less than 5nm, there exists a possibility that a reverse-direction current reduction effect cannot be acquired. On the other hand, when the thickness of the insulation layer 121 exceeds 60nm, there exists a possibility that a layer made of glass composition cannot be formed by an electrophoresis method in the next glass layer forming step.
[0061] (d) Glass layer forming step
Next, a layer made of glass composition for protecting a semiconductor junction is formed on the inner surface of the trench 120 and a surface of the semiconductor base body in the vicinity of the trench 120 by an electrophoresis method, and the layer made of glass composition for protecting a semiconductor junction is baked so that a glass layer 124 for passivation is formed (see Fig. 1(d)). A baking temperature is set to 900°C, for example. Here, in forming the layer made of glass composition for protecting a semiconductor junction on the inner surface of the trench 120, the layer made of glass composition for protecting a semiconductor junction is formed so as to cover the inner surface of the trench 120 by way of the insulation layer 121. Accordingly, the pn junction exposure portion A in the trench 120 is covered with the glass layer 124 by way of the insulation layer 121.
[0062]
As the glass composition for protecting a semiconductor junction, used is a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCg, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing none of components which constitute the raw material in the form of a filler .
[0063]
As such glass composition for protecting a semiconductor junction, a glass composition is preferably used where the content of SiCp falls within a range from 41.1 mol% to 61.1 mol%, the content of AI2O3 falls within a range from 7.4 mol% to 17.4 mol%, the content of B2O3 falls within a range from 5.8 mol% to 15.8 mol%, the content of ZnO falls within a range from 3.0 mol% to 24.8 mol%, the content of oxide of an alkaline earth metal falls within a range from 5.5 mol% to 15.5 mol%, and the content of nickel oxide falls within a range from 0.01 mol% to 2.0 mol%. Further, a glass composition is preferably used where, with respect to oxide of an alkaline earth metal, the content of CaO falls within a range from 2.8 mol% to 7.8 mol%, the content of MgO falls within a range from 1.1 mol% to 3.1 mol%, and the content of BaO falls within a range from 1.7 mol% to 4.7 mol%.
[0064]
As the glass composition for protecting a semiconductor junction, a glass composition which substantially contains no multivalent element (for example, V, Mn, Sn, Ce, Nb and Ta) as a defoaming agent is used. Further, as the glass composition for protecting a semiconductor junction, a glass composition which contains no organic binder is used.
[0065]
As a raw material for the glass composition for protecting a semiconductor junction, it is preferable to use a raw material which substantially contains no P. Further, it is preferable to use a raw material which substantially contains no Bi.
[0066]
In this case, "contains specific components (SiCy, AI2O3, B2O3 and the like)" means not only a case where only the specific components are contained but also a case where components which can be usually contained in the glass composition are further contained in addition to the specific components. Further, "substantially contains none of specific elements (Pb, As, Sb and the like)" means "substantially contains none of specific elements as components" and does not exclude the glass composition where the above-mentioned specific elements are mixed into raw materials for the respective components which constitute glass as impurities. Further, "substantially contains none of specific elements (Pb, As, Sb and the like)" means "substantially contains none of oxides of specific elements, nitrides of specific elements and the like". Further, "contains none of components which constitute the raw material in the form of a filler" means that when the component is SiCg, for example, the component SiCy is not contained in the form of an embedding material, a packing material, a filling material, an addition material or the like formed of fine SiCy particles.
[0067]
The reason the content of the SiCy is set to a value which falls within a range from 41.1 mol% to 61.1 mol% is that when the content of SiCy is less than 41.1 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded, while when the content of SiCp exceeds 61.1 mol%, there exists a tendency that a baking temperature needs to be elevated.
[0068]
The reason the content of AI2O3 is set to a value which falls within a range from 7.4 mol% to 17.4 mol% is that when the content of AI2O3 is less than 7.4 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded, while when the content of AI2O3 exceeds 17.4 mol%, there exists a tendency that a baking temperature needs to be elevated.
[0069]
The reason the content of B2O3 is set to a value which falls within a range from 5.8 mol% to 15.8 mol% is that when the content of B2O3 is less than 5.8 mol%, there exists a tendency that a baking temperature needs to be elevated, while when the content of B2O3 exceeds 15.8 mol%, there may be a case where boron is diffused into the semiconductor base body in step of baking the glass layer thus degrading the insulation property.
[0070]
The reason the content of ZnO is set to a value which falls within a range from 3.0 mol% to 24.8 mol% is that when the content of ZnO is less than 3.0 mol%, there exists a tendency that a baking temperature needs to be elevated, while when the content of ZnO exceeds 24.8 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded.
[0071]
The reason the content of oxide of alkaline earth metal is set to a value which falls within a range from 5.5 mol% to 15.5 mol% is that when the content of oxide of alkaline earth metal is less than 5.5 mol%, there exists a tendency that a baking temperature needs to be elevated, while when the content of oxide of alkaline earth metal exceeds 15.5 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded.
[0072]
Out of oxides of alkaline earth metals, the reason the content of CaO is set to a value which falls within a range from 2.8 mol% to 7.8 mol% is that when the content of CaO is less than 2.8 mol%, there exists a tendency that a baking temperature needs to be elevated, while when the content of CaO exceeds 7.8 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded.
[0073]
The reason the content of MgO is set to a value which falls within a range from 1.1 mol% to 3.1 mol% is that when the content of MgO is less than 1.1 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded, while when the content of MgO exceeds 3.1 mol%, there exists a tendency that a baking temperature needs to be elevated.
[0074]
The reason the content of BaO is set to a value which falls within a range from 1.7 mol% to 4.7 mol% is that when the content of BaO is less than 1.7 mol%, there exists a tendency that a baking temperature needs to be elevated, while when the content of BaO exceeds 4.7 mol%, there may be a case where the chemical resistance is deteriorated or the insulation property is degraded.
[0075]
The reason the content of nickel oxide is set to a value which falls within a range from 0.01 mol% to 2.0 mol% is that when the content of nickel oxide is less than 0.01 mol%, there exists a case where it becomes difficult to suppress the generation of bubbles which may be generated from a boundary surface between a "layer made of glass composition for protecting a semiconductor junction" formed by an electrophoresis method and a semiconductor base body (silicon) in step of baking the layer made of glass composition for protecting a semiconductor junction, while when the content of nickel oxide exceeds 2.0 mol%, there may be a case where it becomes difficult to manufacture homogeneous glass.
[0076]
The glass composition for protecting a semiconductor junction according to the embodiment 1 can be manufactured as follows. That is, raw materials (Si02, Α1(ΟΗ)3, H3BO3, ZnO, CaCCg, Mg(OH)2, BaO and NiO (nickel oxide)) are prepared at the above-mentioned composition ratio (molar ratio), these raw materials are sufficiently mixed by a mixer and, thereafter, the mixed raw material is put into a platinum crucible whose temperature is elevated to a predetermined temperature (1550°C, for example) in an electric furnace and is melted for a predetermined time. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. Thereafter, the glass flakes are pulverized by a ball mill or the like until the glass flakes obtain a predetermined average particle size thus obtaining the powdery glass composition. The obtained powdery glass composition is directly used as the glass composition for protecting a semiconductor junction.
[0077] (e) Oxide film removing step
Next, the photoresist 126 is formed so as to cover the surface of the glass layer 124 and, thereafter, the oxide film 116 is etched using the photoresist 126 as a mask so that the oxide film 116 at a portion 130 where a Ni-plating electrode film is to be formed is removed (see Fig. 2(a)).
[0078] (f) Roughened surface region forming step
Next, a surface of the semiconductor base body at the portion 130 where a Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 132 for enhancing adhesiveness between a Ni plating electrode and the semiconductor base body (see Fig. 2(b)) .
[0079] (g) Electrode forming step
Next, a Ni plating is applied to the semiconductor base body thus forming an anode electrode 134 on the roughened surface region 132 and forming a cathode electrode 136 on the other surface of the semiconductor base body (see Fig. 2(c)). Annealing of the anode electrode 134 and the cathode electrode 136 is performed at a temperature of 600 degrees under a nitrogen atmosphere, for example.
[0080] (h) Semiconductor base body cutting step
Next, the semiconductor base body is cut by dicing or the like at a center portion of the glass layer 124 thus dividing the semiconductor base body into chips whereby semiconductor devices (mesa-type pn diodes) 100 are manufactured (see Fig. 2(d)).
[0081]
Through the above-mentioned steps, the semiconductor devices 100 according to the embodiment 1 can be manufactured.
[0082]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, as can be clearly found from examples described later, it becomes possible to provide a semiconductor device having high breakdown strength using a glass material containing no lead in the same manner as a conventional case where "a glass material containing lead silicate as a main component" is used.
[0083]
That is, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1 can satisfy all of the following conditions (a) to (d) , that is, the condition (a) that the glass material can be baked at a proper temperature (900° or below, for example), the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property. In this case, with the use of the glass composition for protecting a semiconductor junction which contains 55 mol% or more of SiCy and B2O3 in sum as the glass composition for protecting a semiconductor junction, chemical resistance of the glass composition can be enhanced.
[0084]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the insulation layer 121 having higher wettability than the semiconductor base body is interposed between the semiconductor base body and the glass layer 124 and hence, it is possible to make bubbles hardly generated from a boundary surface between the semiconductor base body and the glass layer 124 in step of forming the glass layer by baking the layer made of glass composition. Accordingly, it is possible to suppress the generation of bubbles without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added.
[0085]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the insulation layer 121 is interposed between the semiconductor base body and the glass layer 124 and hence, insulation property is enhanced whereby, as can be clearly found from the examples described later, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner regardless of the composition of the glass layer and the baking condition of the glass layer. That is, even when the content of SiCg is 55 mol% or more or even when a baking time is set to approximately 15 minutes, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0086]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, a glass layer is formed by baking the layer made of glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCg, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K. Accordingly, as can be also clearly found from the examples described later, baking of the glass layer can be performed at a relatively low temperature and hence, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0087]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the glass layer is formed by baking the layer made of glass composition for protecting a semiconductor junction which contains none of components which constitute the raw material in the form of a filler. Accordingly, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0088]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, it is possible to manufacture a semiconductor device having a glass layer made of lead-free glass (glass containing no Pb) which has a lower dielectric constant than lead-containing glass. Accordingly, when a resin-sealed-type semiconductor device is formed by molding the semiconductor device of the embodiment 1 with a resin, there is no possibility that highly concentrated ion is induced on an interface between the mold resin and the glass layer and an interface between the glass layer and the semiconductor layer in the midst of carrying out a high temperature reverse bias test. As a result, the semiconductor device of the present invention can acquire an advantageous effect that resistance against a high temperature reverse bias is increased compared to the conventional resin-sealed-type semiconductor device which is formed by molding a semiconductor device obtained by using "a glass material containing lead silicate as a main component" with a resin .
[0089]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the glass composition which substantially contains none of Li, Na and K is used and hence, as can be also clearly found from examples described later (evaluation aspect 10) , even when the glass composition contains B (boron), there is no possibility that B (boron) is diffused into silicon from the glass layer during baking of the glass composition whereby a highly reliable semiconductor device can be manufactured.
[0090] [Embodiment 2]
In the same manner as the method of manufacturing a semiconductor device of the embodiment 1, the method of manufacturing a semiconductor device of the embodiment 2 is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a silicon-made semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked. However, in the method of manufacturing a semiconductor device of the embodiment 2, a planar-type pn-diode is manufactured as a semiconductor device different from the method of manufacturing a semiconductor device of the embodiment 1.
[0091]
Fig, 3(a) to Fig. 3(d) and Fig. 4(a) to Fig. 4(d) are views for explaining the method of manufacturing a semiconductor device of the embodiment 2 . Fig, 3(a) to Fig. 3 (d) and Fig. 4 (a) to Fig. 4(d) are views showing respective steps.
In the method of manufacturing the semiconductor device of the embodiment 2, as shown in Fig. 3(a) to Fig. 3(d) and Fig. 4(a) to Fig. 4(d), "semiconductor base body preparing step", "p+ type diffusion layer forming step", "n+ type diffusion layer forming step", "insulation layer forming step", "glass layer forming step", "etching step" and "electrode forming step" are carried out in this order. Hereinafter, the method of manufacturing a semiconductor device of the embodiment 2 is explained in order of steps.
[0092] (a) Semiconductor base body preparing step
Firstly, a semiconductor base body where an n~ type epitaxial layer 212 is laminated on an n+ type semiconductor substrate 210 is prepared (see Fig. 3(a)).
[0093] (b) p+ type diffusion layer forming step
Next, after forming a mask Ml on the n~ type epitaxial layer 212, a p type impurity (boron ion, for example) is implanted to a predetermined region on a surface of the n~ type epitaxial layer 212 by an ion implantation method using the mask Ml. Then, a p+ type diffusion layer 214 is formed by thermal diffusion (see Fig. 3(b)).
[0094] (c) n+ type diffusion layer forming step
Next, the mask Ml is removed from the n~ type epitaxial layer 212 and a mask M2 is formed on the n~ type epitaxial layer 212. Thereafter, an n type impurity (arsenic ion, for example) is implanted to a predetermined region on the surface of the n~ type epitaxial layer 212 by an ion implantation method using the mask M2. Then, an n+ type diffusion layer 216 is formed by thermal diffusion (see Fig. 3(c)). Here, a pn junction exposure portion A is formed on a surface of the semiconductor base body.
[0095] (d) Insulation layer forming step
Next, the mask M2 is removed and, thereafter, an insulation layer 218 formed of a silicon oxide film is formed on a surface of the n~ type epitaxial layer 212 (and a back surface of the n+ type silicon substrate 210) by a thermal oxidation method using dry oxygen (DryCq) (see Fig. 3(d)). A thickness of the insulation layer 218 is set to a value which falls within a range from 5nm to 60nm (for example, 20nm) . The insulation layer 218 is formed such that the semiconductor base body is introduced into a diffusion furnace and, thereafter, thermal oxidation treatment is performed at a temperature of 900°C for 10 minutes by supplying an oxygen gas into the diffusion furnace. When the thickness of the insulation layer 218 is less than 5nm, there exists a possibility that a reverse-direction current reduction effect cannot be acquired. On the other hand, when the thickness of the insulation layer 218 exceeds 60nm, there exists a possibility that a layer made of glass composition cannot be formed by an electrophoresis method in the next glass layer forming step.
[0096] (e) Glass layer forming step
Next, a layer made of glass composition for protecting a semiconductor junction is formed on a surface of the insulation layer 218 by an electrophoresis method in the same manner as the embodiment 1 and, thereafter, the layer made of glass composition is baked so that a glass layer 220 for passivation is formed (see Fig. 4(a)). A baking temperature is set to 900°C, for example.
[0097] (f) Etching step
Next, a mask M3 is formed on a surface of the glass layer 220 and, thereafter, the glass layer 220 is etched (see Fig. 4(b) ) and, subsequently, the insulation layer 218 is etched (see Fig. 4(c)). Due to such etching, the insulation layer 218 and the glass layer 220 are formed on a predetermined region on the surface of the n~ type epitaxial layer 212.
[0098] (g) Electrode forming step
Next, the mask M3 is removed from the surface of the glass layer 220 and, thereafter, an anode electrode 222 is formed on a region on the surface of the semiconductor base body surrounded by the glass layer 220, and a cathode electrode 224 is formed on a back surface of the semiconductor base body. Annealing of the anode electrode 222 and the cathode electrode 224 is performed at a temperature of 600 degrees under a nitrogen atmosphere, for example.
[0099] (h) Semiconductor base body cutting step
Next, the semiconductor base body is cut by dicing or the like thus dividing the semiconductor base body into chips whereby semiconductor devices (planer-type pn diodes) 200 are manufactured (see Fig. 4(d)).
[0100]
Through the above-mentioned steps, the semiconductor devices 200 of the embodiment 2 can be manufactured.
[0101]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, as can be also clearly found from examples described later, it becomes possible to provide a semiconductor device having high breakdown strength using a glass material containing no lead in the same manner as a conventional case where "a glass material containing lead silicate as a main component" is used.
[0102]
That is, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, can satisfy all of the following conditions (a) to (d), that is, the condition (a) that the glass material can be baked at a proper temperature (900° or below, for example), the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property.
[0103]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, the insulation layer 218 having higher wettability than the semiconductor base body is interposed between the semiconductor base body and the glass layer 220 and hence, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, it is possible to make bubbles hardly generated from a boundary surface between the semiconductor base body and the glass layer 220 in step of forming the glass layer by baking the layer made of glass composition. Accordingly, it is possible to suppress the generation of bubbles without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added.
[0104]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, the insulation layer 218 is interposed between the semiconductor base body and the glass layer 220 and hence, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, insulation property is enhanced whereby it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner regardless of the composition of the glass layer and the baking condition of the glass layer. That is, even when the content of SiCy is 55 mol% or more or even when a baking time is set to approximately 15 minutes, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0105]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, the glass layer 220 is formed by baking the layer made of glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCy, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K. Accordingly, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, baking of the glass layer can be performed at a relatively low temperature and hence, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0106]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, the glass layer 220 is formed by baking the layer made of glass composition for protecting a semiconductor junction which contains none of components which constitute the raw material in the form of a filler. Accordingly, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0107]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, when a resin-sealed-type semiconductor device is formed by molding the semiconductor device of the embodiment 2 with a resin, there is no possibility that highly concentrated ion is induced on an interface between the mold resin and the glass layer and an interface between the glass layer and the semiconductor layer in the midst of carrying out a high temperature reverse bias test. As a result, the semiconductor device of the present invention can acquire an advantageous effect that resistance against a high temperature reverse bias is increased compared to the conventional resin-sealed-type semiconductor device which is formed by molding a semiconductor device obtained by using "a glass material containing lead silicate as a main component" with a resin.
[0108]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 2, the glass composition which substantially contains none of Li, Na and K is used and hence, as can be also clearly found from examples described later (evaluation aspect 10) , even when the glass composition contains B (boron), there is no possibility that B (boron) is diffused into silicon from the glass layer during baking of the glass composition whereby a highly reliable semiconductor device can be manufactured.
[0109] [Embodiment 3]
In the same manner as the method of manufacturing a semiconductor device of the embodiment 1, the method of manufacturing a semiconductor device of the embodiment 3 is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a silicon-made semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked. Further, in the same manner as the method of manufacturing a semiconductor device of the embodiment 1, as the glass composition for protecting a semiconductor junction, used is a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCy, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, and the glass composition for protecting a semiconductor junction contains none of components which constitute the raw material in the form of a filler. The semiconductor device of the embodiment 3 is a semiconductor device manufactured by the method of manufacturing a semiconductor device of the embodiment 3.
[0110]
Here, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3 differ from the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1 with respect to the constitution of a raw material for fine glass particles.
[0111]
That is, in the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, as a raw material for forming the fine glass particles, used is a raw material where the content of SiCp falls within a range from 49.5 mol% to 64.3 mol%, the content of B2O3 falls within a range from 8.4 mol% to 17.9 mol%, the content of AI2O3 falls within a range from 3.7 mol% to 14.8 mol%, the content of ZnO falls within a range from 3.9 mol% to 14.2 mol%, and the content of oxide of an alkaline earth metal falls within a range from 7.4 mol% to 12.9 mol%.
[0112]
The raw material contains all of CaO, MgO and BaO as oxide of the alkaline earth metal. The content of CaO falls within a range from 2.0 mol% to 5.3 mol%, the content of MgO falls within a range from 1.0 mol% to 2.3 mol%, and the content of BaO falls within a range from 2.6 mol% to 5.3 mol%. In the raw material, the sum of the content of S1O2 and the content of B2O3 falls within a range from 65 mol% to 75 mol%. An average linear expansion coefficient of the glass composition for protecting a semiconductor junction within a temperature range from 50°C to 550°C falls within a range from 3.33X1CT6 to 4.08X1CT6.
[0113]
In this manner, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3 differ from the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1 with respect to the constitution of a raw material for fine glass particles. However, in the same manner as the method of manufacturing a semiconductor device of the embodiment 1, the method of manufacturing a semiconductor device of the embodiment 3 is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked. Further, as the glass composition for protecting a semiconductor junction, used is a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCh, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, and the glass composition for protecting a semiconductor junction contains none of components which constitute the raw material in the form of a filler. Accordingly, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3 have substantially same advantageous effects as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1.
[0114]
That is, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, as can be also clearly found from examples described later, it becomes possible to provide a semiconductor device having high breakdown strength using a glass material containing no lead in the same manner as a conventional case where "a glass material containing lead silicate as a main component" is used. In other words, the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, can satisfy all of the following conditions (a) to (d), that is, the condition (a) that the glass material can be baked at a proper temperature (900°C or below, for example), the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) so as to prevent the warping of a wafer during steps, and the condition (d) that the glass material has excellent insulation property.
[0115]
According to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, the insulation layer having higher wettability than the semiconductor base body is interposed between the semiconductor base body and the glass layer and hence, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, it is possible to make bubbles hardly generated from a boundary surface between the semiconductor base body and the glass layer in step of forming the glass layer by baking the layer made of glass composition. Accordingly, it is possible to suppress the generation of bubbles without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added.
[0116]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, the insulation layer is interposed between the semiconductor base body and the glass layer and hence, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, insulation property is enhanced whereby it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner regardless of the composition of the glass layer and the baking condition of the glass layer. That is, even when the content of SiCg is 55 mol% or more or even when a baking time is set to approximately 15 minutes, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0117]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, a glass layer is formed by baking the layer made of glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state which is obtained by melting a raw material which contains at least SiCg, AI2O3, B2O3, ZnO, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K. Accordingly, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, baking of the glass layer can be performed at a relatively low temperature and hence, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0118]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, the glass layer 124 is formed by baking the layer made of glass composition for protecting a semiconductor junction which contains none of components which constitute the raw material in the form of a filler. Accordingly, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, the crystallization of the glass layer hardly occurs in step of baking the glass layer. Also due to such a technical feature, it is possible to manufacture a semiconductor device having a low reverse direction leak current in a stable manner.
[0119]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, in the same manner as the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 1, when a resin-sealed-type semiconductor device is formed by molding the semiconductor device of the embodiment 3 with a resin, there is no possibility that highly concentrated ion is induced on an interface between the mold resin and the glass layer and an interface between the glass layer and the semiconductor layer in the midst of carrying out a high temperature reverse bias test. As a result, the semiconductor device of the present invention can acquire an advantageous effect that resistance against a high temperature reverse bias is increased compared to the conventional resin-sealed-type semiconductor device which is formed by molding a semiconductor device obtained by using "a glass material containing lead silicate as a main component" with a resin.
[0120]
Further, according to the method of manufacturing a semiconductor device and such a semiconductor device of the embodiment 3, the glass composition which substantially contains none of Li, Na and K is used and hence, as can be also clearly found from examples described later (evaluation aspect 10) , even when the glass composition contains B (boron), there is no possibility that B (boron) is diffused into silicon from the glass layer during baking of the glass composition whereby a highly reliable semiconductor device can be manufactured.
[0121] [Examples] 1. Preparation of specimens
Fig. 5 is a table showing conditions and results of examples. In the examples, raw materials are prepared to have composition ratios described in examples 1 to 11 and comparison examples 1 to 6 (see Fig. 5) , these raw materials are sufficiently mixed by a mixer and, thereafter, the mixed raw material is put into a platinum crucible whose temperature is elevated to a predetermined temperature (1350°C to 1550°C) in an electric furnace and is melted for two hours. Thereafter, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. Thereafter, the glass flakes are pulverized by a ball mill until the glass flakes obtain an average particle size of 5μπι thus obtaining powdery glass composition.
[0122]
The raw materials used in the examples are Si02, AI2O3, H3BO3, ZnO, CaCCb, MgO, BaCCb, NiO (nickel oxide) , Zr02, PbO, K20 and Na20.
[0123] 2 . Evaluation
The respective glass compositions obtained by the above-mentioned methods are evaluated with respect to the following evaluation aspects. Out of the evaluation aspects 1 to 9, with respect to the evaluation aspects 5, 6, 8 and 9, a glass layer is formed on an insulation layer in examples 1 to 11, while a glass layer is directly formed on a semiconductor base body in comparison examples 1 to 6. Baking of the glass layers is performed at a temperature of 800°C to 900°C for 15 minutes. The glass compositions in the examples 1 to 3 are glass compositions included in the glass composition used in the embodiment 1, and the glass compositions in the examples 4 to 11 are glass compositions included in the glass composition used in the embodiment 3. The glass composition of the comparison example 1 is the conventional "glass composition containing lead silicate as a main component". Further, the glass composition of the comparison example 2 is the conventionally known "lead-free glass composition (zinc-based passivation glass GP014 made by Nippon Electric Glass Co., Ltd.). The glass composition of the comparison example 3 is equal to the glass composition of the example 6. The glass composition of the comparison example 4 has the glass composition of the example 6 as the base composition and further contains 3.Omol% of NiO (nickel oxide). The glass composition of the comparison example 5 is equal to the glass composition of the example 1. The glass composition of the comparison example 6 is the glass composition which also contains B and alkaline metal ( Si02-B203-K20-Na20 based glass composition).
[0124] (1) Evaluation aspect 1 (environmental load)
One of the objects of the present invention lies in that a semiconductor device having high breakdown strength can be manufactured by using a glass material containing no lead in the same manner as the conventional case where "a glass material containing lead silicate as a main component" is used and hence, the score "good" is given when the glass composition contains no lead component, and the score "bad" is given when the glass composition contains a lead component.
[0125] (2) Evaluation aspect 2 (baking temperature)
When the baking temperature is excessively high, the baking temperature largely influences a semiconductor device under manufacture. Accordingly, the score "good" is given when the baking temperature is equal to or below 900°C, and the score "bad" is given when the baking temperature exceeds 900°C.
[0126] (3) Evaluation aspect 3 (chemical resistance)
The score "good" is given when the glass composition exhibits insolubility to both aqua regia and a plating solution, and the score "bad" is given when the glass composition exhibits solubility to at least one of aqua regia and a plating solution.
[0127] (4) Evaluation aspect 4 (average linear expansion coefficient)
Flaky glass plates are prepared from a material in a molten state which is obtained in "1. Preparation of specimens" described above, and an average linear expansion coefficient of the glass composition at a temperature of 50°C to 550°C is measured using such flaky glass plates. As a result, the score "good" is given when the difference between an average linear expansion coefficient of the glass composition and a linear expansion coefficient (3.73 X 1CT6) of silicon at a temperature of 50°C to 550°C is equal to or less than "0.7 X 10~6", and the score "bad" is given when the difference exceeds "0.7 X 10~6". The measurement of an average linear expansion coefficient is performed by a total expansion measurement method (temperature elevation speed: 10°C/min) using a thermal mechanical analysis device TMA-60 made by Shimadzu Corp, wherein a silicon monocrystalline member having a length of 20mm is used as a reference specimen.
[0128] (5) Evaluation aspect 5 (presence or non-presence of crystallization)
In step of preparing a semiconductor device (pn diode) by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 1, the score "good" is given when the vitrification without causing crystallization is possible, and the score "bad" is given when the vitrification is not possible due to crystallization.
[0129] (6) Evaluation aspect 6 (presence or non-presence of generation of bubbles) A semiconductor device (pn diode) is manufactured by the same method as the method of manufacturing a semiconductor device of the embodiment 1, and it is observed whether or not bubbles are generated in the inside of the glass layer 124 (particularly, in the vicinity of a boundary surface between the glass layer 124 and the semiconductor base body) (preliminary evaluation). Further, a layer made of glass composition is formed by applying by coating the glass composition according to the examples 1 to 11 and the comparison examples 1 to 6 on the semiconductor base body having a size of 10 mm square, and the layer made of glass composition is baked thus forming the glass layer. Then, it is observed whether or not bubbles are generated in the inside of the glass layer (particularly, in the vicinity of the boundary surface between the glass layer and the semiconductor base body) (subsequent evaluation).
[0130]
Fig. 6(a) and Fig. 6(b) are views for explaining bubbles b generated in the inside of the glass layer 124 in the preliminary evaluation. Fig. 6(a) is a cross-sectional view of a semiconductor device when the bubbles b are not generated, while Fig. 6(b) is a cross-sectional view of a semiconductor device when the bubbles b are generated. Fig. 7(a) and 7(b) are photographs for explaining the bubbles b generated in the inside of the glass layer 124 in subsequent evaluation. Fig. 7(a) is a photograph showing a boundary surface between the semiconductor base body and the glass layer when the bubbles b are not generated in an enlarged manner, while Fig. 7(b) is a photograph showing a boundary surface between the semiconductor base body and the glass layer when the bubbles b are generated in an enlarged manner. As a result of the experiment, it is found that there is a favorable corresponding relationship between the result of the preliminary evaluation and the result of the subsequent evaluation of the present invention. In the subsequent evaluation, the score "good" is given when no bubble having a diameter of 50μπι or more is generated in the inside of the glass layer, the score "fair" is given when one to twenty bubbles having a diameter of 50μπι or more are generated in the inside of the glass layer, and the score "bad" is given when twenty one or more bubbles having a diameter of 50μπι or more are generated in the inside of the glass layer.
[0131]
Fig. 8 is a TEM photograph showing a cross section of a portion including a boundary between a semiconductor base body and a glass layer . As can be also found from Fig. 8, it is clearly confirmed that an insulation layer (layer thickness: approximately 20nm) is present between the semiconductor base body and the glass layer.
[0132] (7) Evaluation aspect 7 (presence or non-presence of addition of nickel oxide)
One of objects of the present invention lies in "to suppress the generation of bubbles which may be generated from a boundary surface between a semiconductor base body and the glass layer in step of forming the glass layer by baking a layer made of glass composition without adding a component having a defoaming action such as nickel oxide or with the addition of a small amount (for example, 2.0 mol% or less) of such a component having a defoaming action even when the component is added. Accordingly, the score "very good" is given when nickel oxide is not added, the score "good" is given when nickel oxide is added but an addition amount of nickel oxide is 2.0 mol% or less, and the score "bad" is given when the content of nickel oxide exceeds 2.0 mol%.
[0133] (8) Evaluation aspect 8 (reverse direction leak current) A semiconductor device (pn diode) is prepared in the same manner as the method of manufacturing a semiconductor device of the embodiment 1, and a reverse direction leak current of the prepared semiconductor device is measured. Fig. 9 is a view showing reverse direction leak currents in the examples. In Fig. 9, Fig. 9(a) is a view showing a reverse direction leak current in the example 1, and Fig. 9 (b) is a view showing a reverse direction leak current in the comparison example 5. As a result of the evaluation, the score "good" is given when a reverse direction leak current is ΙμΑ or less when a reverse direction voltage VR of 600V is applied, and the score "bad" is given when the reverse direction leak current IR exceeds ΙμΑ when the reverse direction voltage VR of 600V is applied.
[0134] (9) Evaluation aspect 9 (high-temperature reverse bias resistance) A resin-sealed-type semiconductor device is formed by molding a semiconductor device which is prepared by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 1. The resin-sealed-type semiconductor device is subjected to a high-temperature reverse bias resistance test, and the high-temperature reverse bias resistance is measured. The high-temperature reverse bias resistance test is performed such that a specimen is put into a constant-temperature bath/high temperature bias tester where a temperature condition is set to 175°C, and a reverse direction current is measured for every 5 minutes over 20 hours in a state where a potential of 600V is applied between an anode electrode and a cathode electrode.
[0135]
Fig. 10 is a view showing a result of the high temperature reverse bias test. In Fig. 10, a solid line indicates a reverse direction leak current with respect to a specimen prepared using the glass composition of the example 1, and a broken line indicates a reverse direction leak current with respect to a specimen prepared using the glass composition of the comparison example 1. As shown in Fig. 10, it is found that with respect to the specimen prepared using the glass composition of the comparison example 1, a reverse direction leak current is increased immediately after the high temperature reverse bias test is started along with the temperature elevation, the reverse direction leak current is further increased thereafter with time, and reaches a predetermined reverse direction leak current value after the lapse of 3 hours from starting the high temperature reverse bias test so that the high temperature reverse bias test was stopped. To the contrary, it is found that with respect to the specimen prepared using the glass composition of the example 1, although a reverse direction leak current is increased immediately after the high temperature reverse bias test is started along with the temperature elevation, the reverse direction leak current is hardly increased after such increase of the reverse direction leak current. The score "good" is given when a reverse direction leak current is increased immediately after the high temperature reverse bias test is started along with the temperature elevation but the reverse direction leak current is hardly increased after such increase of the reverse direction leak current, and the score "bad" is given when a reverse direction leak current is increased immediately after the high temperature reverse bias test is started along with the temperature elevation, and the reverse direction leak current is further increased thereafter with time.
[0136] (10) Evaluation aspect 10 (presence or non-presence of diffusion of B from glass layer) A glass composition layer is formed on a surface of an 14 —3 n-type silicon substrate (impurity concentration: 2.0x10 cm ) by an electrophoresis method and, thereafter, a glass layer is formed by baking the glass composition layer at a temperature of 800°C in a wet oxygen atmosphere. As the glass composition, the glass composition of the example 1 and the glass composition of the comparison example 6 are used. Then, a surface of the n-type silicon substrate is exposed by removing the glass layer using fluorine. Thereafter, the SRP (Spreading Resistance Profiler) distribution is measured using a spreading resistance measurement device (SSM2000 made by Japan SSM Co; Ltd.) in the depth direction from a surface of the n-type silicon substrate, and impurity concentration is calculated based on obtained spreading resistance.
[0137]
Fig. 11 is a view showing the distribution of impurity concentration in the depth direction from a surface of a silicon substrate. In Fig. 11, a solid line indicates the distribution of impurity concentration with respect to a specimen prepared using the glass composition of the example 1, and a broken line indicates the distribution of impurity concentration with respect to a specimen prepared using the glass composition of the comparison example 6. As shown in Fig. 11, it is found that, in the specimen prepared using the glass composition of the comparison example 6, a p-type impurity layer having a depth of lOnm is formed on a surface of the silicon substrate. This implies that, in the glass composition which contains both B (boron) and alkaline metal, B (boron) diffuses into the silicon substrate from the glass layer during baking of the glass composition. To the contrary, it is found that, in the specimen prepared using the glass composition of the example 1, a p-type impurity layer is not formed on the surface of the silicon substrate. This implies that, in the glass composition which contains no alkaline metal, even when the glass composition contains B(boron), B(boron) is not diffused into the silicon substrate from the glass layer during baking of the glass composition. Accordingly, the score "good" is given when the glass composition is the glass composition which contains B(boron) but does not allow B(boron) to be diffused into the silicon substrate from the glass layer during baking of the glass composition, and the score "bad" is given when the glass composition is the glass composition where B(boron) is diffused into the silicon substrate from the glass layer during baking of the glass composition.
[0138] (10) Comprehensive evaluation
The score "good" is given when "fair" or "bad" is given with respect to none of the above-mentioned evaluation aspects 1 to 10, and the score "bad" is given when "fair" or "bad" is given with respect to at least one of the above-mentioned evaluation aspects 1 to 10.
[0139] 3. Result of evaluation
As can be found from Fig. 5, the score "bad" is given to all comparison examples 1 to 6 with respect to any one of the evaluation aspects so that the comprehensive evaluation of "bad" is given to all of the comparison examples 1 to 6. That is, score "bad" is given to the comparison example 1 with respect to the evaluation aspects 1, 9. The score "bad" is given to the comparison example 2 with respect to the evaluation aspect 3. The score "bad" is given to the comparison example 3 with respect to the evaluation aspect 6. The score "bad" is given to the comparison example 4 with respect to the evaluation aspects 5, 7. The score "bad" is given to the comparison example 5 with respect to the evaluation aspect 8. The score "bad" is given to the comparison example 6 with respect to the evaluation aspects 8, 10.
[0140]
To the contrary, the score "good" is given to the example 1 with respect to all evaluation aspects (evaluation aspects 1 to 10), and the score "good" or "very good" is given to the examples 2 to 11 with respect to the evaluation aspects 1 to 9. As a result, it is found that all of the methods of manufacturing a semiconductor device of the examples 1 to 11 are methods of manufacturing a semiconductor device which can manufacture a semiconductor device capable of satisfying all of the following conditions (a) to (d) using glass materials containing no lead, that is, the condition (a) that the glass material can be baked at a proper temperature (900°C or below, for example), the condition (b) that the glass material can withstand chemicals used in steps, the condition (c) that the glass material has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly, an average linear expansion coefficient at a temperature of 50°C to 550°C being close to a linear expansion coefficient of silicon at a temperature of 50°C to 550°C) , and the condition (d) that the glass material has excellent insulation property.
It is found that all of the methods of manufacturing a semiconductor device according to the examples 1 to 11 are methods of manufacturing a semiconductor device which can manufacture a semiconductor device capable of also satisfying the following conditions (e) to (i) using glass materials containing no lead, that is, the condition (e) that the glass material is not crystallized in vitrification step, the condition (f) that the occurrence of a state where a reverse direction breakdown strength characteristic of the semiconductor device is deteriorated is suppressed by suppressing the generation of bubbles which may be generated from a boundary surface between a semiconductor base body and the glass layer in step of forming the glass layer by baking "a layer made of glass composition" formed by an electrophoresis method, the condition (g) that an addition amount of NiO (nickel oxide) can be suppressed to 2.Omol% or less as a result of the suppression of the deterioration of a reverse direction breakdown strength characteristic of the semiconductor device, the condition (h) that a reverse direction leak current is low, and the condition (i) that the glass material has high high-temperature reverse bias resistance.
[0141]
As shown in Fig. 9(b), although the semiconductor device manufactured by the method of manufacturing a semiconductor device of the comparison example 5 exhibits a higher reverse direction current than the semiconductor device manufactured by the method of manufacturing a semiconductor device of the example 1, the semiconductor device manufactured by the method of manufacturing a semiconductor device of the comparison example 5 exhibits a reverse direction current of approximately 4.ΟμΑ when a reverse direction voltage VR of 600V is applied and hence, the semiconductor device manufactured by the method of manufacturing a semiconductor device of the comparison example 5 is at a sufficiently usable level depending on usage.
[0142]
Although the method of manufacturing a semiconductor device and such a semiconductor device according to the present invention have been explained heretofore in conjunction with the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and various modifications of the present invention can be carried out including the following modifications, for example, without departing from the gist of the present invention.
[0143] (1) In the above-mentioned respective embodiments, the glass layer is formed using the glass composition for protecting a semiconductor junction described in the embodiment 1. However, the present invention is not limited to such a case. The glass layer may be formed using the glass composition for protecting a semiconductor junction containing no NiO (nickel oxide) .
[0144] (2) In the above-mentioned respective embodiments, the glass layer is formed by an electrophoresis method. However, the present invention is not limited to such a case. For example, the glass layer may be formed by a spin coating method, a screen printing method or other glass layer forming methods.
[0145] (3) In the above-mentioned respective embodiments, the glass layer is formed by an electrophoresis method while setting a thickness of the insulation layer within a range of 5nm to 60nm. However, the present invention is not limited to such a case. For example, the glass layer may be formed by a spin coating method, a screen printing method or other glass layer forming methods while setting a thickness of the insulation layer within a range of 5nm to lOOnm. In this case, when a thickness of the insulation layer is less than 5nm, there exists a possibility that a reverse direction current reduction effect cannot be obtained. On the other hand, when a thickness of the insulation layer exceeds lOOnm, there exists a possibility that a layer made of the high-quality glass composition cannot be formed by a spin coating method, a screen printing method or other glass layer forming methods in the next glass layer forming step.
[0146] (4) In the above-mentioned respective embodiments, an insulation layer formed of a silicon oxide film is formed by a thermal oxidation method which uses dry oxygen (Dry 02). However, the present invention is not limited to such a case. For example, an insulation layer formed of a silicon oxide film may be formed by a thermal oxidation method which uses dry oxygen and nitrogen (DryCq + N2) . An insulation layer formed of a silicon oxide film may be formed by a thermal oxidation method which uses wet oxygen (Wet02). An insulation layer formed of a silicon oxide film may be formed by a thermal oxidation method which uses wet oxygen and nitrogen (Wet02 + N2) ) . An insulation layer formed of a silicon oxide film may be formed by a CVD method. Further, an insulation layer formed of a film other than a silicon oxide film (for example, an insulation layer formed of a silicon nitride film) may be formed.
[0147] (5) In the above-mentioned respective embodiments, the present invention has been explained by taking a diode (mesa-type pn diode, planar-type pn diode) as an example. However, the present invention is not limited to such a case. The present invention is also applicable to any kinds of semiconductor devices where a pn junction is exposed (for example, a thyristor, a power MOSFET, an IGBT and the like).
[0148] (6) In the above-mentioned respective embodiments, a substrate made of silicon is used as the semiconductor substrate. However, the present invention is not limited to such a case. For example, a semiconductor substrate such as an SiC substrate, a GaN substrate or a GaO substrate can be also used.
[0149] (7) In the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, it is desirable to use the glass composition which is hardly crystallized in step of baking the glass composition layer. With the use of such glass composition, a semiconductor device having a low reverse direction leak current can be manufactured in a stable manner. In this respect, the present invention differs from the technique disclosed in JP-A-63-117929 where the glass composition is transformed into a glass ceramic body having high crystallinity in step of baking a glass layer.
[0150] (8) In the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, it is desirable to use a raw material which substantially contains no Bi. With the use of such a raw material, the crystallization of the glass layer hardly occurs in step of baking the glass composition layer and hence, a semiconductor device having a low reverse direction leak current can be manufactured in a stable manner. In this respect, the present invention differs from the technique disclosed in JP-A-2005-525287 where a raw material which contains Bi is used.
[0151] (9) In the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, it is desirable to use a raw material which substantially contains no Cu. With the use of such a raw material, the crystallization of the glass layer hardly occurs in step of baking the glass composition layer. Also in this case, a semiconductor device having a low reverse direction leak current can be manufactured in a stable manner. In this respect, the present invention differs from the technique disclosed in JP-A-2001-287984 where a raw material which contains Cu is used.
[0152] (10) In the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, a raw material which substantially contains neither Li nor Pb is used. In this respect, the present invention differs from the technique disclosed in JP-A-2002-16272 where a raw material which contains Li and Pb is used.
[0153] (11) In JP-A-53-36463, there is disclosed a technique where zinc-based glass (glass containing a largest amount of zinc oxide) is used as a glass layer for passivation. However, zinc-based glass exhibits low chemical resistance (see the comparison example 2 in the above-mentioned examples) and hence, the zinc-based glass cannot be handily used in the method of manufacturing a semiconductor device and the semiconductor device according to the present invention.
[0154] (12) In the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, it is desirable to use a raw material which substantially contains no P. With the use of such a raw material, it is possible to prevent the diffusion of phosphorus (P) into the semiconductor base body from the glass layer in step of baking the glass composition layer and hence, a highly reliable semiconductor device can be manufactured.
Explanation of Symbols [0155] 100, 200, 900: semiconductor device, 110, 910: n~ type semiconductor substrate, 112, 912: p+ type diffusion layer, 114, 914: n~ type diffusion layer, 116, 118, 916, 918: oxide film, 120, 920: trench, 121, 218: insulation layer, 124, 220, 924: glass layer, 126, 926: photoresist, 130, 930: portion where Ni plating electrode film is to be formed, 132, 932: roughened surface region, 134, 934: anode electrode, 136, 936: cathode electrode, 210: n+ type semiconductor substrate, 212: n~ type epitaxial layer, 214 : p+ type diffusion layer, 216 : n+ type diffusion layer, 222: anode electrode layer, 224: cathode electrode layer, b: bubbles
Claims (20)
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| JP2012061779 | 2012-05-08 | ||
| PCT/JP2012/061779 WO2012160961A1 (en) | 2011-05-23 | 2012-05-08 | Semiconductor device production method and semiconductor device |
| PCT/JP2012/080795 WO2013168314A1 (en) | 2012-05-08 | 2012-11-28 | Semiconductor device production method and semiconductor device |
| JP2012080795 | 2012-11-28 |
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| JPWO2013168521A1 (en) * | 2012-05-08 | 2016-01-07 | 新電元工業株式会社 | Resin-sealed semiconductor device and manufacturing method thereof |
| JP6588028B2 (en) * | 2014-10-31 | 2019-10-09 | 新電元工業株式会社 | Semiconductor device manufacturing method and resist glass |
| JP6029771B2 (en) * | 2014-11-13 | 2016-11-24 | 新電元工業株式会社 | Semiconductor device manufacturing method and glass film forming apparatus |
| WO2017134808A1 (en) * | 2016-02-05 | 2017-08-10 | 新電元工業株式会社 | Method for producing semiconductor device |
| WO2018096643A1 (en) * | 2016-11-25 | 2018-05-31 | 新電元工業株式会社 | Semiconductor device production method, and semiconductor device |
| JP6295378B1 (en) * | 2016-11-25 | 2018-03-14 | 新電元工業株式会社 | Manufacturing method of semiconductor device |
| JP6396598B1 (en) * | 2017-04-19 | 2018-09-26 | 新電元工業株式会社 | Manufacturing method of semiconductor device |
| FR3079662B1 (en) * | 2018-03-30 | 2020-02-28 | Soitec | SUBSTRATE FOR RADIO FREQUENCY APPLICATIONS AND MANUFACTURING METHOD THEREOF |
| JP7461210B2 (en) | 2020-05-14 | 2024-04-03 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
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| JPS57202742A (en) * | 1981-06-09 | 1982-12-11 | Toshiba Corp | Glass for semiconductor coating |
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