MXPA00012437A - Method and apparatus for d.c. offset correction in digital-to-analog converters - Google Patents

Abstract

A method and apparatus for adaptively correcting D.C. offset errors imposed upon signals in a communication device. The invention includes a feedback loop correction circuit (122) and method for measuring and reducing D.C. offset errors imposed upon analog transmission signals by transmit digital-to-analog converters (DACs) (102) and associated analog reconstruction filters. A digital feedback loop is used toremove D.C. offset errors from the analog transmission signals prior to transmission. In one embodiment, the digital feedback loop includes a pair of analog-to-digital converters, a digital D.C. offset correction circuit (222), and a pair of adders (228, 230). The transmission signals are digitized, filtered, and digitally processsed by correction circuit (222) to generate offset correction signals that are equal to undesired D.C. offset error present in the transmission signals. The correction signals are added to digital input baseband signals thereby removing undesirable D.C. offset errors from transmission signals.

Description

METHOD AND APPARATUS FOR THE CORRECTION OF DIRECT CURRENT COMPENSATION IN CONVERTERS FROM DIGITAL TO ANALOG Field of the Invention The present invention relates to digital-to-analog converters, and more particularly to the correction of the offset error of C.D. in converters from digital to analog.

Antecedents of the Invention. The digital to analogous converters that we generally refer to as "DACs" or "D-a-A-" converters, are used to translate information from the digital field to the analog field. DACs generally transform digital signals to a range of analogous values. The DACs represent a limited number of different digital input codes by a corresponding number of separate analog output values. Examples of input code formats accommodated by existing DACs include simple binaries, two-binary binaries, and binary-coded decimals. A number of techniques for the implementation of digital to analog converters are well known in the art. Digital to analog converters are used in a wide variety of applications including wireless digital communication. For example, DACs are used in wireless digital cellular phones to convert digital speech signals into "baseband" analog signals (eg, signals that have frequencies close to C.D). Figures 1 a and 1 b illustrate a block diagram of an exemplary wireless digital cellular telephone 900 that uses the DACs to convert the digitally encoded speech signals into filtered baseband analog signals. The 900 cell phone is manufactured in accordance with the TIA specification entitled "mobile station station compatibility standard for the dual-mode broadband cellular base system" Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Sprectrum Cellular System, TIA / EIA / IS-95-A, published in May 1995 by the Telecommunications Industry Association, which will be referred to below as "the IS-95 specification". As illustrated in Figures 1 a and 1 b, the example digital cell phone 900 comprises mainly a user interface section 916, a specific application integrated circuit (ASIC) 914, the mobile station modem (MSM), an analog baseband ASIC 912, reception and transmission amplifiers 902 and 904 respectively, an upconverter 918, a power amplifier and a transmitter 920, an antenna 906, a duplexer 908, and a low noise amplifier (LNA) and a 910 mixer circuit.

The cellular phone 900, and its component parts are described in greater detail in commonly assigned U.S. Patent Application No. 08/789/108, filed January 27, 1997, entitled "High Variable Gain Dynamic Range Amplifier", which is incorporated herein by reference. To understand the present invention, an understanding of the function and operation of many of the cell phone components 900 is not necessary and therefore not described in the present description. However, a brief description of the MSM 914, and the analogous baseband ASIC 912, is useful for understanding an example application and an operating environment of the present invention. The MSM 914 performs a variety of functions for the 900 cell phone including voice coding, coding, interleaving, data modulation, broadcast and filtering. For example, when the information is transmitted from the telephone 900 to the base station CDMA ("reverse link" transmission), the voice information is first encoded by the voice encoder 950 and transferred to the modulator interleaver circuit 952 where the data they are coded, interleaved, modulated and disseminated and filtered. The digitized and modulated data are supplied to a pair of DACs 954 and 956 in the analog baseband ASIC 912 (Figure 1) for further processing. MSM 914, produces a digital representation of the modulated baseband of the CDMA waveform to the DACs 954 and 956 in the analog baseband ASIC 912. The frequency range of the digital signals of the baseband is between CD (or OHz) and approximately 630 kHz. The analog baseband ASIC 912 (largely due to the operation of the DACs 954, 956) converts the digital modulated data received from the MSM 914 into analog baseband signals. Analog baseband ASIC 912 filters the analog baseband signals generated by the DACs 954, 956 and "up-converts" the filtered signals into a similar intermediate frequency (IF) signal. The signal I F is supplied to the automatic transmission gain control (AGC) amplifier 904, and further processed for eventual transmission to the wireless base station. A better understanding of the operation of DACs 954, 956 can be obtained by describing the analogous ASIC 912 baseband transmission section in more detail. One embodiment of the transmission section 100 of the baseband ASIC 912 of Figure 1 b is illustrated in Figure 2. As illustrated in Figure 2, the transmission section mainly comprises a pair of transmission DACs. 102 (each for the digital modulated signals of the baseband in phase (I) and the modulated digital signals of the quadrature-phase baseband (Q), a pair of CDMA filters 104, 106, and an upconverter transmission circuit 108. Which preferably uses the well-known quadrature modulation scheme to convert upwardly to the IF frequency in the CDMA path of the transmission section 100 illustrated in Figure 2. Therefore, two DACs are needed to perform the digital-to-analogue conversion of the digital baseband signals received from the MSM ASIC 914. The IDAC 1 10 converts the received digital signals into the baseband phase, as a signal it is analogous in phase of the baseband. In a similar way, QDAC 1 12 converts the quadrature-phase digital signals received from the baseband into analog quadrature-phase baseband signals. In the embodiment illustrated in Figure 2, the transmission DACs 102 has differential outputs to reduce the damaging effects caused by external noise that can be generated elsewhere in the ASIC 912 analog baseband. The CDMA filters of the I channel and Q 104, 106 remove the unwanted noise that is generated by the DACs 1 10 and 1 12 respectively. The CDMA filters 104, 106 comprise anti-alias filters which perform a smoothing function on the analog baseband signals generated with the transmission DACs 102 thereby removing any high frequency components introduced by the DACs 102. Similar to the transmission DACs 102, the CDMA filters 104, 106 have differential outputs as illustrated in Figure 2. The outputs of the CDMA filters 104, 106 are inputs for the transmission up converter 108 which converts baseband to analog signals at an IF frequency for further processing, and eventual transmission to the CDMA base station.

In a disadvantageous manner, the transmission section 100 illustrated in Figure 2 introduces errors which are manifested as aggregate CD compensations (referred to hereafter as "induced compensation errors"), in the transmission signals of interest before the signals are produced for the rest of the cell phone's circuit system. In particular, referring again to Figure 2, the induced compensation errors can be imposed on the transmission signals by the transmission DACs and by the active components in the CDMA filters 104, 106. Because the CDMA 104 filters, 106 can be relatively complex for induced compensation errors can be significant. In a disadvantageous manner, the compensation errors introduced in the signal path, and specifically in the input of the mixers 1 14, 1 16 can cause a signal of the conveyor to appear in the IF signal generated in the outputs of the upstream converter circuit Transmission 108. To comply with certain carrier suppression specifications, it is necessary to reduce or eliminate compensation errors introduced by transmission section 100. Unfortunately, induced compensation errors have proven to be difficult to eliminate in the past. Because the magnitude of offsets varies widely depending on the operating characteristics (eg, voltage, temperature, etc.) of the ASIC 912 analog baseband, errors have proven to be difficult to eliminate. Therefore, there is a need for a method and apparatus which can reduce or eliminate the CD offset errors that appear at the input of the transmission mixers 1 14, 1 16. A prior art method for reducing the CD offsets it is illustrated in Figure 3. The prior art uses correction circuits for C.D. based on fuses 120 to reduce the errors produced in the output of the CDMA filters 104, 106. The error correction circuit 120 mainly comprises a series of fuses, and a relatively small DAC which has the ability to add an error setting to the signals at the input of the mixers 1 14, 1 16. The error correction circuit allows the designers to measure the CD compensation in the output of the filters under selected nominal conditions. Using the well-known techniques of fine adjustment fuses by trimming, the fuses in the correction circuit 120 are burned until the errors are reduced to zero under the selected nominal conditions. In a disadvantageous way, this technique produces a static error correction solution once the fuses have been burned, the errors can not be corrected under the variable operating conditions of the ASIC 912. For example, as the voltage and temperature vary of the ASIC 912 over time CD compensations would be introduced despite the static adjustments of the correction circuits 120. The apparatuses that on occasion could be used under nominal conditions in which the fuses were blown have become unusual under some operating environments, thereby adversely affecting the production characteristics of the analogous baseband as well ASIC 912. Furthermore, the prior art method shown in Figure 3, disadvantageously introduces an additional step of manufacturing and testing in the manufacture of the ASIC 912 using the prior art method of Figure 3, the The ASIC 912 should measure the compensation errors, adjust the fuses to eliminate compensation errors, and test the results to ensure that the fuses have been adjusted by the cutouts in an appropriate manner. This process adds additional time to the manufacture of the ASIC 912 and consequently adds costs to its manufacture. Thus, an improved method and apparatus for correction of the compensation error C.D. is required, which does not require the use of fuses, or the fine-tuning technique of trimming the fuses. In addition, a method and apparatus for error correction is needed which dynamically monitors and corrects the errors introduced by the transmission section 100 under all operating conditions under which ASIC 912 must operate. Another technique for the reduction of CD compensation errors It is illustrated in Figure 4. As illustrated in Figure 4, an analog circuit of the feedback circuit 122 was used to measure and suppress the DC compensation errors produced at the output of the filters. CDMA 104, 106. Analog feedback circuit 122 includes analog filters that distinguish CD offset errors of the analog signals of interest. The feedback loop also includes integrators placed to integrate the compensation errors of C. D. in the integration capacitors. By correctly selecting the gains of the integrators, the integrators generate cancellation CD signals, which are nominally equal, to the unwanted CD errors introduced in the signal path by the CDMA filters and the transmission DACs 102. The cancellation signals CDs are added to the analog signals generated by the transmission DACs 102 thereby eliminating the unwanted feeding through the CD. A more detailed description of this prior art method (in the concept of a received RF signal path) is provided with reference to Figures 9 and 10 of US Patent No. 5,617,060, issued April 1, 1997 to Wilson and Associated and assigned to the owner of the present invention which is incorporated herein by reference. In a disadvantageous manner, the analog feedback circuit has proven to be very difficult to implement in an ASIC device. Analogous signals of interest generated at the outputs of the CDMA filters 104, 106 have levels which are very close to the C.D. Therefore, the frequency of the corner of the filters used to differentiate the compensation errors of C. D. from the signals of interest must be very low. Because the frequency of the corner (Wp0? 0) is proportional, the transductance (gm) divided by the capacitance (C), and the transductance gm must be restricted to be very small or alternatively, the value of C must be done to be relatively large. Unfortunately, the value of gm is very difficult to control and there is a limit to how small the transmutation can be. In addition, the physical and cost constraints limit how large the value of C can be made in an integrated circuit environment (large capacitors occupy large areas of an integrated circuit and therefore increase the costs of the integrated circuit). A possible solution is to increase C using a component used outside the integrated circuit, however this method creates current leaks in the circuit board which are not desirable. Therefore, it is desirable to provide a CD correction method and apparatus in which it is easily implemented in an integrated circuit, and which does not require the use of fine fuse trimming, and which can be monitored in a manner dynamic and flexible and correct CD offsets as they are introduced. The present invention provides said method and apparatus for the correction of C. D.

Summary of the Invention. The present invention is a new method and apparatus for adaptively correcting compensation errors C.D. taxes on communication signals in a communication device. The present invention includes a correction circuit of the feedback circuit and a method for measuring and suppressing the CD compensation errors imposed on the analog radio frequency transmission signals by the digital-to-analogue transmission converters (DACs) and the filters associated reconstruction analogs. In accordance with the present invention, a negative feedback digital circuit is used to remove the compensation errors of C.D. of the analog transmission signals before transmission. In the preferred mode, the digital feedback circuit includes a pair of analog-to-digital converters (each for in-phase (I) channels, and (Q) quadrature-phase), a digital offset correction circuit of CD, and a couple of aggregators. Each of the analog-to-digital converters is placed in the output of an associated reconstruction filter. The analog transmission signals are digitized, filtered and digitally processed by the correction circuit to generate compensation correction signals for both channels I and Q channels. The compensation correction signals are nominally equal to compensation errors of unwanted CDs entered into the signal path or the transmission DACs, and the reconstruction filters. The compensation correction signals are added to the input of the digital signals of the baseband before the conversion from digital to analog, thereby removing the undesirable C.D compensation errors of the transmission signals. In a preferred embodiment, the analog-to-digital converters comprise differential comparators of a bit that generate digital signals representative of the signals of the outputs of analog transmission signals by the reconstruction filters. The digital compensation correction device of C.D. process the output of digital signals by differential comparators using a selected digital signal processing technique. In one embodiment, the compensation correction circuit uses a digital signal processing technique "signal bite" by means of which the signal bits generated by the differential comparators are integrated in a continuous manner. In this embodiment, the compensation circuit comprises an integrator of channel I and an integrator of channel Q placed to integrate the analog transmission signals. In another embodiment, the integrators comprise binary ascending / descending counters. The sign of the analog transmission signals controls the direction (increase or decrease) of the counters. After counting a predetermined time interval, the counters contain negative values (due to the negative feedback loop circuit) whose absolute value is nominally equal to the compensation errors of C. D. imposed on the transmission signals. The counter values are added continuously to the digital signals of the baseband to compensate for CD offset errors. The preferred embodiment of the present invention uses the sign characteristics of both digital baseband signals and the outputs. of transmission signals associated by the reconstruction filters to produce the feedback compensation correction signals. The preferred technique forces the transmission output signals by means of the reconstruction filters to have statistical characteristics very similar to those of the digital signals of the baseband. According to this technique, the integrators are positioned to measure the time delays at the elevation end defined as the time delay between the elevation end of the baseband signal, and the elevation end of its associated filtered signal. In a similar manner, the delay of the descending time end defined as the time delay between the descending end of the baseband signal and the descending end of its associated filtered signal is also measured. These "zero crossing" time delays are measured by analyzing the relative signs of the digital input signals and the filtered signals. The sign of the digital input signal is obtained from the most significant bit (MSB) of the baseband signal. The sign of the filtered signal is obtained from the output of the analog to digital converter, which in the preferred embodiment comprises a differential comparator of a bite. Cutters are used to count a period of time that approaches time delays of zero crossings. Zero-crossing time delays are used by the present invention to calculate the compensation errors of C. D. present in the transmission signals.

Brief Description of the Drawings. The characteristics, objects and advantages of the present invention can be appreciated from the reading of the following detailed description of the invention set forth below when taken in conjunction with the drawings in which the similar reference characters identify the corresponding characters and wherein: FIGS. 1 a and 1 b illustrate a block diagram of an exemplary wireless digital cellular telephone, which uses digital-to-analog converters to digitally convert encoded speech signals into analog baseband filtered signals. Figure 2 is a block diagram of the transmission section of the analog baseband ASIC illustrated in Figure 1 b. Figure 3 illustrates a prior art method for reducing the induced compensation errors, produced in the output of the CDMA filters of Figure 2 using, a compensation error correction circuit of C. D. "based on fuses". Figure 4 illustrates another method of the prior art for reducing the induced compensation errors produced in the output of the CDMA filters of Figure 2, using an analog circuit of CD compensation error correction. Figure 5 illustrates a block diagram of the preferred embodiment of the present invention that includes a digital CD compensation error correction circuit. FIG. 6 illustrates a simplified block diagram of an alternative embodiment of the present invention by means of which compensation correction signals are generated. using a digital signal processing technique of a bite sign. Figure 7 illustrates an example of the signals processed by the CD compensation error correction circuit of Figure 5. Figure 8 illustrates a simplified block diagram of the preferred embodiment of the present invention by means of which Compensation correction signals are generated using a digital MSB signal processing technique. Figure 9 illustrates a representation of an exemplary CDMA signal before and after filtering. Figure 10 illustrates an example of a digitized signal that is produced by a comparator of Figure 5, when a digital signal processing technique of a bite sign is used to correct the compensation errors of C. D. present in the signal. Figure 1 1 shows an example of a digitized signal that is produced by a comparator of Figure 5, when a digital signal processing technique MSB is used to correct the compensation errors of C.D. present in the signal.

Detailed Description of the Invention. Throughout that description, the preferred embodiments and the illustrated examples should be considered as examples rather than limitations of the present invention. In Figure 5 a block diagram of the preferred embodiment of the present invention is illustrated. As illustrated in Figure 5, the present invention includes the transmission DACs 102, the CDMA filters 104 and 106, and the transmission upconverters 108. The transmission DACs 102, the CDMA filters 104, 106 and the converter Transmission Upstream 108 all function as described above with reference to Figures 2 through 4. As illustrated in Figure 5, a CD compensation correction circuit of the digital feedback circuit 222 has been exchanged for a correction circuit of the prior art feedback circuit 122, described above with reference to Figure 4. The correction circuit 222 includes inputs that are operatively connected to the outputs of a pair of analog-to-digital converters I and Q 224, 226 respectively, by the signal lines 242, 244 respectively, as illustrated in Figure 5. The outputs of the correction circuit 222 are connected to a first output of a pair of channel I and Q aggregators 228, 230 respectively, as illustrated in Figure 5. As described above with reference to Figures 2 through 4, the CDMA filters 104 and 106 smooth the transmitted signals that are produced by the transmission DACs 102 and therefore, they remove undesired high frequency components, and the caunting noise from the transmission signals introduced by the transmission DACs 102. One embodiment of the present invention uses the well-known quadrature modulation scheme for the transmission of signals up to the intermediate frequency (I F). The induced compensation errors are created by the operation of the DACs 1 12 transmission, and by the active components of the CDMA filters 104 and 106. The errors of DC compensation present in the input of the mixers 1 14, 1 16, can lead to the appearance of carrier signals in the IF signal generated at the output of the uplink converter circuit 108. The preferred embodiment of the present invention illustrated in Figure 5 uses a new technique to reduce the induced compensation errors present in the input of the mixers 1 14, 1 16. The compensating correction circuit of CD222 removes or reduces the compensation errors induced in order to be in accordance with certain criteria of suppression of the conveyor. The operation and functions of the offset correction circuit of C.D. will now be described in greater detail. of the digital feedback circuit 222, and its related circuit system. The outputs of analog transmission signals of the CDMA filters 104, 106 are digitized by the digital analogue converters 224, 226 respectively, and are provided as digital inputs to the correction circuit 222 by the signal lines 242, 244 respectively. In the preferred embodiment, analog-to-digital converters 224, 226 comprise 1-bit differential comparators. Although alternative implementations of the converters 224, 226 may be used to practice the present invention, and are within the scope of the present invention, the 1-bit differential comparators are preferred because they are very simple to implement and because they introduce offsets of CD very small in the error correction circuit. The 1-bit comparators adequately represent the dynamics of the CDMA signal outputs of the CDMA 104, 106 filters. The CDMA signals are essentially symmetric in nature (essentially filtered binary waveforms) and therefore are good candidates to be used with 1-bit comparators. Accordingly, due to the inherent characteristics of the CDMA signals very little low frequency quantization noise is introduced by means of the comparators 224, 226. Therefore, the comparators 224, 226 produce sufficient information about the transmission signals for makes it possible for the feedback loop of the CD Measure and correct the compensation errors of C. D. present in the transmission signals. The outputs of the comparators 224, 226, comprise digital representations of the signs of the transmission signals. For example, the comparator 224 generates a logical one if the filtered transmission signal I (filtered by the channel I of the CDMA filter 104) is positive (for example it has a positive sign), and generates a logical zero if the transmission signal I filtered is negative. Once converted to the digital field, the digital correction circuit C.D. 222 can use a variety of digital techniques to process signals. Two example techniques are described in greater detail with reference to Figures 6 and 8, however, those skilled in the art of digital signal processing will appreciate that various alternative means of digital processing can be used. For example, the correction circuit may alternatively use finite impulse response filters (FI R), infinite impulse response filters (I I R) or adapter filters using at least one average square algorithm. The correction circuit 222 processes the signal input by means of the signal lines 242, 244 using one of the digital processing techniques of the present invention, and generates the compensation correction signals for both channels (I) in phase and the (Q) quadrature-phase. The compensation correction signals I and Q are produced proportional to the first inputs of a pair of eight-bit aggregators 228, 230 by the signal lines 232, 234 respectively the compensation correction signals are added to the band signals digital base of the I and Q channels before being converted by the transmission DACs 1 10, 1 12. In the embodiment illustrated in Figure 5, the transmission DACs 102 include 9-bit analog-to-digital converters. In this embodiment the range of the transmission DACs 102 can be extended by a bit compared to the range of the transmission DACs 102 of the prior art (and described above with reference to Figure 4). The extension of the 1-bit range is necessary in some cases, and will depend on the characteristics of the signals. A 1-bit extension is required to allow both the 8-bit baseband signal and the 8-bit correction signal as illustrated in Figure 5. However, in alternative modes, the transmission DACs 102 may understand converters from digital to 8-bit analog, particularly when the baseband signal comprises a 7-bit or 7.5-bit signal. As illustrated in Figure 5, the compensating correction signal of channel I is added to the digital signal of the baseband of channel I by the aggregator I 228. The 9-bit output of the aggregator I 228 is produced as an entry to I DAC 1 10 of 9 bits. Similarly, the compensation correction signal Q is added to the digital signal of the baseband of channel Q by the aggregator Q 230. The 9-bit signal of the aggregator 230 Q is produced as an input to the QDAC 1 12 In this way, the signals of the baseband appearing on the input lines 238 (input I), and 240 (input Q) are essentially changed by the compensation correction signals appearing on the signal lines 232 ( compensation I) and 234 (compensation Q), respectively for the purpose of counteracting the effects of the CD compensation errors introduced by the CDMA filters of the I channel 104, and the CDMA filter of the Q channel 106, respectively. The present invention advantageously utilizes the same DACs 1 10, 12 both for the analog / digital conversion and for correction purposes of the compensation error. This "new use" of DAC advantageously reduces the number of circuit systems associated with compensation error correction. Thus, using the method and apparatus of the present invention, compensation error correction is performed at a very low cost and complexity compared to other methods using dedicated DACs for compensation error correction. In addition, because both signal conversion and compensation error correction processes use identical DACs, the present invention advantageously exhibits no problems associated with decoupling with any DACs. Next, two example techniques used to implement the digital correction circuit 222 will be described in more detail, with reference to Figures 6 through 8.

Signal Processing Digital Signal Technique of a Bite to Generate the Compensation Correction Signals. Figure 6 shows a simplified block diagram of an alternative embodiment of the present invention by means of which the compensation correction signals (compensation I and compensation Q) described above are generated with reference to Figure 5, using a digital technique signal processing "bite sign". In the illustrated alternative mode, the compensation correction circuit C.D. 222 of Figure 5 comprises a pair of integrators 246, 248. The integrators 246, 248 continuously integrate the digital representations of the signals of the transmission signals. More specifically, and referring consecutively to Figures 5 and 6, the integrator 246 integrates the digitized sign of the I channel transmission signals generated by the CDMA filter of the I channel 104. In a similar way, the integrator 248 integrates the signal digitized transmission signals of the Q channel generated by the CDMA filter of the Q channel 106. As described above with reference to Figure 5, because the filtered transmission signals (both I and Q channels), produced by the CDMA 104, 106 filters are CDMA signals, they must be substantially symmetric about the CD therefore, the digitized sign signals produced by the comparators of a bite 224, 226 (Figure 5) must comprise an equal number of logical ones that logical zeros. That is, in the absence of any induced compensation errors, the comparators must produce the same Number of ones as of zeros due to the symmetric nature of the CDMA signals. However, as described above, the induced compensation errors are present in the transmission signals and therefore the comparators 224, 226 generate a slightly inclined output (for example they produce slightly more zeros than ones or vice versa, depending on the sign of the change of CD). The integrators 246, 248 detect this inclination, and compensate it by subtracting (for example by adding the negative of the compensation error of C.D.), the compensation of the digital signals of the baseband before they are converted into analog signals. In one embodiment, the integrators 246, 248 may comprise ascending / descending binary counters. The production of logical values in the signal lines 242, 244 indicates the address of the account. For example, in one embodiment, if the digitized output of the comparator 224 represents a negative transmission signal I (eg, the comparator 224, produces a logical "0"), then a 0 will be the input to the counter 246 by means of the signal line 244 and counter 246 will therefore have instructions to count upward in the next clock cycle. In contrast, the digitized logic 1 is input to counter 246, the counter will count down in the next clock cycle. Any convenient clock can be used to program the counters 246, 248. However, due to the operation of the feedback circuit depends somewhat on the index of the clock signals used to regulate the counters 246, 248, the selected clock must have a frequency sufficient to cover the requirements of the system. In one embodiment, the counters are regulated using the signals of the I clock (ICLK), and the clock Q (QCLK) that are used to regulate the signals of the baseband. Alternatively, any clock signal that is not synchronized with the transmission signals may be used. In addition, multiple clock signals ICLK or QCLK can be used by dividing downwardly or multiplying the clock signals upwardly. If positive errors of induced compensation are present in the transmission signals, the comparators 224, 226 will produce more positive sign values (for example more ones) than negative sign values. Counters count down when they receive a logical one, and count down when they receive a logical zero. Accordingly, the integrators 246, 248 will count down more frequently than an ascending count if positive compensation errors are present in the transmission signals. Therefore, the counters will contain negative values representative of the C.D. these negative values are added to the baseband signal to compensate for the positive compensation of CD, so a positive compensation causes the meter outputs to decrease (for example, the counters are decreased), while an equal compensation causes increase the outputs of the counter (for example the counters are increased). Therefore, when positive compensation errors are detected, less is added to the input signals before conversion to the analog field. In contrast, when negative compensation errors are detected, more is added to the input signal to compensate for negative C.D. compensation errors. The integrator 248 operates in an identical manner as the integrator 246 and integrates the digitized transmission signals Q. The counter outputs are supplied in signal lines 234 (compensation I) and 234 (compensation Q) as described above with reference to Figure 5, the compensation correction signal of channel I (produced by integrator 246) is added to the band signal of the digital base of channel I. in a similar way, the compensation correction signal of the Q-channel (produced by the integrator 248) is added to the digital signal of the baseband of the Q-channel. In this way, the digital signals of the data band that appear in the input lines 238 (input I) and 240 (input Q), they are corrected by the outputs of their respective integrators, thus compensating the induced compensation errors. In one embodiment, the transformation version z of the integrators 246, 248 comprises integrators manufactured according to the following transformation equation Z: - (2 n) / 1-z "1.

Essentially the compensation circuit of C.D. 222 illustrated in Figure 6 is a digital analog, of an analog integrator circuit. In a disadvantageous manner, there are a few problems associated with the implementation of the compensation circuit of C. D.222 illustrated in Figure 6. First, the frequency of the corner must be restricted to be very low. In addition, the transmission signals must be integrated in a relatively long period of time. Accordingly, the meters used to implement the integrators 246, 248 must be relatively large. Because the feedback circuit of Figure 5 using the correction circuit of Figure 6 attempts to track the low frequency content of the input baseband signal in a non-linear manner, it will tend to distort and corrupting the CDMA signal close to CD therefore, an improved method and apparatus for generating the CD offset correction signals is desirable. and which is described below with reference to Figures 7 and 8.

Digital Signal Processing Technique MSB To Generate Compensation Correction Signals - the Preferred Modality of the Present Invention. The apparatus and the preferred method for generating the compensation signals of C.D. as described below with reference to Figures 7 and 8. Briefly, the preferred technique uses signal characteristics of the signal input of the data band in the signal lines 238 (input I) and 240 (input Q ) (Figure 5), and signal characteristics of the output of the associated transmission signals of the CDMA filters 104, 106 (and are digitized by the comparators 224, 226 respectively) to produce the feedback correction correction signals. The technique forces the transmission signals provided as inputs to the mixers 1 14, 1 16 to have statistical characteristics very similar to those of the digital signals of the baseband provided as inputs to the aggregators 228, 230. Figure 7 illustrates an example of the signals processed by the CD correction circuit of Figure 5. The signals shown in Figure 7 are simplified only for explanation purposes. As illustrated in Figure 7, an example signal that is an input for DACs 1 12 transmission (Figure 5), is illustrated as a sine wave. We refer to that signal as an "original" 400 signal (for example, the original signal is how the signal appears before it is filtered by the CDMA 104 or accented filters 106).

After being filtered by the CDMA filters (104 or accented 106), the original signal 400 is changed and delayed, as illustrated in Figure 7 as a filtered signal 402. The amplitude of the filtered signal 402 is changed by a CD compensation 404 that is introduced as described above, by CDMA filters 104, 106. The preferred embodiment of the present method and apparatus for CD compensation correction takes advantage of the observation that CD compensation 404 can be estimated by measuring the difference between the zero crossing time delays of the elevation end and the descending end of the original signal 400 and the filtered signal 402. The difference between the time delays of zero crossing of the elevation signal and the down signal is proportional to the CD offset error 404 imposed on the original signal 400. Therefore, by measuring the time delay between the elevation end of the original signal 400 and the filtered signal 402 (shown as a delay of the elevation end 406 in Figure 7), and between the downstream end of the filtered signal 402 and the original signal 400 (illustrated as a downstream signal delay 408 in Figure 7), the CD offset error can be measured and corrected subsequently. As described below in greater detail with reference to Figure 8, the time delays 406, 408 are measured by analyzing the relative signs of the original signal 400, and the filtered signal 402 in different instances of time.

For example, the zero crossing time delay of the lifting end 406 can be measured by starting the counter at a first moment of time when the original signal 400 changes the sign from negative to positive (for example the moment when the signal 400 crosses the zero at the elevation end), and subsequently stopping the counter at a second instant of time, when the filtered signal 402 changes the sign from negative to positive (eg, the instant when the signal 402 crosses the zero at the extreme of elevation). Similarly, the zero-crossing time delay of the descending end 408 can be measured by initiating the counter at a third instant of time when the filtered signal 402 changes the sign from positive to negative (for example, the time at which the signal 402 crosses the zero at the extreme descending), and subsequently terminating the counter at a fourth instant of time when the original signal 400 changes the sign from negative to positive (for example the instant when the signal 400 crosses the zero at the downstream end). The delay of the rising end 406 is shortened by a positive and prolonged C.D compensation by a negative C.D. offset (the delay 406 is prolonged in the example shown in Figure 7). In contrast, the delay of the descending end 408 is prolonged by a compensation of C.D. positive and shortened by a negative D.D. compensation (for example, the descending end of the filtered signal 402 will occur after that of the signal 400 as the compensation of C.D. is increased). the preferred correction technique. measures the difference between the zero crossing time delays to determine the compensation errors of C.D. present in the transmission signals. In the preferred embodiment of the present invention, the correction circuit of C.D. 222 of Figure 6 can be modified to take advantage of the observations described above with reference to Figure 7. In Figure 8, a simplified block diagram of the preferred embodiment of the present invention is illustrated. As illustrated in Figure 8, correction circuit 222 of Figure 6 has been modified to include a decision block of channel I 250 and a decision block of channel Q 252. Decision blocks 250, 252 , compare the signals of the input of the signals of the baseband in the lines of the signals 238, 240 (Figure 5), with the signs of the output of the signals transmitted by the CDMA filters 104, 106 respectively. Depending on the relative signs of the baseband and transmission signals, the decision blocks 250, 252, generate outputs to instruct the integrators 246, 248 to alternately become inactive, a count up or a count down. In one embodiment, the integrators 246, 248 may comprise ascending / descending binary counters. The decision blocks 250, 252 therefore implement the following compensation correction algorithm of C. D. for their I and Q channels respectively: • If the signal of the baseband and the transmission signal has the same sign - do not operate. • If the signal from the baseband is positive and the transmission signal is negative - count up. • If the baseband signal is negative and the transmission signal is positive - countdown. Accordingly, in the preferred embodiment, the decision blocks 250, 252 are implemented according to the following true Table: In this way, the decision blocks issue a counting instruction, (for example, count up or count down) to the counters 246, 248 only during the zero crosses of their associated baseband and transmission signals. The counters 246, 248 are used in this manner to count the time delays between the zero crossings of the baseband signals and the filtered transmission signals. For the most part (for example, when both the baseband signal and the filtered transmission signal have the same sign, both positive or both negative) the decision blocks instruct the counters to remain inactive (eg, output of "error signal" by the decision block is equal to "0"). However, during zero crossings, the counters are instructed to count either ascending or descending, depending on the direction of the CD offset error. As described above with reference to Figure 7, the time delays of the zero crossing, therefore they are used to estimate the CD compensation errors present in the transmission signals. If the induced compensation errors are present in the transmission signals, the counters will track the zero crossing time delays imposed on the transmission signals by the compensation errors. Therefore, the counters contain values that are representative of the compensation errors of C.D. These values are added continuously to the signals of the baseband to compensate the compensation of C. D. present in the signals of the baseband. In this way, the digital signals of the baseband appearing on the input lines 238 (Input I) and 240 (Input Q) are corrected by the outputs of their respective counters 232, 234, thus compensating for the errors of induced compensation. The sign of the selected baseband signal at a time of a given moment is obtained by observing the most significant bit ("MSB") of the digitized signal of the selected baseband which is the input to an associated aggregator. For example, the MSB of the baseband signal of channel I which is the input to aggregator 228 (Figure 5) provides a digitized representation of the sign of the baseband signal of channel I. The MSB of the baseband signal of channel I is provided to a first input of the decision block of channel I 250 by means of signal line 254. Similarly, the MSB of the signal of the band of The base of the channel Q is provided to a first input of the decision block of the channel Q 252 by means of the signal line 256. As described above with reference to the Figures 5 and 6, the sign of a selected transmission signal is obtained from a selected comparator. For example, the sign of the transmission signal of the channel I that is produced by the CDMA filter 104 is obtained from the comparator 224. The comparator 224 generates a digitized representation of the transmission signal of the channel I. Therefore, the signal of the transmission signal of the channel I is provided to a second input of the decision block of the channel I 250, by means of the signal line 242. In a similar way, the sign of the transmission signal of channel Q is provided to a second input of the decision block of channel Q 252 by means of signal line 244. Beyond the inclusion of decision blocks 250, 252, correction circuit 222 of Figure 8, It functions in a manner similar to the correction circuit 222 described above with reference to Figure 6. Accordingly, the same hardware can be used to implement both modalities of the correction circuit 222. Advantageously, both modalities can therefore be implemented in the same integrated circuit, and can be selected in an operative way to cover the operating requirements of correcting the compensation error of the system. The correction method and apparatus illustrated in Figure 8 has certain advantages over that of Figure 6. For example, as counters 246, 248 are inactive most of the time (because the signals of the band signals base and transmission are the same most of the time) the preferred apparatus of Figure 8 requires less power than the correction circuit of Figure 6. Similarly, as the apparatus of Figure 8 only counts the delays of time of the zero crossing of the baseband and transmission signals (which are generally very small) the counters 246, 248 are small compared to the counters of Figure 6. In contrast to the method described above with reference to Figure 6, the preferred method measures compensation errors when the signals of interest are on or near the CD Therefore, the counters used to implement the integrators 246, 248, can be relatively small. Accordingly, when the present invention is implemented in an integrated circuit, the surface area necessary to place the correction circuit 222 is reduced. Therefore, the associated manufacturing costs are also small.

In addition, the preferred correction method of Figure 8 introduces much less noise and distortion in the feedback circuit, than the method of Figure 6. In contrast to the correction circuit illustrated in Figure 6, the correction circuit of Figure 8 makes no assumptions about the CD characteristics of the baseband. The first method in Figure 6 assumes that the baseband signals do not contain any C.D components of any nature. In effect, the method of Figure 6 only indirectly analyzes the signals of the baseband. In contrast, the circuit of Figure 8 makes no assumptions about the content of C.D. of the input signals of the baseband and analyzes these signals directly. As a consequence, the method of Figure 8 tracks in a more accurate manner and filters the signals from the baseband. The correction of D.C. it is only applied to the compensations of D.C. introduced by the transmission DACs and the CDMA filters 104, 106. Advantageously, using the method of Figure 8, the correction of D.C. it is not applied to the components of D.C. present in the base band signals if said components are present. Once the correction has been made to the signals of the baseband, the output of the correction circuit D.C. 222 of Figure 8, remains relatively static until a new compensation error of D.C. By contrast, circuit 222 of Figure 6 is not static and will continuously attempt to converge around a correction point. Accordingly, the compensation conversion circuit of D.C. of Figure 8 introduces much less noise and distortion in the systems than that of Figure 6. Next, a mathematical analysis of the compensation circuit of D.C. of Figure 5 (e.g., the feedback "circuit" comprising the aggregators 228, 230, the transmission DACs 102, the CDMA filters 104, 106, the comparators 224, 226, and the DC compensation correction circuit. 222) to more fully describe the operation of the preferred and alternative embodiments of the present invention.

Analysis of the compensation circuit D.C. The compensation circuit of D.C. of Figure 5 is highly non-linear due to the use of one-bit comparators 224, 226 in the feedback path. Therefore, certain characteristics of the circuit (for example, the time constant of the circuit) are dependent on the signal and as a consequence, are difficult to quantify. The following analysis uses the characteristics of the CDMA signals to predict the time constants of the compensation circuit when used with the correction circuits of Figure 6 and Figure 8. Figure 9 illustrates a representation of an example CDMA signal before of the filtration 600 and after the filtration 602. As illustrated in the example signal 600 of Figure 9, the CDMA signals are essentially randomly filtered bit streams. This implies that the value of the signal will be taken most of the time, either positive-large or negative-large. The transition between the two (the zero crossing) provides the only opportunity for the compensation circuit of D.C. Measure the compensation of D.C. introduced by the CDMA transmission filters 104, 106. In order to track the analysis, suppose that the The slope of the signal is constant as it passes through the zero crossing. This assumption is not completely accurate but it is a reasonable approximation. The slope to zero crossing, therefore, can be calculated as follows: s V = A os. { ?! t) dV Then -_ = -A -Tü)? sin (ü)? /) Because the signal is a CDMA signal, it has a band limited to 630 kHz. Therefore,? MAx = 2? p? 630? 103 To calculate the amplitude A, suppose that the previously filtered signal is of half scale (+ 64 Less Significant Bits (LSBs)) and it is tilted at a maximum rate of 630 kHz. Therefore, A = (4 p)? 64 LBSs. So: mode t-iμ * = p? 6. { 4 O?; R? 630? 103 what = 322.56 LSBs zzs 64 LSBs? elk because the clock T x operates at approximately 5 MHz. If a compensation error of C.D. is entered by any of the transmission DACs 102 or the CDMA filters 104, 106, the error will appear as added to the output of the transmission signal. The error will delay (or advance) the zero crossing. Assuming that the compensation is small, this delay can be calculated as follows: "-K Where? V is the CD offset error in LSBs." This delay can now be examined in light of the two DC error compensation correction techniques described above with reference to Figures 6 through 6. 8. Figure 10 illustrates an example of a digitized signal that is produced by a comparator (224 or 226, Figure 5) when the bit-signal digital signal processing technique described above is used to correct the compensation error. When the signal bit technique described above with reference to Figure 6 is used, a positive DC offset causes the comparator output signal to remain at +1 for a longer time interval and -1 for a shorter time interval As previously described with reference to Figure 6, the sign bit technique integrates the outputs of the comparators During the cycle of a signal (for example, two zero crosses) the integrator counts down for a time interval equal to _T + 2? t, and a count down by a range equal to _T-2? t, where T is the period of the cycle. In this way, the change in the output of the integrator can be calculated in the following way: ? / = -2""? 2-? R + 2? / ^ - 2-? 7, -2 ?? 7? LSBs ZC the integrator output changes a value that is proportional to the offset error of C. D. every two crosses zero. ("ZC"). Figure 11 illustrates an example of a digitized signal that is produced by a comparator (224 or 226, Figure 5) when the digital signal processing technique MSB described above is used to correct the offset error C.D. present in the signal. When the MSB technique described above is used with reference to FIGS. 7 and 8, there is a factor that differentiates from two because the integrator (eg, counter 246 of FIG. 8) only counts a? T per zero crossing in place of two. In general: where "USAR_MSB" is 1 for the MSB technique and 0 for the bit-sign technique. The zero crossing number by crossing the clock can now be determined. In a preferred embodiment, the clock operates at a frequency of two times the Nyquist index, or four times the "chip" index when it is used in a CDMA communication system. The CDMA signals comprise random data signals. Therefore, the probability of a zero crossing between the chips is _. Therefore, on average, a zero crossing occurs every two chips and thus every eight clock cycles. Consequently: A T _ _2- < »* USE_MSB) 25o ^ e | ° J = -2"< n + USE ***» > ?? P 7LSBs Rßioj The feedback is negative and proportional to the compensation error of C.D. Because the change in the output of the integrator is the same as the change in the C.D. , the following happens: d (AV) AV -a ~ a 'twr where ~ This is a first-order differential equation, which can be easily solved. The solution has the form: AV = A.e "/ + B The item of interest in the above equation is the time constant t. This is equal to Tclk / a. Therefore, the time constant of the compensation cycle can be expressed as follows: t = 2 { n + USe-MSB + *) r > Tre, oj The apparatus of the present invention is preferably implemented in an ASIC that is used in a digital cell phone that was described above with reference to Figures 1 a and 1 b. Alternatively, the present invention can be used in any apparatus or system where it is desired to remove the errors of compensation of C. D. which have been imposed on a signal of interest. The compensation method and apparatus of C.D. of the present invention, it can be implemented in the hardware (for example, "thick wiring"), or it can be implemented by software that is executed by a microprocessor or other data processing apparatus in the mobile station. Alternatively, the method may be implemented, using any convenient or desirable sequence apparatus such as a state machine, a separate logical apparatus of the next present condition state, or a programmable field port distribution apparatus. In summary, the present invention includes means for detecting, measuring and correcting the compensation errors of C.D. present in the signal of interest. The present invention is advantageously implemented in an ASIC, it does not require fine adjustment by trimming fuses, as did the offset correction methods of C.D. of prior art and monitors in a dynamic and flexible manner and corrects C.D. as they are introduced in the signal of interest. The present invention is particularly useful in broadband wireless digital communication systems, such as CDMA systems, however, it also finds utility in PCSs and other digital cellular communication systems.

A number of embodiments of the present invention have been described. However, it should be understood that various modifications can be made to it without departing from the spirit and scope of the present invention. For example, the means for converting the transmission signals that are produced by the CDMA filters 104, 106 of Figure 5 can, in alternative embodiments, comprise analog-to-digital converters having a resolution greater than one bit. However, the value added to the operation of the compensation correction of C.D. it is probably not justified by the increase in complexity and cost that arise from it with the use of high resolution A / D converters. Therefore, as described above, the preferred A / D converter comprises a one-bit comparator. In addition, the means for digitally processing the converted transmission signals in the compensation correction circuit of C.D. 222 (Figures 6 and 8), may, in some alternative embodiments, comprise relatively complex digital signal processing techniques that depend on the desired convergence characteristics of the system. For example, more complex integrators can be used including a plurality of integration stages. In a similar way, in some alternative embodiments, the feedback signal (eg, the transmission signal output by the CDMA filters) can be operated in multiple stages of the CDMA filters. The CDMA filters 104, 106 comprise active multi-stage filters that can be operated at one or more stages of the filtration chain. Therefore, in an alternative embodiment of the present invention, the sign information is sampled by the correction circuit of C.D. 222 at various points along the CDMA filter chain. Accordingly, this alternative C.D. correction circuit includes an increased number of entries corresponding to an increased number of information sign interventions. In another alternative embodiment, counters 246, 248 of Figures 6 and 8 are regulated using at least two alternative regulation techniques to reduce the potential tilt problems that may occur when the counters using the signal clocks are being regulated. of channel I (ICLK) (or channel Q (QCLK)). Over time, the clock signals (ICLK or QCLK) can be tilted due to the correlation between the digital signals of the baseband, and the clock signal transitions. This inclination can cause the counters 246, 248 to make a wrong count and therefore incorrectly measure the time delays between zero crossings of the baseband input signals and their associated transmission output signals. Therefore, according to an alternative embodiment of the present invention, the counters 246, 248 are regulated by the random transfer of the clocks of channel I and channel Q. By randomly selecting the clock signals of the counter (using the value of the digital signals of the CDMA baseband), the clock signal is processed in a random manner, and the interval over which the tilt occurs is reduced by a factor of two. Alternatively, each of the digital channels of the baseband signal is hesitant using the opposite signal channel. Therefore, at the point at which the input signals of the digital baseband approach the D.D., it is operated randomly. In this alternative mode, some percentage of the baseband signal of channel I is added to the baseband signal of the Q channel (for example, 10% of the baseband of the channel is added in one mode). I to the signal of the baseband of channel Q). Similarly, some percentage of the baseband signal from the Q channel is added to the baseband signal from channel I (for example, in one mode, 10% of the band signal is added). from the base of channel Q to the signal of the base band of channel I). Using this alternative, the resulting output signal from the CDMA filters will converge to zero even if the baseband signals from channel I and channel Q include a CD offset error. In practice, none of these methods alternatives are necessary, because there seems to be sufficient randomness associated with the transitions of the clock QCLK, ICLK and its zero crosses of the respective associated signal, to prevent the clock signals from exhibiting an undesired inclination with respect to the signal of interest. Accordingly, it should be understood that the present invention should not be limited by the specific embodiment illustrated, but only by the scope of the appended claims.

Claims (18)

1. R E I V I N D I C A I N N E S Having described the present invention, it is considered as a novelty and, therefore, the content of the following CLAIMS is claimed as property: 1 . A compensation correction circuit of C.D., to remove the compensation errors of C.D. from the transmission signals of the baseband in a communication apparatus, receiving the apparatus, the digital input signals of the baseband, wherein the input signals are converted into analog signals by the digital transmission converters to analog and where the analog signals are filtered by the reconstruction filters to produce baseband transmission signals which comprise: a) an analog to digital converter (A / D) placed to convert the transmission signals into digital signals of feedback; b) a digital processing block of correction signal of C.D. having at least one input operatively connected to the A / D converter, wherein the compensation correction block processes the digital feedback signals to produce the compensation correction signals of C.D. nominally equal to the compensation errors of C.D.; and c) an aggregator, operatively connected to the compensation correction block, the aggregator having a first input for receiving the input signals, and a second input for receiving the compensation correction signals, wherein the correction signals are aggregated to the input signals, thus removing the CD compensation errors of the transmission signals.
2. 2. The compensation correction circuit of C.D. , as described in claim 1, further characterized in that the A / D converter comprises a one-bit differential comparator.
3. 3. The compensation correction circuit of C.D., as described in claim 2, further characterized in that the comparator generates the digital feedback signals comprising digitalized representations of the signs of the transmission signals.
4. 4. The compensation correction circuit of C.D. , as described in claim 3, further characterized in that the digital compensation correction signal processing block comprises means for integrating the signs of the transmission signals.
5. 5. The compensation correction circuit of C.D., as described in claim 4, further characterized in that the integration means comprise binary ascending / descending counters.
6. 6. The CD compensation correction circuit, as described in claim 3, further characterized in that the compensation correction signal digital processing block comprises: d) a decision block for generating an error signal in response to the input signals and the transmission signals, wherein the error signal is indicative of the relative signs of the input signals and the transmission signals at any given time point; and e) integrator means for integrating the error signal.
7. 7. The compensation correction circuit of C.D. , as described in claim 6, further characterized in that the decision block comprises logical apparatuses that implement the following true Table: and where the error signal is provided as an input to the integrating means.
8. 8. The compensation correction circuit of C.D. , as described in claim 7, further characterized in that the integrating means comprises a binary ascending / descending counter, and wherein the counter is incremented when the error signal is positive, and wherein the counter is decreased when the signal Error is negative.
9. 9. The compensation correction circuit of C.D., as described in claim 1, further characterized in that the aggregator comprises an eight-bit digital aggregator.
10. 10. The CD compensation correction circuit, as described in claim 1, further characterized in that the correction circuit comprises a processor capable of executing software instructions and has a zero-crossing time delay counter and where the software instructions compare the signals of the input signals with the signs of the transmission signals at a certain time, and where the processor increases, decreases, but does not affect the time delay counter based on the result of the comparison. eleven .
11. The compensation correction circuit of C.D. for removing the CD compensation errors of the baseband transmission signals in a communication apparatus, the apparatus receiving digital input signals from the baseband, wherein the input signals are converted into analog signals by the transmission D / A converters, and wherein the analog signals are filtered by the reconstruction filters to produce the transmission signals which comprise: f) conversion means for converting the transmission signals into digital feedback signals; g) compensation correction means, connected to the conversion means, for digitally processing the digital feedback signals to produce compensation correction signals of C.D. nominally equal to the compensation errors of C.D.; and h) aggregating means, connected to the compensation correction means, the aggregating means having a first input to receive input signals and a second input to receive the compensation correction signals, wherein the correction signals are added to the signals input, thus removing the CD compensation errors from the transmission signals.
12. 12. the CD compensation correction circuit as described in Claim 1 1, further characterized in that the compensation correction means comprise: i) decision means for generating an error signal in response to the input signals and the transmission signals, when the error signal is indicative of relative signs of the input signals and the transmission signals at a given moment of time; and integrating means, connected to the decision means to integrate the error signal.
13. 13. A method to remove the compensation errors of C.D. taxes on the transmission signals in a communications apparatus that receives input signals, wherein the input signals are converted to analog signals and subsequently filtered into the apparatus to produce the transmission signals, which includes the steps of: i) convert the transmission signals into digital feedback signals. j) the processing of the digital feedback signals to produce the compensation correction signals of C. D. nominally equal to the compensation errors of C.D.; and add the compensation correction signals of C.D. to the input signals, removing in this way, the compensation errors of C.D. coming from the transmission signals.
14. 14. The method as described in Claim 13, further characterized in that the processing step (b) comprises the steps of integrating the digital feedback signals with the passage of time.
15. 15. The method as described in Claim 13, further characterized in that the processing step (b), comprises the steps of: k) receiving the most significant bits of the input signals; I) the reception of the digital feedback signals; m) the comparison of the most significant bits of the input signals with the digital feedback signals; and n) the regulation of a counter based on the result of the comparison step (c).
16. 16. A computer program that can be executed in a processor for general purposes in a communications apparatus, wherein the apparatus receives digital input signals, converts the input signals into analog signals and filters the analog signals to produce transmission signals, and wherein the apparatus introduces the DC compensation errors in the transmission signals, which comprises: o) a first set of instructions for converting the transmission signals into digital feedback signals; p) a second set of instructions for the processing of the digital feedback signals to produce compensation correction signals of C. D. nominally equal to the compensation errors of C. D.; and a third set of instructions for adding the compensation correction signals of C.D. to the input signals thereby removing the compensation errors of C.D. of the transmission signals.
17. 17. The computer program as described in Claim 16, further characterized in that the program is executed by an integrated circuit of specific application in the communications apparatus.
18. 18. The computer program as described in Claim 16, further characterized in that the program is executed by a programmable field gate distribution apparatus.