KR980006175A - 엘오씨(loc) 패키지 - Google Patents
엘오씨(loc) 패키지 Download PDFInfo
- Publication number
- KR980006175A KR980006175A KR1019960022068A KR19960022068A KR980006175A KR 980006175 A KR980006175 A KR 980006175A KR 1019960022068 A KR1019960022068 A KR 1019960022068A KR 19960022068 A KR19960022068 A KR 19960022068A KR 980006175 A KR980006175 A KR 980006175A
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- chip
- semiconductor chip
- loc
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 LOC 패키지에 관한 것이다. 반도체 칩이 반도체 리드 프레임의 리드부 선단 하부의 소정영역에 탑재되어 있고, 상기 반도체 칩과 반도체 칩이 탑재된 상기 리드부 선단 하부 사이에, 접착층, 테이프층 및 접착층이 순차적으로 적층된 3층의 절연 부재를 구비하고 있는 엘오씨(LOC: Lead On Chip) 패키지에 있어서, 상기 절연부재가 상기 리드부 선단에만 형성되어 있는 본 발명은 엘오씨(LOC) 패키지는 테이프로 인하여 발생되는 열이 적어 테이프와 칩간의 발기 현상을 방지할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 절연 부재가 형성된 엘오씨(LOC)용 반도체 리드 프레임의 정면도이다.
Claims (1)
- 반도체 칩이 반도체 리드 프레임의 리드부 선단 하부의 소정영역에 탑재되어 있고, 상기 반도체 칩과 반도체 칩이 탑재된 상기 리드부 선단 하부 사이에, 접착층, 테이프층 및 접착층이 순차적으로 적층된 3층의 절연부재를 구비하고 있는 엘오씨(LOC: Lead On Chip) 패키지에 있어서, 상기 절연부재가 상기 리드부 선단에만 형성되어 있는 것을 특징으로 하는 엘오씨(LOC) 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960022068A KR0183653B1 (ko) | 1996-06-18 | 1996-06-18 | 엘오씨 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960022068A KR0183653B1 (ko) | 1996-06-18 | 1996-06-18 | 엘오씨 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980006175A true KR980006175A (ko) | 1998-03-30 |
KR0183653B1 KR0183653B1 (ko) | 1999-03-20 |
Family
ID=19462318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960022068A KR0183653B1 (ko) | 1996-06-18 | 1996-06-18 | 엘오씨 패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0183653B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100686461B1 (ko) * | 2005-04-25 | 2007-02-26 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 리드프레임 구조 |
-
1996
- 1996-06-18 KR KR1019960022068A patent/KR0183653B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0183653B1 (ko) | 1999-03-20 |
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FPAY | Annual fee payment |
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LAPS | Lapse due to unpaid annual fee |