KR970030728A - 수지패키지를 갖는 장치 및 그 제조방법 - Google Patents

수지패키지를 갖는 장치 및 그 제조방법 Download PDF

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Publication number
KR970030728A
KR970030728A KR1019960052529A KR19960052529A KR970030728A KR 970030728 A KR970030728 A KR 970030728A KR 1019960052529 A KR1019960052529 A KR 1019960052529A KR 19960052529 A KR19960052529 A KR 19960052529A KR 970030728 A KR970030728 A KR 970030728A
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South Korea
Prior art keywords
resin
chip
metal film
resin package
package
Prior art date
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KR1019960052529A
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English (en)
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KR100212403B1 (ko
Inventor
유시유키 요네다
가즈토 쓰지
세이이치 오리모
히데하루 사코다
류지 노모토
마사노리 오노데라
주니치 가사이
Original Assignee
세키사와 다다시
후지쓰 가부시키가이샤
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Priority claimed from JP07290135A external-priority patent/JP3129169B2/ja
Priority claimed from JP7322803A external-priority patent/JP3007833B2/ja
Priority claimed from JP25070796A external-priority patent/JP3181229B2/ja
Priority claimed from JP26760796A external-priority patent/JP3189703B2/ja
Application filed by 세키사와 다다시, 후지쓰 가부시키가이샤 filed Critical 세키사와 다다시
Publication of KR970030728A publication Critical patent/KR970030728A/ko
Application granted granted Critical
Publication of KR100212403B1 publication Critical patent/KR100212403B1/ko

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Abstract

장치는 칩(111) 및 칩을 밀봉하고 실장측면에 수지돌출부(117, 154, 318)가 배치된 수지패키지(112, 151, 314)를 포함한다. 금속막(113, 155, 315)은 수지돌출부에 각각 설치된다. 접속부(118, 101, 163, 245, 313, 341, 342)는 금속막과 칩의 전극패드를 전기적으로 접속한다.

Description

수지패키지를 갖는 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 3도는 본 발명의 제 1실시예에 의한 반도체장치의 단면도.

Claims (50)

  1. 칩(111), 상기 칩을 밀봉하고 실장측면에 수지돌출부(117, 154, 318)가 배치된 수지 패키지(112, 151, 314), 수지돌출부에 각각 형성된 금속막(113, 155, 315) 및 금속막과 칩의 전극패드를 전기적으로 접속하는 접속부(118, 101, 163, 245, 313, 341, 342)로 구성되는 것을 특징으로 하는 장치.
  2. 제 1항에 있어서, 상기 금속막의 각각이 금속물질로 된(113A)인 것을 특징으로 하는 장치.
  3. 제 1항에 있어서, 상기 금속막의 각각이 적층되는 다수의 금속층(113B-113D, 213E-213G)로 구성되는 것을 것을 특징으로 하는 장치.
  4. 제 1항에 있어서, 상기 접속부가 각각 전극패드와 금속막에 접합되는 본딩와이어(118)로 구성되는 것을 특징으로 하는 장치.
  5. 제 1항에 있어서, 상기 접속부가 각각 본딩와이어(118)와, 금속막에 각각 설치된 본딩볼(101, 245)로 구성되고, 본딩와이어가 전극패드와 본딩볼에 접합되는 것을 특징으로 하는 장치.
  6. 제 1항에 있어서, 상기 수지패키지가 수지돌출부를 일체로 형성하도록 한 성형패키지인 것을 특징으로 하는 장치.
  7. 제 7항에 있어서, 상기 수지패키지가 칩을 설치되는 제 1수지부(153)과 칩을 덮는 제 2수지부(152)를 포함하는 것을 특징으로 하는 장치.
  8. 제 7항에 있어서, 상기 접속부가 각각 본디와이어(118)과, 상기 제 1수지부상에 설치되고 금속막에서 수지돌출부로 연장되는 접속전극(156)으로 구성되고, 상기 본딩와이어가 전극패드와 접속전극에 접합되는 것을 특징으로 하는 장치.
  9. 칩(111) 상기 칩을 밀봉하고, 칩이 설치되는 제 1수지부(153)의 칩을 덮는 제 2수지부(152)하는 를 갖는 수지패키지(151), 본디와이어(118)와, 제 1수지부(153)상에 설치되어 그로부터 돌출하는 접속전극(172)을 갖는 접속부(118, 172), 상기 접속부의 접속전극에 각각 형성된 금속막(155)으로 구성된 것을 특징으로 하는 장치.
  10. 칩(111) 상기 칩을 밀봉하고, 칩이 설치되고 관통공을 갖는 제 1수지부(183)와 칩을 덮는 제 2수지부(182)를 갖는 수지패키지(181), 상기 제 1수지부(182)에 설치되어 각각 관통공을 덮는 전극부(185), 및 전극부(185)와 상기 칩의 전극패드를 접속하는 접속부(118)로 구성되는 것을 특징으로 하는 장치.
  11. 칩(111) 상기 칩을 밀봉하고, 칩이 설치되고 관통공을 갖는 제 1수지부(183)와 칩을 덮는 제 2수지부(182)를 갖는 수지패키지(181), 상기 제 1수지부(182)에 설치되어 각각 관통공을 덮는 전극부(185), 및 전극부(185)와 상기 칩의 전극패드를 접속하는 접속부(118)로 구성되는 것을 특징으로 하는 장치.
  12. 제 11항에 있어서, 상기 제 1수지부가 수지 테이프(183)로 구성되는 것을 특징으로 하는 장치.
  13. 제 11항에 있어서, 상기 접속부가 각각 전극패드와 전극부(185)에 접합하는 본딩와이어로 구성되는 것을 특징으로 하는 장치.
  14. 칩(211) 상기 칩을 밀봉하고, 실장측면에 배치된 수지돌출부(217, 217B)를 갖되, 이 수지돌출부가 수지패키지의 실장측면에서 하방을 연장되고 그 적어도 일측면에서 횡으로 연장되는 수지패키지(212), 수지돌출부에 각각 형성된 금속막(213) 및 금속막과 상기 칩의 전극패드를 전기적으로 접속하는 접속부(218)로 구성되는 것을 특징으로 하는 장치.
  15. 제 14항에 있어서, 상기 금속막의 각각이 금속물질로 된 단층(113A)인 것을 특징으로 하는 장치.
  16. 제 14항에 있어서, 상기 금속막의 각각이 적층되는 다수의 금속층(113B-113D, 213E-213G)로 구성되는 것을 특징으로 하는 장치.
  17. 제 14항에 있어서, 상기 접속부가 각각 전극패드와 금속막에 접합되는 본디와이어(218)로 구성되는 것을 특징으로 하는 장치.
  18. 제 14항에 있어서, 상기 접속부가 각각 본딩와이어(218)와 금속막에 각각 설치된 본딩볼(101, 245)로 구성되고, 본딩와이어가 전극패드와 본딩볼에 접합되는 것을 특징으로 하는 장치.
  19. 제 14항에 있어서, 상기 수지패키지가 수지돌출부로 일체로 형성하도록 한 성형패키지인 것을 특징으로 하는 장치.
  20. 제 14항에 있어서, 상기 수지돌출부(217)가 상기 수지패키지의 다수의 측면에서 횡으로 연장되는 것을 특징으로 하는 장치.
  21. 제 14항에 있어서, 상기 수지돌출부(217b)가 상기 수지패키지의 일측면에서만 횡으로 연장되는 것을 특징으로 하는 장치.
  22. 제 20항에 있어서, 상기 수지패키지(212)에 설치되어 회로기판상에 수직으로 실장되는 장치를 지지하는 지지부재(253)로 구성되는 것을 특징으로 하는 장치.
  23. 칩(211) 상기 칩을 밀봉하고, 실장측면에서 배치된 수지돌출부(291A, 291B)를 갖되, 이 수지돌출부가 수지패키지의 실장측면에서 하방으로 연장되고, 그 측면과 거의 동일 평면에 있는 수지패키지(212), 수지돌출부에 각각 형성된 금속막(290A, 290B) 및 금속막과 상기 칩의 전극패드를 전기적으로 접속하는 접속부(218)로 구성되는 것을 특징으로 하는 장치.
  24. 제 23항에 있어서, 상기 수지돌출부가 제 1돌출부(291A)와 제돌출부 보다 횡방향으로 더 길어 칩아래로 연장되고 제 2돌출부(291B)로 구성되고, 상기 금속막이 제 1돌출부상에 형성된 제 1금속막(290A)과 제 2돌출부상에 형성된 제 2금속막(290B)로 구성되는 것을 특징으로 하는 장치.
  25. 제 23항에 있어서, 수지패키지의 실장측면에 설치되는 스페이서(293)로 더 구성되어 스페이서가 회로기판상에 장치를 지지할 때에 다른 장치와 접촉하여 수지패키지의 상기 측면이 회로 기판에 접하는 것을 특징으로 하는 장치.
  26. 제 25항에 있어서, 상기 스페이서가 열방사 부재인 것을 특징으로 하는 장치.
  27. 수지패키지에 의해 밀봉된 칩을 각각 갖는 제조방법에 있어서, (a) 금속막(113)을 각각 갖는 요부(122)를 갖는 베이스(121)를 갖는 리드프레임(120)을 형성하고, (b) 리드프레임상에 칩(111)을 실장하고, (c) 금속막과 칩의 전극패드를 전기적으로 접속하는 접속부(118, 101, 163, 245)를 설치하고, (d) 수지를 형성하여 성형된 수지가 각각 칩과 리드 프레임에 의해 지지된 금속막을 덮고, (e) 요부의 상대물인 수지돌출부에 형성된 금속막과 함께 성형된 수지패키지를 리드프레임에서 분리하는 단계로 구성되는 것을 특징으로 하는 장치의 제조방법.
  28. 제 27항에 있어서, 상기 단계(e)는 리드프레임을 에칭하여 리드프레임을 용해하는 단계로 구성되는 것을 특징으로 하는 장치의 제조방법.
  29. 제 27항에 있어서, 상기 단계(e)는 성형된 수지패키지와 금속막에서 리드프레임을 기계적으로 분리하는 단계로 구성되는 것을 특징으로 한는 장치의 제조방법.
  30. 제 27항에 있어서, 상기 단계(e)를 실행하기 전에 형성된 수지패키지에 테이프를 설치하는 단계로 더 구성되는 것을 특징으로 하는 장치의 제조방법.
  31. 제 27항에 있어서, 상기 단계(c)는 금속막에 본딩볼을 설치하는 제 1단계와 본딩볼과 칩의 전극패드에 본딩와이어를 접합하는 제 2단계로 구성되되, 본딩볼과 본딩와이어가 상기 접속부에 상응하는 것을 특징으로 하는 장치의 제조방법.
  32. 제 27항에 있어서, 상기 단계(d)는 수지를 형성하여 성형된 수지패키지가 함께 접합되는 것을 특징으로 하는 장치의 제조방법.
  33. 제 27항에 있어서, 상기 단계(d)가 수지를 성형하여 성형된 수지패키지가 서로 분리되는 것을 특징으로 하는 장치의 제조방법.
  34. 칩(311), 상기 칩을 밀봉하고 실장측면을 갖는 수지패키지(314), 금속막이 실장측면과 동일평면이고 그로부터 노출되도록 수지패키지에 각각 형성된 금속막(315) 및 금속막과 칩의 전극패드를 전기적으로 접속하는 접속부(313, 101, 342)로 구성되는 것을 특징으로 하는 장치의 제조방법.
  35. 제 34항에 있어서, 상기 접속부가 각각 본딩와이어(313) 및 금속막에 각각 형성된 본딩볼(101)로 구성되고, 본딩와이어가 전극패드와 본딩볼에 접합되는 것을 특징으로 하는 장치의 제조방법.
  36. 제 34항에 있어서, 상기 금속막의 각각이 금속물질로 된 단층(315A)인 것을 특징으로 하는 장치의 제조방법.
  37. 제 34항에 있어서, 상기 금속막의 각각이 적층되는 다수의 금속층(315B-315B)으로 구성되는 것을 특징으로 하는 장치의 제조방법.
  38. 제 34항에 있어서, 상기 접속부가 금소막(315)과 칩(311)의 전극패드(312) 사이에 설치된 범프(342)로 각각 구성되는 것을 특징으로 하는 장치의 제조방법.
  39. 수지패키지에 의해 밀봉된 칩을 각각 갖는 제조방법에 있어서, (a) 금속막(315)이 형성되는 베이스(321)는 리드 프레임(320)을 형성하고, (b) 리드프레임상에 칩(311)을 실장하고, (c) 금속막과 칩의 전극패드를 전기적으로 접속하는 접속부(313, 101)를 설치하고, (d) 수지를 형성하여 성형된 수지가 각각 칩과 리드 프레임에 의해 지지된 금속막을 덮고, (e) 금속막과 함께 성형된 수지패키지를 리드프레임에서 분리하여 성형된 수지패키지의 실장측면에서 칩을 노출하는 단계로 구성되는 것을 특징으로 하는 장치의 제조방법.
  40. 제 39항에 있어서, 상기 단계(e)가 리드프레임을 에칭하여 리드프레임을 용해하는 단계로 구성되는 것을 특징으로 하는 장치의 제조방법.
  41. 제 39항에 있어서, 상기 단계(e)는 성형된 수지패키지와 금속막에서 리드프레임을 기계적으로 분리하는 단계로 구성되는 것을 특징으로 하는 장치의 제조방법.
  42. 제 1항에 있어서, 상기 금속막(315)이 각각 수지패키지에 의해 밀봉되고 칩쪽으로 연장되는 리드부(3151)을 갖고, 상기 접속부가 상기 리드부에 접합되는 본딩와이어를 포함는 것을 특징으로 하는 장치의 제조방법.
  43. 제 42항에 있어서, 수지패키지에 의해 밀봉된 열방사부재(340)로 더 구성되어, 칩이 상기 열방사부재상에 설치되는 것을 특징으로 하는 장치.
  44. 제 1항에 있어서, 상기 접속부재가 각각 금속막(315)과 칩(311)의 전극패드(312) 사이에 설치된 범프(342)로 구성되는 것을 특징으로 하는 장치.
  45. 제 1항에 있어서, 상기 금속막(315)이 각각 수지패키지에 의해 밀봉되고 칩 쪽으로 연장되는 리드부(3151)를 갖고, 상기 접속부가 금속막의 리드부(3151)와 칩(331)의 전극패드(312)사이에 설치된 범프(342)를 포함하는 것을 특징으로 하는 장치.
  46. 제 1항에 있어서, 상기 금속막(315)이 각각 수지패키지에 의해 밀봉되고 칩쪽으로 연장되며 요부(343)를 갖는 리드부(3151)를 갖고, 상기 접속부가 상기 요부(343) 내에 배치되고 금속막의 리드부(3151)와 칩(311)의 전극패드(312) 사이에 설치되는 범프(342)를 포함하는 것을 특징으로 하는 장치.
  47. 제 44항에 있어서, 전극패드가 설치되는 표면과 반대인 칩(311)의 이면이 수지패키지의 실장측면과 반대인 그 표면에서 노출되는 것을 특징으로 하는 장치.
  48. 제 47항에 있어서, 칩의 이면에 부착된 열방사부재(345)로 구성되는 것을 특징으로 하는 장치.
  49. 제 4항에 있어서, 전극패드가 설치되는 칩의 표면에 설치된 절연부재로 더 구성되는 것을 특징으로 하는 장치.
  50. 제 44항에 있어서, 상기 접속부가 소정의 압력하에 함께 접합된 도전성 입자(348)를 포함하는 전기적 도전성 수지로 구성되는 것을 특징으로 하는 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960052529A 1995-11-08 1996-11-07 수지패키지를 갖는 장치 및 그 제조방법 KR100212403B1 (ko)

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JP95-322803 1995-12-12
JP18383896 1996-07-12
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JP25070796A JP3181229B2 (ja) 1996-07-12 1996-09-20 半導体装置及びその製造方法及びその実装方法及びリードフレーム及びその製造方法
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JP26760796A JP3189703B2 (ja) 1996-10-08 1996-10-08 半導体装置及びその製造方法
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