KR970006254B1 - Fabrication method of tft - Google Patents
Fabrication method of tft Download PDFInfo
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- KR970006254B1 KR970006254B1 KR1019940005484A KR19940005484A KR970006254B1 KR 970006254 B1 KR970006254 B1 KR 970006254B1 KR 1019940005484 A KR1019940005484 A KR 1019940005484A KR 19940005484 A KR19940005484 A KR 19940005484A KR 970006254 B1 KR970006254 B1 KR 970006254B1
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- Prior art keywords
- forming
- metal material
- semiconductor layer
- anodization
- source
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 title description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000007743 anodising Methods 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 42
- 239000007769 metal material Substances 0.000 claims description 40
- 238000002048 anodisation reaction Methods 0.000 claims description 31
- 230000000903 blocking effect Effects 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 21
- 239000010409 thin film Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 69
- 229910021417 amorphous silicon Inorganic materials 0.000 description 14
- 239000011810 insulating material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1도는 종래의 기술에 의한 박막트랜지스터의 단면도.1 is a cross-sectional view of a thin film transistor according to the prior art.
제2도는 본 발명에 의한 박막트랜지스터의 제1실시예의 단면도.2 is a cross-sectional view of a first embodiment of a thin film transistor according to the present invention.
제3도는 제2도의 제조공정을 도시한 단면도.3 is a sectional view showing a manufacturing process of FIG.
제4도는 본 발명에 의한 박막트랜지스터의 제2실시예의 제조공정을 도시한 단면도.4 is a cross-sectional view showing the manufacturing process of the second embodiment of the thin film transistor according to the present invention.
제5도는 본 발명에 의한 박막트랜지스터의 제3실시예의 제조공정을 도시한 단면도.5 is a cross-sectional view showing the manufacturing process of the third embodiment of the thin film transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2a : 소스/드레인 전극1 substrate 2a source / drain electrodes
2b : 양극산화막 3 : 오믹 접촉용 반도체층2b: anodized film 3: semiconductor layer for ohmic contact
4 : 제2반도체층 5 : 절연막4: second semiconductor layer 5: insulating film
6 : 게이트전극 7 : 양극산화저지막6 gate electrode 7 anodization blocking film
본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 특히 소스/드레인(source/drain) 전극에 의한 단차를 최소화 하기 위한 박막트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor for minimizing the step by the source / drain (source / drain) electrode.
종래의 박막트랜지스터는 스태거형(staggered type)의 경우 제1도에 도시한 바와 같이, 기판(1) 상부에 도전물질을 마스크를 형성하고 상기 마스크를 적용하여 식각함으로써 형성된 소스/드레인 전극(2a)과, 상기 결과물 전면에 불순물(n+)이 도핑된 비정질 실리콘을 증착시킨 후 상기 소스/드레인 전극(2a) 상부에만 남도록 식각하여 형성된 오믹 접촉용 반도체층(3)과, 상기 오믹 접촉용 반도체층(3) 상부에 반도체물질을 증착시킨 후 일정 타입으로 식각하여 형성된 제2반도체층(4)과, 하부 구조물과 상부구조물을 전기적으로 절연시키기 위해 상기 결과물 전면에 절연물질을 증착시켜 형성된 절연막(5)과, 절연막(5) 상부에 도전물질을 증착시킨 후 선택적으로 식각하여 형성된 게이트전극(6)으로 구성되어 있는데, 이러한 스태거형 박막트랜지스터의 경우 소스/드레인 전극(2a) 형성시 소스/드레인 전극의 에지(edge)부분을 테이퍼(taper) 식각하여야 하나 후속공정시 상기 소스/드레인 전극에 의한 단차로 인해 상기 소스/드레인 전극 상부에 형성될 다음 박막을 끊어지지 않고 형성하기 위해서는 상시 테이퍼 식각의 제어가 매우 어렵기 때문에 재현성과 균일성이 저하되는 문제점이 있다.In the conventional thin film transistor, a staggered type source / drain electrode 2a formed by etching a conductive material on the substrate 1 and etching by applying the mask, as shown in FIG. ), An ohmic contact semiconductor layer 3 formed by depositing amorphous silicon doped with an impurity (n + ) on the entire surface of the resultant and remaining only on the source / drain electrode 2a, and the ohmic contact semiconductor. A second semiconductor layer 4 formed by depositing a semiconductor material on the layer 3 and then etching to a predetermined type, and an insulating film formed by depositing an insulating material on the entire surface of the resultant to electrically insulate the lower structure and the upper structure. 5) and a gate electrode 6 formed by depositing a conductive material on the insulating film 5 and selectively etching the same. In the case of such a staggered thin film transistor, source / When the drain electrode 2a is formed, the edge portion of the source / drain electrode should be tapered. However, in the subsequent process, the next thin film to be formed on the source / drain electrode due to the step by the source / drain electrode is removed. Since it is very difficult to control the taper etching at all times in order to form without breaking, there is a problem in that reproducibility and uniformity are lowered.
따라서 본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 기판위에 소스/드레인 전극을 형성하기 위한 금속물지층을 형성한 후 그 상부에 양극산화 저지막 패턴을 형성하고 상기 양극산화 저지막 패턴을 적용하여 상기 금속물층의 일부분을 양극산화하여 산화되지 않은 부분으로 소스/드레인 전극을 형성함으로써 단차를 감소시킬 수 있는 박막트랜지스터의 제조방법을 제공하는 것이다.Therefore, an object of the present invention is to form a metal material layer for forming a source / drain electrode on the substrate in order to solve the above problems and then to form an anodization stop layer pattern on the top and apply the anodization stop layer pattern By anodic oxidation of a portion of the metal material layer to form a source / drain electrode as an unoxidized portion to provide a method for manufacturing a thin film transistor that can reduce the step difference.
본 발명의 다른 목적은 기판위에 금속물질층 및 불순물이 도핑된 비정질 실리콘층을 순차적으로 적층시켜 형성한 후 상기 비정질 실리콘층 상부에 양극산화 저지막을 적용하여 상기 비정질 실리콘층을 식각하고, 계속하여 상기 양극산화 저지막을 마스크로 적용하여 상기 금속물질층을 양극산화시켜 산화되지 않은 금속물질층으로 소스/드레인 전극을 형성하는 박막트랜지스터의 제조방법을 제공하는 것이다.Another object of the present invention is formed by sequentially laminating a metal material layer and an amorphous silicon layer doped with impurities on a substrate and then etching the amorphous silicon layer by applying an anodization blocking film on the amorphous silicon layer, and subsequently The present invention provides a method of manufacturing a thin film transistor in which an anodization blocking film is used as a mask to anodize the metal material layer to form a source / drain electrode with an unoxidized metal material layer.
본 발명의 또다른 목적은 기판위에 금속물질층 및 불순물이 도핑된 비정질 실리콘층을 순차적으로 적층시켜 양성한 후 오믹접촉용 반도체층 형성시 상기 불순물이 도핑된 반도체층을 식각하지 않고 상기 양극산화 저지막을 마스크로 하여 상기 불순물이 도핑된 반도체층 및 금속물질층을 양극산화함으로써 소스/드레인 전극과 동시에 오믹접촉용 반도체층을 형성하는 박막트랜지스터의 제조방법을 제공하는 것이다.It is another object of the present invention to sequentially stack and train a metal material layer and an amorphous silicon layer doped with impurities on a substrate, and then prevent the anodization without etching the semiconductor layer doped with impurities when forming an ohmic contact semiconductor layer. The present invention provides a method of manufacturing a thin film transistor which forms an ohmic contact semiconductor layer simultaneously with a source / drain electrode by anodizing a semiconductor layer and a metal material layer doped with impurities using a film as a mask.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터의 제조방법은 기판 상부에 양극산화 가능한 금속물질을 소정의 두께로 증착하여 금속물질층을 형성하는 공정과, 상기 금속물질층 상부에 양극산화 저지막을 형성하는 공정과, 상기 양극산화 저지막을 마스크로 하여 상기 금속물질층을 양극산화시켜 양극산화되지 않은 부분으로 소스/드레인 전극을 형성하는 공정과, 상기 소스/드레인 전극 형성 후 오믹접촉용 반도체층, 반도체층, 절연막 및 게이트 전극을 형성하는 공정을 포함하여 구성된 것을 특징으로 한다.A method of manufacturing the thin film transistor of the present invention for achieving the above object is a step of forming a metal material layer by depositing an anodizable metal material on a substrate with a predetermined thickness, and forming an anodization blocking film on the metal material layer And anodizing the metal material layer using the anodization blocking film as a mask to form a source / drain electrode on an unanodized portion, and forming an ohmic contact semiconductor layer after forming the source / drain electrode. And forming a layer, an insulating film, and a gate electrode.
상기 다른 목적을 달성하기 위한 본 발명의 박막트랜지스터의 제조방법은 기판 상부에 양극산화가 가능한 금속물질을 소정의 두께로 증착하여 금속물질층을 형성하는 공정과, 상기 금속물질층 상부에 불순물이 도핑된 반도체층을 형성하는 공정과, 상기 불순물이 도핑된 반도체층 상부에 양극산화 저지막을 형성하는 공정과, 상기 양극산화 저지막 형성 후 상기 양극산화 저지막을 마스크로 하여 상기 불순물이 도핑된 반도체층을 식각하여 오믹 접촉용 반도체층을 형성하는 공정과, 상기 양극산화 저지막을 마스크로 하여 상기 금속물질층을 양극산화하여 양극산화되지 않은 부분으로 소스/드레인 전극을 형성하는 공정과, 상기 소스/드레인 전극 형성 후 반도체층, 절연막 및 게이트 전극을 형성하는 공정을 포함하여 구성된 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, by depositing a metal material capable of anodizing to a predetermined thickness on a substrate to form a metal material layer, and doping impurities on the metal material layer. Forming an anodic oxidation stopper film on the semiconductor layer doped with the impurity, and forming the anodization stopper film as a mask after the formation of the anodization stopper film. Etching to form an ohmic contact semiconductor layer, anodizing the metal material layer using the anodization blocking layer as a mask, and forming a source / drain electrode on an unanodized portion, and the source / drain electrode And forming a semiconductor layer, an insulating film, and a gate electrode after formation.
또한 상기 또다른 목적을 달성하기 위한 본 발명의 박막트랜지스터의 제조방법은 기판 상부에 양극산화가 가능한 금속물질을 소정의 두께로 증착하여 금속물질층을 형성하는 공정과, 상기 금속물질층 상부에 불순물이 도핑된 반도체층을 형성하는 공정과, 상기 불순물이 도핑된 반도체층 상부에 양극산화 저지막을 형성하는 공정과, 양극산화 저지막 형성 후 불순물이 도핑된 반도체층을 식각하지 않고 상기 양극산화 저지막을 마스크로 하여 상기 불순물이 도핑된 반도체층 및 금속물질층을 양극산화함으로써 소스/드레인 전극과 동시에 오믹 접촉용 반도체층을 형성하는 공정과, 상기 소스/드레인 전극 형성 후 반도체층, 절연막 및 게이트 전극을 형성하는 공정을 포함하여 구성된 것을 특징으로 한다.In addition, the manufacturing method of the thin film transistor of the present invention for achieving the above another object is a step of forming a metal material layer by depositing a metal material capable of anodizing to a predetermined thickness on the substrate, and an impurity on the metal material layer Forming the doped semiconductor layer, forming an anodization blocking film on the impurity doped semiconductor layer, and forming an anodization blocking film without etching the impurity doped semiconductor layer after forming the anodization blocking film. Forming an ohmic contact semiconductor layer at the same time as the source / drain electrode by anodizing the impurity-doped semiconductor layer and the metal material layer as a mask, and forming the semiconductor layer, the insulating film, and the gate electrode after forming the source / drain electrode. Characterized in that it comprises a step of forming.
이하 첨부도면을 참조하여 본 발명을 좀 더 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
본 발명의 박막트랜지스터의 제조방법은 오믹 접촉용 실시예의 경우 먼저, 제3도의 (a)도에서는 기판(1) 상부에 소스/드레인 전극을 형성하기 위해 금속물질로서 예를 들면 알루미늄(Al) 또는 탄탈(Ta)을 단층으로 증착시키거나 다층으로 증착시킨다.In the method of manufacturing a thin film transistor of the present invention, in the case of an ohmic contact, first, in FIG. 3 (a), in order to form a source / drain electrode on the substrate 1, for example, aluminum (Al) or Tantalum (Ta) is deposited in a single layer or in multiple layers.
(b)도에서는 계속하여 상기 금속물질층 상부에 포토레지스터나 실리콘 나이트 라이드 또는 실리콘 옥사이드와 같은 절연물질을 소정의 두께로 증착시킨 후 패터닝하여 양극산화 저지막(7)을 형성한다.In FIG. 2B, an insulating material such as photoresist, silicon nitride, or silicon oxide is deposited on the metal material layer to a predetermined thickness, and then patterned to form an anodization blocking film 7.
(c)도에서는 상기 양극산화 저지막(7)을 적용하여 상기 금속물질층을 양극산화하여 산화되지 않고 남은 금속물질층으로 소스/드레인 전극(2a)를 형성한다.In FIG. 3C, the anodization blocking film 7 is applied to anodize the metal material layer to form a source / drain electrode 2a using the metal material layer remaining without being oxidized.
(d)도에서는 상기 양극산화 저지막(7)을 제거한다.In (d), the anodization blocking film 7 is removed.
그리고 상기 (d)도의 공정 후에는 종래와 동일한 방법으로 상기 결과물 전면에 불순물(n+)이 도핑된 비정질 실리콘을 증착시킨 후 상기 소스/드레인 전극(2a) 상부에만 남도록 식각하여 오믹(obmic) 접촉용 반도체층(3)을 형성하고, 상기 오믹 접촉용 반도체층(3) 상부에 반도체물질을 증착시킨 후 일정타입으로 식각하여 제2반도체층(4)을 형성하며, 하부 구조물과 상부 구조물을 전기적으로 절연시키기 위해 상기 결과물 전면에 절연물질을 증착시켜 절연막(5)을 형성하며, 상기 절연막(5) 상부에 도전물질을 증착시킨 후 선택적으로 식각하여 게이트전극(6)을 형성하여 제2도에 도시한 바와 같은 박막트랜지스터를 완성한다.After the process of (d), the amorphous silicon doped with impurity (n + ) is deposited on the entire surface of the resultant body in the same manner as in the related art, and then etched to remain only on the source / drain electrode 2a to form an ohmic contact A second semiconductor layer 4 is formed by depositing a semiconductor material 3 on the ohmic contact semiconductor layer 3, depositing a semiconductor material on the ohmic contact semiconductor layer 3, and etching the substrate to a predetermined type. In order to insulate the insulating film, an insulating material is deposited on the entire surface of the resultant to form an insulating film 5. A conductive material is deposited on the insulating film 5, and then selectively etched to form a gate electrode 6. The thin film transistor as shown is completed.
한편 본 발명의 제2실시예에서는 오믹 접촉용 실시예와는 달리 오믹 접촉층이 될 오믹 접촉용 반도체층을 소스/드레인 전극과 동시에 형성하는데 제조방법은 제4도에 도시한 바와 같다.On the other hand, in the second embodiment of the present invention, unlike the ohmic contact embodiment, the ohmic contact semiconductor layer to be the ohmic contact layer is formed at the same time as the source / drain electrodes. The manufacturing method is as shown in FIG.
먼저 (a)도를 참조하면 기판(1) 상부에 탄탈 또는 알루미늄과 같은 금속물질과 불순물이 도핑된 비정질 실리콘을 순차적으로 적층시켜 금속물질층 및 불순물 비정질 실리콘층을 형성한다.Referring first to (a), a metal material such as tantalum or aluminum and amorphous silicon doped with impurities are sequentially stacked on the substrate 1 to form a metal material layer and an impurity amorphous silicon layer.
이어서 (b)도에서는 상기 불순물 비정질 실리콘층 상부에 포토레지스트를 도포한 후 패터닝하여 양극산화 저지막(7)을 형성한다.Subsequently, in (b), a photoresist is applied on the impurity amorphous silicon layer and then patterned to form an anodization blocking film 7.
(c)도에서는 상기 양극산화 저지막(7)을 적용하여 상기 비정질 실리콘층 및 금속물질층을 양극산화시켜 산화되지 않은 금속물질층으로 소스/드레인 전극(2a)을 형성하며 그 상부의 비정질실리콘으로 오믹 접촉용 반도체층(2b)을 형성한다.In (c), the anodization stopper layer 7 is applied to anodize the amorphous silicon layer and the metal material layer to form a source / drain electrode 2a as an unoxidized metal material layer, and the amorphous silicon on the top. Thus, the ohmic contact semiconductor layer 2b is formed.
(d)도에서는 상기 오믹 접촉용 반도체층(2b) 형성 후 상기 양극산화 저지막을 제거하고 그 결과물 전면에 비정질 실리콘 및 절열물질을 순차적으로 증착시켜 제2반도체층(4) 및 절연막(5)을 형성한 후 계속하여 상기 절연막(5) 상부에 게이트 전극(6)을 형성한다.In (d), after the formation of the ohmic contact semiconductor layer 2b, the anodization stopper film is removed, and the second semiconductor layer 4 and the insulating film 5 are sequentially deposited by depositing amorphous silicon and an insulating material on the entire surface of the resultant. After the formation, the gate electrode 6 is formed on the insulating film 5.
또한 본 발명의 제3실시예에서는 제2실시예에서 오믹 접촉용 반도체층을 식각없이 형성하는 대신 불순물 비정질 실리콘을 소정의 두께로 도포한 후 식각하고 그 하부의 금속물질층을 양극산화하여 소스/드레인 전극을 형성하는데, 그 제조방법은 제5도에 도시한 바와 같다.In addition, in the third embodiment of the present invention, instead of forming the ohmic contact semiconductor layer without etching in the second embodiment, an impurity amorphous silicon is applied to a predetermined thickness and then etched, and the lower metal material layer is anodized so that the source / A drain electrode is formed, the manufacturing method of which is as shown in FIG.
먼저 양극산화 저지막(7) 형성까지는 제4도의 (a)도 및 (b)도와 동일하므로 제4도의 (a)도 및 (b)도를 참조하고, 계속하여 제5도의 (a)도에서는 상기 양극산화 저지막(7)을 마스크로 하여 상기 불순물이 도핑된 비정질 실리콘층으로 식각함으로써 오믹 접촉용 반도체층(3)을 형성한다.First, the formation of the anodization stopper film 7 is the same as in FIGS. 4A and 4B, and thus, FIGS. 4A and 4B are continued. The ohmic contact semiconductor layer 3 is formed by etching the amorphous silicon layer doped with the impurity using the anodization blocking layer 7 as a mask.
(b)도에서는 상기 양극산화 저지막(7)을 마스크로 하여 금속물질층을 양극산화시켜 양극산화되지 않은 부분의 금속물질층으로 소스/드레인 전극(2a)을 형성한다.In FIG. 2B, the metal material layer is anodized using the anodization blocking film 7 as a mask to form a source / drain electrode 2a using a metal material layer of an unanodized portion.
(c)도에서는 상기 소스/드레인 전극(2a) 형성 후 결과물 전면에 반도체 물질 및 절연물질을 순차적으로 적층시킨 후 소정패턴으로 식각하여 제2반도체층(4) 및 절연막(5)을 형성하고 이어서 상기 절연막(5) 상부에 도전물질을 증착시킨 후 선택적으로 식각하여 게이트전극(6)을 형성한다.In FIG. 3C, after forming the source / drain electrodes 2a, semiconductor materials and insulating materials are sequentially stacked on the entire surface of the resultant, and then etched in a predetermined pattern to form a second semiconductor layer 4 and an insulating film 5. The conductive material is deposited on the insulating film 5 and then selectively etched to form the gate electrode 6.
이상에서와 같이 본 발명에 의하면 양극산화에 의해 소스/드레인 전극을 형성함으로써 단차의 발생을 방지할 수 있으며, 이에 따라 박막트랜지스터의 안정성 및 신뢰도를 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, the source / drain electrodes may be formed by anodization to prevent generation of steps, thereby improving stability and reliability of the thin film transistor.
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