KR970000198B1 - Process for anisotropically etching semiconductor material - Google Patents

Process for anisotropically etching semiconductor material Download PDF

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Publication number
KR970000198B1
KR970000198B1 KR93009164A KR930009164A KR970000198B1 KR 970000198 B1 KR970000198 B1 KR 970000198B1 KR 93009164 A KR93009164 A KR 93009164A KR 930009164 A KR930009164 A KR 930009164A KR 970000198 B1 KR970000198 B1 KR 970000198B1
Authority
KR
South Korea
Prior art keywords
semiconductor material
pattern
material layer
forming
anisotropically etching
Prior art date
Application number
KR93009164A
Other languages
English (en)
Inventor
Hae-Sung Park
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=19356071&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR970000198(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR93009164A priority Critical patent/KR970000198B1/ko
Priority to US08/248,754 priority patent/US5509995A/en
Priority to JP6110900A priority patent/JP2690860B2/ja
Application granted granted Critical
Publication of KR970000198B1 publication Critical patent/KR970000198B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
KR93009164A 1993-05-26 1993-05-26 Process for anisotropically etching semiconductor material KR970000198B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR93009164A KR970000198B1 (en) 1993-05-26 1993-05-26 Process for anisotropically etching semiconductor material
US08/248,754 US5509995A (en) 1993-05-26 1994-05-25 Process for anisotropically etching semiconductor material
JP6110900A JP2690860B2 (ja) 1993-05-26 1994-05-25 半導体物質の非等方性エッチング方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93009164A KR970000198B1 (en) 1993-05-26 1993-05-26 Process for anisotropically etching semiconductor material

Publications (1)

Publication Number Publication Date
KR970000198B1 true KR970000198B1 (en) 1997-01-06

Family

ID=19356071

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93009164A KR970000198B1 (en) 1993-05-26 1993-05-26 Process for anisotropically etching semiconductor material

Country Status (3)

Country Link
US (1) US5509995A (ko)
JP (1) JP2690860B2 (ko)
KR (1) KR970000198B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1098162A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd 半導体集積回路装置の製造方法
US5930644A (en) * 1997-07-23 1999-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation using oxide slope etching
US6083803A (en) 1998-02-27 2000-07-04 Micron Technology, Inc. Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances
JP2000216274A (ja) * 1999-01-26 2000-08-04 Seiko Epson Corp 半導体装置及びその製造方法
KR100792386B1 (ko) * 2006-09-29 2008-01-09 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460435A (en) * 1983-12-19 1984-07-17 Rca Corporation Patterning of submicrometer metal silicide structures
US4487652A (en) * 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4676869A (en) * 1986-09-04 1987-06-30 American Telephone And Telegraph Company At&T Bell Laboratories Integrated circuits having stepped dielectric regions
US4690728A (en) * 1986-10-23 1987-09-01 Intel Corporation Pattern delineation of vertical load resistor
JPH02210825A (ja) * 1989-02-10 1990-08-22 Hitachi Ltd プラズマエッチング方法及び装置
US4889588A (en) * 1989-05-01 1989-12-26 Tegal Corporation Plasma etch isotropy control
JPH04125924A (ja) * 1990-09-17 1992-04-27 Mitsubishi Electric Corp プラズマエッチング方法

Also Published As

Publication number Publication date
JPH0750284A (ja) 1995-02-21
JP2690860B2 (ja) 1997-12-17
US5509995A (en) 1996-04-23

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