KR960036129A - Field effect type semiconductor device and manufacturing method thereof - Google Patents

Field effect type semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR960036129A
KR960036129A KR1019960005896A KR19960005896A KR960036129A KR 960036129 A KR960036129 A KR 960036129A KR 1019960005896 A KR1019960005896 A KR 1019960005896A KR 19960005896 A KR19960005896 A KR 19960005896A KR 960036129 A KR960036129 A KR 960036129A
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diffusion layer
contact
semiconductor substrate
layer
channel
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KR1019960005896A
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Korean (ko)
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히데아키 구로다
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이데이 노부유키
소니 가부시기가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

LDD구조에 있어서의 고농도 확산층의 위치의 불균일에 기인하는 임계치전압의 변동을 없애서, 임계치전압의 불균일을 작게 한다.The variation of the threshold voltage due to the unevenness of the position of the high concentration diffusion layer in the LDD structure is eliminated, and the nonuniformity of the threshold voltage is reduced.

LDD구조에 있어서의 저농도 확산층(42)의 접합깊이가 채널부중에서 소스부에 접하고 있는 부분에 있어서의 공핍층(空乏層)(57)의 깊이방향의 폭보다 깊다. 그러므로 스페이서(46)의 폭의 불균일에 의하여, 고농도 확사층(52)의 위치가 채널길이방향으로 불균일해도, 이른바 포켓층으로서의 확산층(44)과 소스부측의 공핍층(57)과의 위치관계가 변동하지 않고, 임계치전압에 영향을 주는 소스부측이 공핍층(57)내에 있어서의 포켓층의 불순물량이 변동하지 않는다.The junction depth of the lightly doped diffusion layer 42 in the LDD structure is deeper than the depth in the depth direction of the depletion layer 57 in the portion of the channel portion that is in contact with the source portion. Therefore, even if the position of the high-concentration diffusion layer 52 is non-uniform in the channel length direction due to the unevenness of the width of the spacer 46, the positional relationship between the diffusion layer 44 as the pocket layer and the depletion layer 57 at the source- The impurity amount of the pocket layer in the depletion layer 57 does not fluctuate in the source side portion which affects the threshold voltage.

Description

전계효과형 반도체장치 및 그 제조방법Field effect type semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본원의 발명의 일실시예의 확대측단면도.1 is an enlarged side sectional view of an embodiment of the invention of the present application;

Claims (3)

반도체기판중의 채널부에 접하고 있는 상대적으로 저농도의 제1의 확산층과 상기 채널부와는 반대측에서 상기 제1의 확산층에 접하고 있는 상대적으로 고농도의 제2의 확산층으로 소스부 및 드레인부의 각각이 구성되어 있고, 상기 반도체기판과 동일 도전형이고 또한 이 반도체기판보다 불순물 농도가 높은 제3의 확산층이 상기 제1의 확산층에 접하여 상기 채널부에 배설되어 있는 매입채널형의 전계효과형 반도체장치에 있어서, 상기 제1의 확산층의 접합깊이가 상기 채널부에서 상기 소스부에 접하고 있는 부분에 있어서의 공핍층(空乏層)의 깊이방향의 폭보다 깊은 것을 특징으로 하는 전계효과형 반도체장치A first diffusion layer having a relatively low concentration in contact with a channel portion in the semiconductor substrate and a second diffusion layer having a relatively high concentration in contact with the first diffusion layer on the side opposite to the channel portion, And a third diffusion layer of the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate is disposed in the channel section in contact with the first diffusion layer, And a junction depth of the first diffusion layer is deeper than a width in a depth direction of a depletion layer in a portion of the channel portion in contact with the source portion. 반도체기판중의 채널부에 접하고 있는 상대적으로 저농도의 제1의 확산층과 상기 채널부와는 반대측에서 상기 제1의 확산층에 접하고 있는 상대적으로 고농의 제2의 확산층으로 소스부 및 드레인부의 각각이 구성되어 있고, 상기 반도체기판과 동일 도전형이고 또한 이 반도체기판보다 불순물 농도가 높은 제3의 확산층이 상기 제1의 확산층에 접하여 상기 채널부에 배설되어 있는 매입채널형의 전계효과형 반도체장치에 있어서, 상기 제1의 확산층의 접합깊이가 상기 제2의 확산층의 접합깊이 이상인 것을 특징으로 하는 전계효과형 반도체장치A first diffusion layer of a relatively low concentration in contact with a channel part of the semiconductor substrate and a second diffusion layer of a relatively high concentration in contact with the first diffusion layer on the side opposite to the channel part, And a third diffusion layer of the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate is disposed in the channel section in contact with the first diffusion layer, , And the junction depth of the first diffusion layer is not less than the junction depth of the second diffusion layer 반도체기판중의 채널부에 접하고 있는 상대적으로 저농도의 제1확산층과 상기 채널부와는 반대측에서 상기 제1의 확산층에 접하고 있는 상대적으로 고농도의 제2의 확산층으로 소수 및 드레인부의 각각이 구성되어 있고, 상기 반도체기판과 동일 도전형이고 또한 이 반도체기판보다 불순물 농도가 높은 제3의 확산층이 상기 제1의 확산층에 접하며 상기 채널부에 배설되어 있는 매입채널형의 전계효과형 반도체장치의 제조방법에 있어서, 투영비정(投影飛程)이 서로 다른 복수회의 이온중입에 의하여 상기 제1의 확산층을 형성하는 것을 특징으로 하는 전계효과형 반도체장치의 제조방법.The first diffusion layer having a relatively low concentration in contact with the channel portion in the semiconductor substrate and the second diffusion layer having a relatively high concentration in contact with the first diffusion layer on the side opposite to the channel portion are each constituted of a prime number and a drain portion And a third diffusion layer of the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate is disposed in the channel section in contact with the first diffusion layer, Wherein the first diffusion layer is formed by a plurality of ion inhomogeneities of the projection projections different from each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960005896A 1995-03-10 1996-03-07 Field effect type semiconductor device and manufacturing method thereof KR960036129A (en)

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JP7079525A JPH08250728A (en) 1995-03-10 1995-03-10 Field-effect semiconductor device and manufacturing method thereof
JP95-79525 1995-03-10

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Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926714A (en) * 1996-12-03 1999-07-20 Advanced Micro Devices, Inc. Detached drain MOSFET
US6025232A (en) * 1997-11-12 2000-02-15 Micron Technology, Inc. Methods of forming field effect transistors and related field effect transistor constructions
US5970353A (en) * 1998-03-30 1999-10-19 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
KR100269510B1 (en) 1998-05-20 2000-10-16 윤종용 Method for fabricating semiconductor device
US6251755B1 (en) * 1999-04-22 2001-06-26 International Business Machines Corporation High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe
TW449836B (en) * 1999-09-06 2001-08-11 Winbond Electronics Corp Manufacturing method and device for forming anti-punch-through region by large-angle-tilt implantation
US6635925B1 (en) * 1999-10-29 2003-10-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6974998B1 (en) 2001-09-19 2005-12-13 Altera Corporation Field effect transistor with corner diffusions for reduced leakage
US7092227B2 (en) * 2002-08-29 2006-08-15 Industrial Technology Research Institute Electrostatic discharge protection circuit with active device
US6882009B2 (en) * 2002-08-29 2005-04-19 Industrial Technology Research Institute Electrostatic discharge protection device and method of manufacturing the same
US7326998B1 (en) * 2002-11-14 2008-02-05 Altera Corporation Effective I/O ESD protection device for high performance circuits
KR100602113B1 (en) * 2003-12-31 2006-07-19 동부일렉트로닉스 주식회사 Transistor and manufacturing process thereof
US20060125121A1 (en) * 2004-12-15 2006-06-15 Chih-Hsin Ko Capacitor-less 1T-DRAM cell with Schottky source and drain
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US9577079B2 (en) * 2009-12-17 2017-02-21 Infineon Technologies Ag Tunnel field effect transistors
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US9875976B2 (en) * 2015-12-31 2018-01-23 Taiwan Semiconductor Manufacturing Company Ltd. Switching device
CN114551595B (en) * 2020-11-20 2023-10-31 苏州华太电子技术股份有限公司 Channel doping modulation RFLDMOS device applied to radio frequency amplification and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771012A (en) * 1986-06-13 1988-09-13 Matsushita Electric Industrial Co., Ltd. Method of making symmetrically controlled implanted regions using rotational angle of the substrate
US5102816A (en) * 1990-03-27 1992-04-07 Sematech, Inc. Staircase sidewall spacer for improved source/drain architecture
JP2907344B2 (en) * 1990-06-27 1999-06-21 株式会社東芝 Semiconductor device and manufacturing method thereof

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