KR960026413A - Method for forming gettering layer on silicon substrate - Google Patents

Method for forming gettering layer on silicon substrate Download PDF

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Publication number
KR960026413A
KR960026413A KR1019940038253A KR19940038253A KR960026413A KR 960026413 A KR960026413 A KR 960026413A KR 1019940038253 A KR1019940038253 A KR 1019940038253A KR 19940038253 A KR19940038253 A KR 19940038253A KR 960026413 A KR960026413 A KR 960026413A
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KR
South Korea
Prior art keywords
silicon substrate
implanted
substrate
argon ions
gettering layer
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Application number
KR1019940038253A
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Korean (ko)
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KR0151954B1 (en
Inventor
김광일
권영규
배영호
정욱진
Original Assignee
김만제
포항종합제철 주식회사
신창식
재단법인 산업과학기술연구소
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Priority to KR1019940038253A priority Critical patent/KR0151954B1/en
Publication of KR960026413A publication Critical patent/KR960026413A/en
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Publication of KR0151954B1 publication Critical patent/KR0151954B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

반도체소자의 제조에 있어서, 실리콘 기판에 혼입된 금속불순물등을 제거하기 위한 게터링층을 형성하는 방법이 제공된다. 이 방법은 실리콘 기판뒷면에 비정질층이 형성되도록 아르곤 이온을 주입하므로써, 고온 열처리에서도 결함회복이 늦은 아르곤 이온의 특성을 이용하여 기판뒷면에 결함층을 형성하여 금속불순물등을 제거한다.In the manufacture of a semiconductor device, a method of forming a gettering layer for removing metal impurities and the like incorporated in a silicon substrate is provided. In this method, argon ions are implanted so that an amorphous layer is formed on the back side of the silicon substrate, and thus, defects are formed on the back side of the substrate using the characteristics of argon ions, which are late in defect recovery even at high temperature heat treatment, to remove metal impurities.

Description

실리콘 기판에의 게터링층 형성방법Method for forming gettering layer on silicon substrate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 (a) 내지 (c)는 본 발명에 의한 방법을 실시하여 위한 공정의 일예를 단계적으로 나타낸 공정 개략도, 제2도는 (A)(B)는 각각 본발명의 방법에 따라 아르곤 이온을 사용한 경우와 종래의 실리콘 이온을 사용한 경우의 열처리 후 결함상태를 보여주는 단면투과전자 현미경사진이다.1 is a process schematic diagram showing an example of a process for carrying out the method according to the present invention step by step (a) to (c), and FIG. 2 (A) (B) is an argon ion according to the method of the present invention It is a cross-sectional transmission electron micrograph showing the defect state after the heat treatment in the case of using and conventional silicon ions.

Claims (4)

반도체소자의 제조방법에 있어서, 실리콘 기판의 일면에 아르곤 이온을 비정질층 형성 임계 도우즈량 이상으로 주입하는 단계 ; 상기 실리콘 기판의 반대면에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계 ; 상기 이온주입부위로 통해 기판내에 불순물을 주입하는 단계 ; 및 상기 기판을 질소분위기 하에서 고온으로 급속 열처리하는 단계 ; 를 포함하는 실리콘 기판에의 게터링층 형성방법.A method of manufacturing a semiconductor device, comprising: implanting argon ions into one surface of a silicon substrate in an amount greater than or equal to an amorphous layer formation threshold dose; Forming a SiO 2 oxide film on an opposite surface of the silicon substrate and etching away a portion into which ions are implanted; Implanting impurities into the substrate through the ion implantation site; And rapidly heat treating the substrate to a high temperature in a nitrogen atmosphere. A gettering layer forming method on a silicon substrate comprising a. 1항에 있어서, 상기 아르곤 이온을 1×1015∼1×1017/㎤범위의 도우즈량으로 주입함을 특징으로 하는 방법.The method of claim 1, wherein the argon ions are implanted in a dose of 1 × 10 15 to 1 × 10 17 / cm 3. 2항에 있어서, 상기 아르곤 이온을 2회이상 다중주입함을 특징으로 하는 방법.The method of claim 2, wherein the argon ion is multiplyed two or more times. 1 내지 3항 중 어느 한 항에 있어서, 상기 아르곤 이온을 가속전압 100keV 에서 1×1015/㎤ 도우즈량으로 주입됨을 특징으로 하는 방법.The method according to any one of claims 1 to 3, wherein the argon ions are implanted in an amount of 1 × 10 15 / cm 3 dose at an acceleration voltage of 100 keV. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038253A 1994-12-28 1994-12-28 Formation method of gattering layer in silicon substrate KR0151954B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038253A KR0151954B1 (en) 1994-12-28 1994-12-28 Formation method of gattering layer in silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038253A KR0151954B1 (en) 1994-12-28 1994-12-28 Formation method of gattering layer in silicon substrate

Publications (2)

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KR960026413A true KR960026413A (en) 1996-07-22
KR0151954B1 KR0151954B1 (en) 1998-12-01

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KR1019940038253A KR0151954B1 (en) 1994-12-28 1994-12-28 Formation method of gattering layer in silicon substrate

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328455B1 (en) * 1997-12-30 2002-08-08 주식회사 하이닉스반도체 Method of manufacuring a semiconductor device
KR100434960B1 (en) * 1996-10-02 2004-10-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device for trapping impurities using gettering layer
KR200466176Y1 (en) * 2007-11-15 2013-04-05 삼성전자주식회사 Refrigerator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100727262B1 (en) * 2006-08-30 2007-06-11 동부일렉트로닉스 주식회사 Method of forming metal in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434960B1 (en) * 1996-10-02 2004-10-14 주식회사 하이닉스반도체 Method for manufacturing semiconductor device for trapping impurities using gettering layer
KR100328455B1 (en) * 1997-12-30 2002-08-08 주식회사 하이닉스반도체 Method of manufacuring a semiconductor device
KR200466176Y1 (en) * 2007-11-15 2013-04-05 삼성전자주식회사 Refrigerator

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Publication number Publication date
KR0151954B1 (en) 1998-12-01

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