KR960015259A - Multiple Ethernet Bus Arbitration Processing System Using Backplane Board - Google Patents
Multiple Ethernet Bus Arbitration Processing System Using Backplane Board Download PDFInfo
- Publication number
- KR960015259A KR960015259A KR1019940026518A KR19940026518A KR960015259A KR 960015259 A KR960015259 A KR 960015259A KR 1019940026518 A KR1019940026518 A KR 1019940026518A KR 19940026518 A KR19940026518 A KR 19940026518A KR 960015259 A KR960015259 A KR 960015259A
- Authority
- KR
- South Korea
- Prior art keywords
- ethernet
- repeater
- board
- backplane
- arbitration processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40084—Bus arbitration
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
본 발명은 다중 이더넷 중계기 시스템과 관련된 것으로서, 종래에는 이러한 시스템에서 각각의 이더넷중계기보드에서 제각기의 이더넷중재기나 레벨비교회로 등을 구비하고 있기 때문에 그 시스템의 구성을 복잡하게 할 뿐만 아니라 시스템의 처리효율을 저하시킨다는 문제점이 있었다.The present invention relates to a multiple Ethernet repeater system, and in the related art, since each of the Ethernet repeater boards includes their respective Ethernet intermediators and level comparators, the system not only complicates the configuration of the system but also the processing efficiency of the system. There was a problem of lowering.
본 발명은 종래의 이러한 문제점을 개선할 수 있도록 통상의 이더넷중재기와 레벨 비교회로가 각기 중계기보드측에 구비되어져 있지 않고 이더넷중계기콘트롤러(31)만 구비되어져 있는 다수의 중계기보드(3)와, 이 중계기보드(3)측의 이더넷중계기콘트롤러(31)와 연결되어져서 버스사용 중재 처리를 공통으로 처리하여 줄 수 있는 백플레인중재로직(41)를 갖는 백플레인보드(40)와의 관련 구성으로 이루어져 있는 다중 이더넷 중재 처리시스템을 제공하는데 있다.The present invention provides a plurality of repeater boards (3), each of which is equipped with only an Ethernet repeater controller (31) without a conventional Ethernet intermediator and a level comparison circuit on the side of the repeater board, so as to improve such a conventional problem. This is connected to the Ethernet repeater controller 31 on the side of the repeater board 3, and is composed of a related configuration with the backplane board 40 having a backplane mediation logic 41 which can handle bus arbitration processing in common. To provide an Ethernet arbitration processing system.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명에 의한 이더넷 버스 중재 로직의 시스템 회로 블럭도.2 is a system circuit block diagram of Ethernet bus arbitration logic in accordance with the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940026518A KR0158940B1 (en) | 1994-10-17 | 1994-10-17 | Multiple ethernet bus arbitration processing system using back-plane board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940026518A KR0158940B1 (en) | 1994-10-17 | 1994-10-17 | Multiple ethernet bus arbitration processing system using back-plane board |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960015259A true KR960015259A (en) | 1996-05-22 |
KR0158940B1 KR0158940B1 (en) | 1999-02-18 |
Family
ID=19395237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940026518A KR0158940B1 (en) | 1994-10-17 | 1994-10-17 | Multiple ethernet bus arbitration processing system using back-plane board |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0158940B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100334417B1 (en) * | 1999-11-22 | 2002-05-03 | 석한진 | Backplane system with a point-to-point bus architecture |
-
1994
- 1994-10-17 KR KR1019940026518A patent/KR0158940B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0158940B1 (en) | 1999-02-18 |
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