KR960007637B1 - Method for programming a memory device which is compatible with pin and nonprogrammable - Google Patents

Abstract

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Description

Program method of a memory device usable as non-programmable memory and pin compatible with it

1A is an outer plan view of a non-programmable basic buffer chip with input and output pins applied to embodiments of the present invention.

1B is an outer plan view of a programmable basic buffer chip with input and output pins applied to an embodiment of the invention.

2 is an illustration of two program registers provided in a programmable buffer chip in accordance with one embodiment of the present invention.

3 is a timing diagram in an embodiment in which a process relating to a programming method according to the present invention is disclosed.

4A is a timing diagram showing active and inactive states of a nearly filled flag according to program information input to a programmable buffer chip.

4B is a timing diagram showing the activation and deactivation of a nearly empty flag according to program information input to a programmable buffer chip.

5 is a block diagram showing a structural arrangement of a programmable buffer chip according to an embodiment of the present invention; and

6 is a block diagram showing a structural arrangement of a programmable buffer chip according to another embodiment of the present invention.

The present invention relates to a programmable buffer fabricated on a single integrated circuit chip and a programming method thereof.

A buffer is a storage device commonly used for data transfer, where data elements can be written into a buffer from one information source and read out from another information source. Programmable or impossible, a buffer built on a single chip is called a buffer chip, and the buffer communicates with the external environment through the input and output pins of the buffer chip in which the buffer is integrated. Generally, the buffer chip has a designated buffer status pin that indicates any checked buffer status, such as full, empty, half-full, and so on. Programmable means that a particular buffer state, which is checked at any buffer status pin and displayed in the external environment, can be changed by external selection. The procedure for entering program information is called programming. The buffer chip is programmed by inputting program information to the buffer chip. Programmable means that the user of the buffer chip can change the checked buffer state according to the special requirements of the application environment in which the buffer chip is configured. Without programming, the buffer state being checked cannot be changed, limiting the usefulness of the buffer chip.

Programmable buffer chips are conventionally known. Programmability per se is not a subject of the present invention but rather the invention relates to a special programming method and to a programmable buffer chip by the method for eliminating the major disadvantages common to all conventional programmable buffer chips. The main disadvantage of conventional programmable buffer chips is the compatibility problem, i.e. backward compatibility with non-programmable buffer chips.

In the context of the present invention, interchangeability means interchangeability. If a non-programmable buffer chip can be removed at that position in the original circuit and replaced with a pin-to-pin with a programmable buffer chip without causing a malfunction in the original circuit, the programmable buffer chip is a non-programmable buffer chip. Compatible with The original circuit will then continue to operate as if it had a programmable buffer chip. In that sense, compatibility is slow to progress as more advanced buffer chips with programming features are compatible with basic buffer chips without programming features. Nevertheless, so far compatibility has never been achieved. There are no known conventional buffer chips that are compatible with non-programmable basic buffer chips having the same number of functional input and output pins.

The use of conventional dedicated programming pins is one reason why compatibility could not be realized in the past. The dedicated programming pin indicates that the signal applied to that pin is entirely related to the programming of the buffer chip. If such dedicated programming pins exist on a programmable buffer chip, a lot of debate may arise if the programmable buffer chip is replaced by a non-programmable basic buffer chip. In other words, there will be situations where the original system may signal a dedicated programming pin that does not match the number of pins or that is not intended to operate as a programmable buffer chip. In either case, the system will not be able to get a proper response from the replaced buffer chip.

It is therefore an object of the present invention to provide a method for programming a programmable buffer chip that can achieve compatibility between a programmable buffer chip and a non-programmable basic buffer chip having the same number of input and output pins.

It is still another object of the present invention to provide a programmable buffer chip capable of achieving compatibility between a programmable buffer chip and a non-programmable basic buffer chip having the same number of input and output pins.

The method of the present invention for achieving the above object creates a time period that looks like an extended reset period so that it is added at the end of the actual reset period. Program information is input to the buffer chip during the changed time period to program the buffer chip. The program information selects buffer states to be checked. The checked states are indicated by at least one buffer status pin.

The programmable buffer chip according to the invention also receives program information for an extended period of time at the end of a normal reset period which appears to be an extension of the reset period.

The present invention is based on the presence of reset characteristics in non-programmable basic buffer chips. The basic buffer chip enters the reset mode for a minimum duration of a predetermined period in a reset operation performed to return the buffer chip to a predetermined initial condition (for example, setting a flag indicating that the buffer is empty). Answer After that period, the basic buffer chip responds to a reset-release signal that terminates the reset mode to perform normal non-reset buffer operation to receive, store and output data components. The period provided for reset should be sufficient to terminate the reset operation.

According to the present invention, when a reset signal is generated, the programmable buffer chip enters a reset mode of a predetermined period sufficient to perform a reset operation. The reset-release signal is not applied to the programmable buffer chip for the next time period following the reset period, but at the end of the next time period. Thus the next time period is added to the end of the actual reset period and looks like an extension of the reset period. The programmable buffer is programmed during that changed time period, just as program information is entered into the buffer chip during the reset period.

Since the programming method described above is a modified extension of the reset period, it is necessary to perform a reset operation on the buffer chip every time the buffer chip is programmed. According to another embodiment of the present invention, the actual reset operation is inhibited during the normal reset period before the changed period for programming so that the programmable buffer chip will not be involved in the reset operation each time it is to be programmed.

According to the present invention, the compatibility between the programmable buffer chip and the non-programmable basic buffer chip in the original system to operate with the basic buffer chip is pin for pin. Is realized. There will be no controversy about the replacement because the original system will not attempt to extend the extended time period to the end of the normal reset period or to enter the program information into the buffer chip for an extended time period that appears to be an extension of the reset period. will be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1A shows a basic buffer chip 2 which is not programmable. The basic buffer chip 2 has a plurality of input / output pins, and only a part thereof is shown in FIG. 1a. P1 is a read control pin that initiates a read operation. Read ( Signal is applied to the P1, and the read Initializes the read operation of the buffer when the signal goes low. P2 is a write control pin for initializing the write operation. entry( Signal is applied to the P2, and When the signal goes low, the write operation is initiated. P3 is a reset control pin for initializing a series of reset operations in the buffer chip 2, Signal is applied to P3.

The reset ( Signals play two functional roles. That is, reset ( When the read and write control signals applied to P1 and P2 when the signal is low are high at that time, they perform a reset operation by arranging the buffer chips in the reset mode. The reset cycle starts with the application of the reset signal. Also reset ( When the signal transitions high, it acts as a reset-release signal that terminates the reset mode, causing the buffer chip to exit the reset mode to perform normal non-reset buffer operation.

P4 through P12 are data input pins for 9 bit data words, and P18 through P26 are also data output pins for 9 bit data words. P14 is a control signal pin that has no functional meaning during the time the base buffer is in reset mode to perform a reset operation and may be one of a number of control pins on the base buffer chip. P15, P16, and P17 are buffer status pins that check for a certain buffer status by the signal level present at that pin. P15 checks that the buffer is full by outputting a predetermined signal level when the buffer is full, and P16 checks that the buffer is half full by outputting a predetermined signal level when more than half of the buffer position is subscribed but not yet read. Check the (half-full) state. In addition, P17 checks the empty state of the buffer by outputting a predetermined signal level when the buffer is empty. In the basic buffer chip 2, the buffer full, half full and empty states are fixed and cannot be changed, so the basic buffer chip 2 is not programmable.

The above-described basic buffer chip performs a first-in-first-out (FIFO) operation of data transfer. The data elements are read from the buffer in the buffer chip and output from the buffer chip in the same operation as input to the buffer chip and written to the buffer chip. If no data element has been written to the buffer, or if all data elements written to the buffer have been read, the buffer is considered empty. If all locations in the buffer are filled with data elements and none of them have been read, the buffer is considered filled. If there are more than half data elements written to the buffer but not yet read, the buffer is considered half full.

1B shows a programmable buffer chip 4. The programmable buffer chip 4 has the same number of input and output pins in the same physical arrangement as the basic buffer chip 2. Each pin of the basic buffer chip 2 has a corresponding pin on the programmable buffer chip 4. As with the basic buffer chip 2, the programmable buffer chip 4 has a read control pin P1, a write control pin P2, a reset control pin P3, a data input pin P4-P12, and a buffer status pin P15-P17 (modified by programming). Data output pins P18-P26 and data indicator pins P14.

The data indicator pin P14 in the programmable buffer chip is used to perform the characteristic of selectively inputting program information to the chip from one of two sets of input / output pins. One level signal applied to pin P14 indicates that data input pins P4-P12 are used for inputting the program information, and another level signal means that P18-P26, which is a constant data output pin, is used for inputting the program information. do. As mentioned above, in the basic buffer chip, the corresponding pin P14 has no functional meaning during the reset mode, so the use of pin P14 for programming by the programmable buffer chip is performed if programming is performed while the buffer chip is in the reset mode. If possible, it is compatible with the basic buffer chip. In another embodiment in which the role of the pin used to input program information is fixed, the data indicating pin P14 need not be provided to select the pin and may have the same function as that of the corresponding pin in the basic buffer chip.

In programmable buffer chip 4, P15 is an almost-full state defined as being full, except for a few positions defined by offset values input by the user into the buffer chip as part of the program information. Can be used to check. P17 can also be used to check an almost-empty state in which the buffer is defined as empty, except for a few positions defined by offset values input to the buffer chip as part of the program information. P16 can be used to check whether the buffer is half full, or if the buffer is full or empty, by an indication in the program information input to the buffer chip. When P16 is used to check whether the buffer is full or empty, this state represented by P16 can be determined by checking the nearly full state represented by P15 or the almost empty state represented by P17. If the buffer is almost full, the affirmative indication at P16 should be interpreted by the environment as it is filled. Likewise, if the buffer is nearly empty, the check mark at P16 will be empty and should be interpreted by the environment. Simple gating logic is used to make such an interpretation. The program information may also include an indication in which pins P15, P16 and P17 are to be checked for the same condition as that checked by pins P15, P16 and P17 of the basic buffer chip.

Although the physical pin arrangement between the basic buffer chip 2 and the programmable buffer chip 4 is the same, the specific arrangement shown in FIGS. 1A and 1B is solely for illustrative purposes. In order to achieve compatibility where the programmable buffer chip can replace the default buffer chip in a system that is not intended for programming, a programming method, i.e., a pin that already exists on the basic buffer chip for inputting program information into the programmable buffer chip. Only need a way to use.

Program information implemented in the preferred embodiment of the present invention is in the form of two 9-bit program instructions. The first instruction is allocated 7 bits to define the offset (first offset data) for the nearly filled state and each offset increment corresponds to a two byte offset in the buffer. Therefore, if the first offset of the instruction corresponds to a state in which the buffer is filled except for 2 bytes of data, the nearly filled state may range from the actually filled state to 127 × 2 bytes. Similarly, the second instruction is assigned 7 bits to define the offset (second offset data) for the buffer being empty and each offset increment corresponds to a two byte offset in the buffer. Therefore, if the first offset in the instruction corresponds to the empty state except for 2 bytes of data, the almost empty state may range from the actual empty state to 127 × 2 bytes. Depending on the size of the buffer itself, more or fewer offset numbers are desirable in the instruction. Seven offset bits are appropriate for each instruction for the 1K x 9-bit first in, first out (FIFO) and six offset bits for each instruction for the 512K x 9-bit first in, first out (FIFO). Also, how many bytes correspond to each offset increase depends on the application environment and may be changed by other embodiments.

2 shows the first and second program instructions. The first program instruction is stored in a full flag program register and the second program instruction is stored in an empty flag program register in the programmable buffer chip 4 of FIG. These program registers are used to receive and store program information. Since the basic buffer chip 2 is not programmable, it will not contain any program registers, such as for storing program information. The program registers, each storing a 9-bit program instruction, consist of 9 bits. The full flag program register operates to store a first instruction that contains offset information for an almost filled state (first offset data), and an empty flag program register is offset for an almost empty state (second offset data). Operate to store a second instruction containing information.

Bit 7 (the eighth bit counting from bit 0) of the first and second program instructions is reserved for the next offset extension. Until then bit 7 is not used and may contain a dummy bit.

Bit 8 (the ninth bit counted from bit 0) of the first program instruction (hereinafter referred to as the program instruction bit) is the default value for checking one or more of the same states as those checked by the basic buffer chip 2. Is determined to be set. In the exemplary embodiment of the present invention, when the program instruction bit is low, P15 indicating the buffer is full, P16 indicating the buffer is half full, and P17 indicating the empty buffer, as in the case of the basic buffer chip. This means that the programmable buffer will respond with a program instruction bit. If the program instruction bit is high, the program buffer chip is almost empty according to the second offset data in the second instruction word of program information, P15 which indicates the state is almost filled according to the first offset data in the first instruction word of the program information. You will want to use P17 to indicate the state and P16 to indicate the filled and empty states. The confirmation of the state indicated when P16 is used to indicate a filled and empty state can be determined by examining P15 and P17. If a nearly full state is provided by P15, you will try to use P16. The confirmation of the state indicated when P16 is used to indicate a filled and empty state can be determined by examining P15 and P17. If a nearly filled state is provided at P15, a confirmatory indication at P16 will indicate the filled state. If an almost empty state is provided at P17, a check mark at P16 will indicate an empty state. As such, if the program instruction bit is high, four states are checked: nearly full, nearly empty, filled, empty, and empty states are represented by the same buffer status pin.

In another embodiment, the program indication bit determines only that P16 performs a function in the same way only in the case of a basic buffer chip. Whether P15 represents a nearly filled state or a default value is set to indicate a filled state such as P15 of the basic buffer chip depends on the first offset data value. Also, whether P17 represents an almost empty state or to represent an empty state such as P17 of the basic buffer chip depends on the second offset data value. If the first offset data is zero, the programmable buffer chip will respond by executing P15 to indicate the filled state (as in the case of the basic buffer chip). If the first offset data is not zero, the programmable buffer chip will automatically respond by executing P15 to indicate an almost filled state with an offset defined by the first offset data. If the second offset data in the second program is zero, the programmable buffer chip will respond by executing P17 to indicate an empty state (as in the case of the basic buffer chip). If the second offset data is not zero, the programmable buffer chip will automatically respond by executing P17 to indicate an almost empty state with an offset defined by the second offset data. Of course in this embodiment the programmable buffer chip has a logic circuit for examining the value of each offset data and the combination of the program indication bit, the first offset data and the second offset data are all the same or checked against the basic buffer chip. Indicates whether different buffer states are checked by the corresponding pin on the base buffer chip.

Bit 8 (the 9th bit counting from bit 0) of the second program instruction is a reset inhibit indication bit whether the programmable buffer chip will abort its reset operation at the next time it should effectively transition to a reset operation. . The meaning of that feature will become apparent in light of the following discussion of this specification. The reset prohibit indication bit is optional to prevent the buffer from resetting every time the programmable buffer chip is programmed. In another embodiment where the option is not provided, the reset prohibit indication bit is not included in the program information.

In order to facilitate a proper understanding of the programming method according to the invention, a reset specification of the basic buffer chip 2 is first described.

Reset means that the buffer is initialized to a predetermined state in preparation for receiving a new batch of data elements. For example, if the buffer is half full after receiving the first batch of data elements, the reset will return the buffer to its initial state as if the buffer had no empty data elements written to it and is now empty. After reset, the buffer can receive a new batch of data elements at any time. If a pointer is used in the buffer to point to a location in the buffer relative to the current state of the buffer, the pointer will be initialized to a state related to the initial buffer state.

When the reset signal is applied to the pin P3 in the basic buffer chip 2, the read and write signals ( ) And ( When is high, the buffer chip is arranged in reset mode and starts a series of reset operations. After a sufficient period of time has elapsed to complete the reset operation, a reset-reset signal is applied to pin P3 to terminate the reset mode by causing the buffer chip to exit reset mode to perform normal non-reset buffer operation. .

The programming method according to the invention depends on the way the basic buffer chip enters and exits the reset mode. The reason is that a programmable buffer chip having a programming method according to the present invention and to be used would have to perform the same mechanism to enter and exit the reset mode if backward compatibility with the basic buffer chip would be realized.

The programming method according to the invention adds an extended time period to the end of the reset period as if it were an extension of the reset period. Although the reset operation has already been completed, the chip remains idle as if it were being reset, while the program information is input to the programmable buffer chip for that radius of time. In that way the input of program information makes the programmable buffer chip compatible with the corresponding non-programmable base buffer chip. This is because when a programmable buffer chip is placed in an environment designed for a basic buffer chip, the circuits in that environment will not create a modified reset extension period that will be added at the end of the normal reset cycle, or attempt to enter program information during that cycle. to be. Without a reset reset extension period for programming, the programmable buffer chip behaves as if it is not programmable.

3 is a timing diagram showing a series of steps to be taken to input program information into the programmable buffer chip 4 in the form of two program instructions. Initially, reset ( ) Signal, read ( ) Signal, write ( The signals are all high. reset( When the signal transitions to the low state, the sequence of reset operations is started in the programmable buffer chip 4 as in the case of the basic buffer chip 2. The minimum duration of a given period is required for the reset operation to be performed, which is shown as Trs in FIG. Typically, a reset-release signal (a reset that inverts to a high state) at the end of the period Trs in the basic buffer chip. Signal is applied to pin P3 to terminate the reset mode. However, in order to input the program information into the programmable buffer chip 4, the application of the reset-release signal is delayed over the extended period text past the period Trs. The cycle text is a modified extended reset cycle during which program information is input to the programmable buffer chip. As shown, the text extends at the end of the normal reset period Trs. Read during the period Text ( Signal transitions to a low state to alert the programmable buffer chip 4 to which program information is about to be input, and then transitions to a high state. In other embodiments, some other signal may be needed for this purpose. However, it is only necessary to warn any signal after the period Trs to be alert to the programmable buffer chip of the first and second program instructions being input. Then, the first and second program instructions are sequentially input to the programmable buffer chip 4.

Write for each command ( The signal first transitions to a low state before the command is entered, then remains low for a while and then transitions back to its initial state in preparation for a low state transition. Fill in like this The signal toggles twice, one of which is for entering each program command. As already mentioned, the first program instruction contains offset information associated with the buffer in a nearly full state and is stored in the full buffer flag register. The second program instruction contains offset information associated with a buffer that is nearly empty and is stored in the empty buffer flag register. In another embodiment, the order of the first and second program instructions may be reversed.

In one embodiment of executing the data indicating pin P14, the instruction signal DIR is written during the text period. It is applied to the data indicator pin P14 just before the first toggling of the signal. In this way, the state of the DIR signal will inform the programmable buffer chip 4 so that the pins of P4-P12 or P18-P26 will pass the program command to be input to the programmable buffer chip 4. In one embodiment, the logic low state selects pins P4-P12 and the high state selects P18-P26, and in another embodiment, the selection can be reversed.

As described above, the program information is input to the programmable buffer chip 4 during the modified extended text period of the normal reset period. In certain embodiments the input is read ( Send the signal low and indicate ( The signal is applied to pin P14, followed by inputting the first program commander and writing a second program command (command entered via the data entry / exit pin selected by the signal at pin 14). Toggling the signal.

According to the embodiment described above, the programmable buffer chip also performs a reset operation during the period Trs before the period text every time it is programmed. It may not be desirable. In another embodiment, program information may be made to include an indication of whether the programmable buffer chip will stop initiating a reset operation. Bit 8 (the 9th bit counting from bit 0) of the second program instruction is used for that purpose. One state of bit 8 indicates that there is no reset operation in the next Trs period with the programmable buffer chip 4, and another state of bit 8 indicates that there is no reset operation in the programmable buffer chip 4 in the next Trs period. Indicates that

As described above, when the basic buffer chip transitions to the low state, A different reset may be performed by any other basic buffer chip, even if it includes a single reset pin to which the signal and a reset-release signal transitioning to a high state are applied. Programmable buffer chips that are compatible with a basic buffer chip that includes a isolation pin for receiving reset and reset-release signals will have to have that isolation chip.

Figure 4a shows the assertion and deassertion of the Almost Full Flag AFF in accordance with the preferred embodiment of the present invention, and Figure 4b shows the Almost Empty Flag AEF. The active and inactive states are shown. For convenience of explanation, the two byte offsets are assumed to be almost filled and nearly empty (each offset increase in the first and second offset data corresponds to an offset of two bytes in the buffer).

Write during normal buffer operation Each time the signal transitions low, a write cycle for the data component, that is, a byte of data is initialized and The signal transitions high before the next write cycle is initiated. The data byte is written to the buffer chip during the write cycle and the write cycle ends when the data components are written out. It also reads during normal buffer operation. Each time the signal transitions low, a read cycle for the data component, that is, a byte of data is initialized and The signal transitions high before the next read cycle is initiated. During the read cycle, data bytes are read from the buffer and the read cycle ends when the data components are read.

As shown in Fig. 4A, writing ( When the signal transitions low to the second to last available buffer position before the buffer is filled, the nearly filled flag AFF transitions to the low state to store that data element. In this embodiment, the low state AFF signal indicates that the buffer is almost full. If the program information specifies that a nearly full state will be monitored and displayed, the AFF flag will need to be applied to the corresponding buffer status pin. entry( The arrow pointing from the falling edge of the signal to the falling edge of the AFF signal indicates that the write signal causes the AFF signal. entry( At the end of the two write cycles from the low state that caused the active state of the flag to almost full, the buffer is filled if no read cycles intervene. Then, after the buffer is filled, the second read ( When the signal transitions to the high state, the AFF transitions to the high state and becomes inactive. The second read after the buffer is filled ( The arrow pointing from the rising edge of the signal to the rising edge of the AFF indicates that the read signal causes the AFF signal. The AFF is inactive if no write cycle is inserted at the end of two read cycles after the buffer is filled.

As shown in Figure 4b, When the signal transitions low for the last buffer position that contains the data element that has not yet been read in the second, the nearly empty flag AEF transitions low. In this embodiment, the low state AEF signal indicates that the buffer is almost empty. If the program information specifies that an almost empty state will be checked and displayed, the AFF flag will be applied to the buffer status pin. Read ( The arrow pointing from the falling edge of the signal to the falling edge of the AFF signal indicates that the read signal causes the AEF signal. Read ( At the end of the two read cycles from the time the signal went low, resulting in the active state of the nearly empty flag, the buffer is empty if no read cycles are involved. Then the second write after the buffer is filled ( When the signal transitions to the high state, the AEF transitions to the high state and becomes inactive. Second write after the buffer is filled The arrow pointing from the rising edge of the signal to the rising edge of the AEF indicates that the write signal causes the AEF signal. The AEF is inactive if no read cycles intervene at the end of two write cycles after the buffer is empty.

5 is a block diagram showing the structural arrangement of a programmable buffer chip according to an embodiment of the present invention, which is intended to be programmed by the above-described programming method of the present invention. The buffer / buffer control unit 20 is provided with a cellarray storing data components and a corresponding access control circuit for reading out from the buffer and writing to the buffer. The status monitor / flag generator 22 represents a circuit that monitors the status of the buffer in accordance with program information input to the buffer chip and provides a corresponding indication to the buffer status pin. The program storage unit 24 is a circuit that receives the program information during the period in which the buffer chip is programmed, and then stores the received program information. As described above, the first and second program registers are located in the program storage section 24 of the buffer chip. The reset / reset-release section 26 operates to reset the buffer chip in response to an applied reset signal located on the buffer chip in the reset mode, and performs a normal non-reset buffer operation in response to the applied reset-release signal. In order to prevent the buffer chip from the reset mode is shown. The reset operation may include initializing a pointer in the status monitor / flag generator 22 indicating some current position in the buffer and initializing any access circuit in the buffer / buffer control unit 20. The connection between the reset / reset-release section 26 and the program storage section 24 is executed by the program storage section 24 during the period starting from the end of a normal predetermined reset period and ending at the application of the reset-release signal. Indicates to operate to receive.

6 is a block diagram showing the structural arrangement of a programmable buffer chip according to another embodiment of the present invention, which is intended to be programmed by the above-described programming method of the present invention. The configuration is the same as that shown in FIG. 5 except that a reset prohibition function in the reset / reset-release section 26 and a data indicating signal applied to the program storage section 24 are added. The reset prohibit function is performed by the corresponding circuit in block 26 responsive to the display of the program information stored in the program store 24 to prevent a reset that may otherwise occur upon the generation of the next reset signal. In this embodiment, the program storage section 24 uses one of two types of data pins indicated by the data indication signal to receive program information in response to the data indication signal.

For those of ordinary skill in the art, the block components in the block diagrams of FIGS. 5 and 6 may be easily implemented using conventional logic circuits and thus are not described in more detail. In addition, the exact circuit for each block component may be applied differently according to the configuration and the configuration of other block components. The programmable buffer chip according to the present invention can be easily configured by those skilled in the art in view of the programming method as described above. For example, a counter or comparator can be used to let the buffer know how many buffer locations are written and read, and a reset can be realized by storing a certain value in a counter that identifies the next location whose contents are to be written or read. have.

Although the present invention has been described with reference to the drawings and described with reference to the embodiments above, the present invention is not limited thereto, and various changes and modifications can be made without departing from the basic definition of the present invention. Anyone with ordinary knowledge will know it clearly.

Claims (26)

Program lock with data storage means, at least one flag program register, a compatible input data pin, a compatible output data pin, a compatibility condition / status pin, a compatible read / write control pin, and a compatible reset pin. A method of writing program information to a program function memory device that is pin compatible and functionally compatible with a memory device designed for use as a memory device, the method comprising: at least said first memory device being set to a reset mode for a first duration of time; Applying an activation reset clock having a one duration to the compatible reset pin; Maintaining the reset clock in an active state during the second sustain period, wherein the memory device is set to a program mode during a second sustain period after the first sustain period; During said second duration, inputting at least a first activation enable signal to one of said compatible read / write control pins; Inputting at least an area of the program information through the compatibility input pin and the compatibility output pin during the second duration; During the second duration, storing the program information in the at least one flag program register; Inputting a second activation enable signal to one of the compatible read / write control pins after the second duration; Inputting program fixed data into the data storage means through the compatibility input pin when the second activation enable signal corresponds to a write operation; Outputting program fixed data from said data storage means via said compatible input pin when said second activation enable signal corresponds to a read operation; Outputs through the compatibility condition / status pin in response to the second enable enable signal a data buffer condition / status data defined in a flag program register that provides a programmable request status of data currently stored in the data storage means. And the programmable memory device is reset in response to a first value of a programmed bit currently stored in the at least one flag register during the reset mode, wherein the programmable memory device is configured to reset the program bit value. And not reset during the reset mode when not the first value. Program lock with data storage means, at least one flag program register, a compatible input data pin, a compatible output data pin, a compatibility condition / status pin, a compatible read / write control pin, and a compatible reset pin. A method of writing program information to a program function memory device that is pin compatible and functionally compatible with a memory device designed for use as a memory device, the method comprising: at least said first memory device being set to a reset mode for a first duration of time; Applying an activation reset clock having a one duration to the compatible reset pin; Maintaining the reset clock in an active state during the second sustain period, wherein the memory device is set to a program mode during a second sustain period after the first sustain period; During said second duration, inputting at least a first activation enable signal to one of said compatible read / write control pins; Inputting at least an area of the program information through the compatibility input pin and the compatibility output pin during the second duration; During the second duration, storing the program information in the at least one flag program register; After the second duration, inputting a second enable enable signal to one of the compatible lead / write control pins; Inputting program fixed data into the data storage means through the compatibility input pin when the second activation enable signal corresponds to a write operation; Outputting program fixed data from said data storage means via said compatible input pin when said second activation enable signal corresponds to a read operation; Outputs through the compatibility condition / status pin in response to the second enable enable signal a data buffer condition / status data defined in a flag program register that provides a programmable request status of data currently stored in the data storage means. And the at least first activation enable signal further comprises a data direction signal for selectively determining an input direction of the program information through the compatibility input pin or the compatibility output pin. Way. The reset mode is written in response to the reset signal for the programmable buffer chip and the reset, and thereafter the compatibility between the program fixed basic buffer chips with the same number of input and output pins in response to the reset release signal to exit the reset mode. A method for writing a program information determining factor of a buffer state condition sensed by at least one buffer status pin in a period converted into an extended period for an extended reset to obtain, Writing a reset signal to the programmable buffer causing the buffer chip to write the reset mode for a period of a predetermined minimum delay period reset to an initial state; Blocks the buffer chip from applying a reset release signal to the programmable buffer chip that sets the normal mode into a reset fixed buffer operation, thus converting it into an extended reset period for writing program information to the programmable buffer chip. Creating an established time window; Inputting program information to the programmable buffer chip during the converted reset period to determine the selection of a buffer state condition sensed by the at least one buffer status pin when the programmable buffer chip is in the normal mode; ; Applying the reset release signal to a programmable buffer chip after the input operation, thereby setting the programmable buffer chip into a normal mode, such that the programmable buffer chip is compatible with the buffer chip, The program information area indicates whether the programmable buffer chip is blocked from writing a reset mode to be set in the reset operation in response to the occurrence of the reset signal, and the program information stored in the programmable buffer chip is blocked. And the programmable buffer chip is operable to block writing of the reset mode in response to the next generation of the reset signal. The reset mode is written in response to the reset signal for the programmable buffer chip and the reset, and thereafter the compatibility between the program fixed basic buffer chips with the same number of input and output pins in response to the reset release signal to exit the reset mode. A method for writing a program information determining factor of a buffer state condition sensed by at least one buffer status pin in a period converted into an extended period for an extended reset to obtain, Writing a reset signal to the programmable buffer causing the buffer chip to write the reset mode for a period of a predetermined minimum delay period reset to an initial state; Blocks the buffer chip from applying a reset release signal to the programmable buffer chip that sets the normal mode into a reset fixed buffer operation, thus converting it into an extended reset period for writing program information to the programmable buffer chip. Creating an established time window; Inputting program information to the programmable buffer chip during the converted reset period to determine the selection of a buffer state condition sensed by the at least one buffer status pin when the programmable buffer chip is in the normal mode; ; Applying the reset release signal to a programmable buffer chip after the input operation, thereby setting the programmable buffer chip into a normal mode, such that the programmable buffer chip is compatible with the buffer chip, The input step determines whether program information is to be input through a data pin that is used differently to input data arguments into the buffer memory during normal mode or through a data pin that is used differently to output data arguments from the buffer memory during normal mode. And applying a direction signal indicating whether or not to said programmable buffer chip, said direction signal corresponding to said control pin in said basic buffer chip having no functional significance during a reset of a basic buffer chip. Is applied to the pin of the mouth The programmable information during the writing step is program information, it characterized in that the input through the pin indicated by the direction signal. The reset mode is written in response to the reset signal for the programmable buffer chip and the reset, and thereafter the compatibility between the program fixed basic buffer chips with the same number of input and output pins in response to the reset release signal to exit the reset mode. A method for writing a program information determining factor of a buffer state condition sensed by at least one buffer status pin in a period converted into an extended period for an extended reset to obtain, Writing a reset signal to the programmable buffer causing the buffer chip to write the reset mode for a period of a predetermined minimum delay period reset to an initial state; Blocks the buffer chip from applying a reset release signal to the programmable buffer chip that sets the normal mode into a reset fixed buffer operation, thus converting it into an extended reset period for writing program information to the programmable buffer chip. Creating an established time window; Inputting program information to the programmable buffer chip during the converted reset period to determine the selection of a buffer state condition sensed by the at least one buffer status pin when the programmable buffer chip is in the normal mode; ; Applying the reset release signal to a programmable buffer chip after the input operation, thereby setting the programmable buffer chip into a normal mode, such that the programmable buffer chip is compatible with the buffer chip, The program information includes a special indication of whether the same or different buffer state detected by at least one buffer status pin of the basic buffer chip is detected by the buffer status pin of the corresponding programmable buffer chip, respectively. How to fill out program information. 6. The method of claim 5, wherein the programmable buffer chip and the two buffer memories in the basic buffer chip maintain data transfer of a first-in first-out sequence. 7. The method of claim 6 wherein the reset signal is a signal level applied to a reset pin of a programmable buffer chip; And the reset release signal is another signal level applied to the reset pin of the programmable buffer chip. 6. The method of claim 5 wherein the basic buffer chip comprises two buffer status pins and the programmable buffer chip comprises two corresponding buffer status pins; A first state pin of the basic buffer chip indicates a buffer pool condition; A second state pin of the basic buffer chip indicates a buffer empty condition; When the special indication indicates that the same buffer state condition sensed by the first and second state pins of the basic buffer chip is detected by the corresponding first and second state pins of the programmable buffer chip, the programmable buffer The first state pin of the chip indicates a buffer pool condition; And a second state pin of the programmable buffer chip indicates a buffer empty condition. 9. The method of claim 8, wherein a buffer state condition is different from that detected by the first and second state pins of a basic buffer chip to a corresponding first and second state pin of a programmable buffer chip. Indicate a buffer all-most pool state in which the buffer is full except for a plurality of areas indicated by the first offset data included in the program information, when indicating that the detection is performed by the program information; And a buffer indicates an empty status of an empty buffer, except for a plurality of areas represented by second offset data included in the program information. 10. The apparatus of claim 9, wherein the basic buffer chip comprises a third buffer status pin and the programmable buffer chip comprises a corresponding third buffer status pin; The buffer status pin of the basic buffer chip senses a buffer condition intermediate a full condition empty condition; When the special indication indicates that the special indication is detected by a corresponding buffer status pin of a programmable buffer chip of the same buffer status condition as that detected by the third buffer status pin of a basic buffer chip. And a status pin detects a condition identical to a condition sensed by the third buffer status pin of the basic buffer chip. 11. The method of claim 10, wherein when the special indication indicates that a buffer condition condition different from the condition sensed by the third buffer status pin of the basic buffer chip is detected by the corresponding buffer status pin of the programmable buffer chip, And a third state pin of the programmable buffer chip detects both conditions of the buffer pool condition and the buffer empty condition. 10. The apparatus of claim 9, wherein the special indication in the program information includes the first offset data and the second offset data; Similar to the first buffer status pin of the basic buffer chip, first offset data of a predetermined value indicates that the first buffer status pin of the programmable buffer chip indicates a buffer pool condition; Similar to the second buffer status pin of the basic buffer chip, the second offset data of a predetermined value indicates that the second buffer status pin of the programmable buffer chip indicates a buffer empty condition. Way. 13. The method of claim 12, wherein the first offset data value other than the predetermined value indicates that the first buffer status pin of the programmable buffer chip indicates the buffer all-most pull condition according to an offset represented by the first offset data. Instruct; The second offset data value other than the predetermined value indicates that the second buffer status pin of the programmable buffer chip indicates the buffer all-most empty condition according to the offset indicated by the second offset data. How to write program information. 12. The apparatus of claim 11, wherein the special indication in the program information includes a program indication bit; Any one binary level of the program indication bit indicates that the same condition sensed by the third buffer status pin of a basic buffer chip is sensed by a corresponding third buffer status pin of a programmable buffer chip; Another previous level of the program indication bit indicates that the condition different from the condition sensed by the third buffer status pin of the basic buffer chip is detected by the corresponding third buffer status pin of the programmable buffer chip. Program information writing method characterized by the above-mentioned. 15. The apparatus of claim 14, wherein the special indication in the program information includes the first offset data and the second offset data; Similar to the first buffer status pin of the basic buffer chip, first offset data of a predetermined value indicates that the first buffer status pin of the programmable buffer chip indicates a buffer pool condition; Similar to the second buffer status pin of the basic buffer chip, the second offset data of a predetermined value indicates that the second buffer status pin of the programmable buffer chip indicates a buffer empty condition. Way. 16. The method of claim 15, wherein the first offset data value other than the predetermined value indicates that the first buffer status pin of the programmable buffer chip indicates the buffer all-most pull condition according to an offset represented by the first offset data. Instruct; The second offset data value other than the predetermined value indicates that the second buffer status pin of the programmable buffer chip indicates the buffer all-most empty condition according to the offset indicated by the second offset data. How to write program information. 12. The device of claim 11, wherein the reset signal is a signal level applied to a reset pin of a programmable buffer chip; And the reset release signal is another signal level applied to the reset pin of the programmable buffer chip. 17. The device of claim 16, wherein: the reset signal is a signal level applied to a reset pin of a programmable buffer chip; And the reset release signal is another signal level applied to the reset pin of the programmable buffer chip. 12. The method of claim 11, wherein the two buffers on the programmable buffer chip and the basic buffer chip maintain data transfer of a first-in, first-out sequence. 12. The method of claim 11, wherein each of said first and second offset data is a binary value, wherein each increment corresponds to a two byte offset in a programmable buffer chip. 12. The apparatus of claim 11, wherein the special indication in the program information is a single program indication bit; The binary level of any one of the program indication bits is such that the same condition sensed by the first, second and third buffer status pins of the basic buffer chip corresponds to the corresponding first, second and third buffer states of the programmable buffer chip. Indicate sensing by a pin; Another binary level of the program indication bit is different from the condition sensed by the first, second and third buffer status pins of the basic buffer chip. Program information writing method, characterized in that it is detected by the third buffer status pin. 22. The device of claim 21 wherein the reset signal is a signal level applied to a reset pin of a programmable buffer chip; And the reset release signal is another signal level applied to the reset pin of the programmable buffer chip. The computer program product of claim 13, wherein the program information comprises two data words; One of the data words contains the first offset data and the other data word contains the second offset data; And during said input step, said first and second data words are sequentially input into said programmable buffer chip. 6. The apparatus according to claim 5, wherein the program information area indicates whether the programmable buffer unit blocks the writing of a reset mode to be set in a reset operation in response to the generation of the reset signal; Whereby the programmable buffer chip is operable to block writing the reset mode in response to the next occurrence of the reset signal when the program information already written in the programmable buffer chip indicates such blocking. How to write program information. 6. The data pin of claim 5, wherein said input step comprises a data pin wherein program information is used differently to output a data factor from or through a data pin that is otherwise used to input a data factor into the buffer memory during normal mode. Applying a direction signal to the programmable buffer chip indicating whether or not to be inputted through the programmable buffer chip; The direction signal is applied to a pin of the programmable buffer chip corresponding to a control pin in the basic buffer chip that has no functional significance during the reset of the basic buffer chip; And the program information is input through the pin indicated by the direction signal during the input step. 25. The data pin of claim 24, wherein said input step comprises a data pin where program information is used differently to output a data factor from or through a data pin that is otherwise used to input a data factor into the buffer memory during normal mode. Applying a direction signal to the programmable buffer chip indicating whether or not to be inputted through the programmable buffer chip; The direction signal is applied to a pin of the programmable buffer chip corresponding to a control pin in the basic buffer chip that has no functional significance during the reset of the basic buffer chip; And the program information is input through the pin indicated by the direction signal during the input step.