KR957000573A - High-performance, non-decaying RAM write cache protected accelerator system (high-perfor-mance non-volatile ram protected write cache accel-erator system) - Google Patents

High-performance, non-decaying RAM write cache protected accelerator system (high-perfor-mance non-volatile ram protected write cache accel-erator system)

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Publication number
KR957000573A
KR957000573A KR1019940703157A KR19940703157A KR957000573A KR 957000573 A KR957000573 A KR 957000573A KR 1019940703157 A KR1019940703157 A KR 1019940703157A KR 19940703157 A KR19940703157 A KR 19940703157A KR 957000573 A KR957000573 A KR 957000573A
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South Korea
Prior art keywords
data
means
non
memory
data storage
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Application number
KR1019940703157A
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Korean (ko)
Inventor
유-핑 쳉
데이비드 히쯔
Original Assignee
프레드 너보
오스펙스 시스템즈, 인코포레이티드
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Priority to US84853992A priority Critical
Priority to US848,539 priority
Application filed by 프레드 너보, 오스펙스 시스템즈, 인코포레이티드 filed Critical 프레드 너보
Priority to PCT/US1993/001911 priority patent/WO1993018461A1/en
Publication of KR957000573A publication Critical patent/KR957000573A/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22Employing cache memory using specific memory technology
    • G06F2212/222Non-volatile memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31Providing disk cache in a specific location of a storage system
    • G06F2212/312In storage controller

Abstract

본 발명은 호스트(32) 및 다수의 데이타 기억장치(34,40,42) 사이의 데이타의 전송을 위한 호스트 컴퓨터시스템(32)에 접속된 데이타 기억장치 시스템을 구현하는 것이다. The present invention is to implement the data storage system connected to a host computer system (32) for transmission of data between a host 32 and a plurality of data storage devices (34,40,42). 데이타 기억장치(34,40,42)는 데이타 기억장치(34,40,42)중 적어도 각각의 하나에 접속된 각각의 데이타 기억장치 채널을 가진 다수의 데이타 전송채널(86)에 접속되어진다. Data storage apparatus (34,40,42) will be connected to the data storage device a plurality of data transfer channels (86) at least with each of the data storage channel connected to the respective one of (34,40,42). 각각의 데이타 전송 채널(86)은 데이타 버퍼(85) 및 채널(86)과 데이타 기억장치(34,40,42) 사이의 데이타 전송을 위한 자율 운용 제어기(38)를 포함한다. Each data transmission channel 86 includes a data buffer 85 and the channel 86 and the data storage device autonomous operation controller 38 for data transmission between the (34,40,42). 비-소멸성 임의 접근 기억장치 메모리(42)가 데이타의 캐시된 페이지를 저장하도록 제공된다. Non-decaying random access storage memory 42 is provided to store a cache of the data page. 인터페이스(100)는 전송된 데이타를 통해 데이타 기억장치 시스템을 호스트로 접속시킨다. Interface 100 connects the data storage system via a data transmission to the host. 재구성 가능한 데이타 경로(80)가 데이타 전송 채널, 비-소멸성 메모리(42) 및 인터페이스(100) 사이의 선택적인 데이타 전송 접속을 허용하다. A reconfigurable data path (80) data transfer channel, a non-it allows for selective data transmission connection between the decaying memory 42 and the interface 100. 제어기(76)는 데이타 경로(80)의 구성을 관리하고, 인터페이스(100) 및 채널 데이타 버퍼(85)사이, 인터페이스 및 비-소멸성 메모리(42)사이 그리고, 비-소멸성 메모리(42) 및 채널 데이타 버퍼(85) 사이의 데이타의 버스트 전송을 위한 직접 메모리 접근 제어기(114)를 제어한다. The controller 76 manages the configuration of the data path 80, and the interface 100 and channel data buffer (85) between the interface and the non-between the decaying memory 42 and the non-decaying memory 42 and channel and it controls the data buffer 85, a direct memory access controller (114) for a burst transfer of data between.

Description

고-성능 비-소멸성 램 보호 기록 캐시 가속기 시스템(HIGH-PERFOR-MANCE NON-VOLATILE RAM PROTECTED WRITE CACHE ACCEL-ERATOR SYSTEM) High-performance, non-decaying RAM write cache protected accelerator system (HIGH-PERFOR-MANCE NON-VOLATILE RAM PROTECTED WRITE CACHE ACCEL-ERATOR SYSTEM)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음 This information did not disclose more professional information because lumbar Articles

제2도는 본 발명의 바람직한 실시예에 따라 고 무결성(integrity) 기록 캐시 가속기 부-시스템(sub-system)을 채용한 컴퓨터 시스템의 블럭도, 제3a도는 본 발명에 따라 구성된 기억 장치 프로세서 부-시스템의 바람직한 실시예의 상세한 블럭도, 제3b도는 본 발명의 바람직한 실시예에 따른 데이타 채널 인터페이스 장치의 개략 블럭도, 제3c도는 본 발명에 따라 구성된 바와 같이 부착된 배터리 백업 기능을 갖는 이동가능 비-소멸성 메모리 어레이의 바람직한 보조카드 구현의 단순 블럭도, 제4도는 본 발명의 바람직한 실시예에서 구현된 데이타 구조를 제어하는 소프트웨어 및 관련된 하드웨어의 개략 도시도. A second turn and in accordance with a preferred embodiment of the present invention integrity (integrity) write cache accelerator sub-block of a computer system employing a system (sub-system) also, the 3a turns storage processor unit constructed in accordance with the present invention system of the preferred embodiment detailed block diagram, the 3b to turn a schematic block diagram of the data channel interface unit in accordance with a preferred embodiment of the present invention, 3c turn movable with a battery backup attachment, as constructed in accordance with the present invention a non-decaying simple block diagram of a preferred implementation of the daughter card, the memory array is also a fourth turning a schematic showing the hardware and associated software for controlling the data structures implemented in the preferred embodiment of the present invention.

Claims (3)

  1. 데이타 전송을 위해 호스트 컴퓨터 시스템에 접속된 데이타 기억장치 시스템으로, 상기 데이타 기억장치 시스템은, 다수의 데이타 기억장치와, 상기 대수의 데이타 기억장치에 각각 접속되고, 데이타 버퍼 및 상기 데이타 버퍼 및 상기 데이타 기억장치의 각각의 하나사이의 데이타 전송을 자율 제어하는 수단을 각각 포함하는 다수의 데이타 전송 채널과, 데이타의 비-소멸성 임의 접근 기억장치용 메모리 수단과, 데이타 전송용 인터페이스 수단과, 상기 데이타 전송 채널, 상기 메모리 수단 및 상기 인터페이스 수단사이에 선택적인 데이타 전송 접속을 제공하는 데이타 수단과, 상기 데이타 수단에 접속되어, 상기 데이타 전송 채널, 상기 메모리 수단 및 상기 인터페이스 수단사이에 데이타 전송을 관리하고, 상기 인터페이스 수단 및 상기 메모리 수단 In a data storage system connected to a host computer system for data transfer, the data storage system, is connected to the plurality of data storage devices, and a data storage device of the number, the data buffer and the data buffer and the data of the storage device each of the plurality of means for self-control the data transfer between a respective data transmission channel and, in the data non-decaying random access memory the memory means, the data transfer interface means, the data transfer for channel, data means for providing said memory means, and an optional data transfer connection between said interface means, connected to said data unit, and manage the data transfer between the data transfer channel, said memory means and said interface means, said interface means and said memory means 사이 그리고 상기 메모리 수단 및 상기 데이타 버퍼사이에 데이타 버스트 전송을 위하여 상기 제어 수단에 응답하는 직접 메모리 접근 제어 수단을 포함하는 제어 수단으로 구성된 것을 특징으로 하는 데이타 기억장치 시스템. And between the data storage system, characterized in that the control means is configured to include a direct memory access control means responsive to said control means for a data burst transmitted between said memory means and said data buffer.
  2. 제1항에 있어서, 상기 메모리 수단은 상기 데이타 기억장치의 각각의 하나에 의한 기억장치용으로 충당되어지는 데이타의 캐시 페이지를 저장하고, 상기 데이타 기억장치 시스템은 각각의 데이타의 캐시 페이지의 목적지 및 상태를 정의하는 제어 데이타의 비-소멸성 임의 접근 기억장치용 제어 메모리 수단을 포함하는 것을 특징으로 데이타 기억장치 시스템. The method of claim 1, wherein the memory means is the destination of a cache page in the data cover for the memory device according to each one of the storage device stores the cache page of data that is, wherein the data storage system, each of the data, and the control data that define the state a non-decaying data storage system characterized in that it comprises a random access memory for controlling the memory means.
  3. 제2항에 있어서, 데이타의 캐시 페이지의 상태는 자유 및 사용중을 포함하고, 상기 제어 수단은 상기 인터페이스로부터 사전결정된 제1케시 페이지로 데이타의 전송을 선택적으로 관리하고, 상기 제어 수단은 사전결정된 제2캐시 페이지의 상태를 정의하는 제어 데이타를 변경하는 것을 특징으로 하는 데이타 기억장치 시스템. Of claim 2 wherein the determined status of the cache page of data comprises a free, and in use, said control means selectively managing the transfer of data to a predetermined first Kathy page from said interface, said control means is pre claim the data storage system, characterized in that to change the control data defining the state of the second cache page.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임. ※ Note: Will you disclose by the first application information.
KR1019940703157A 1992-03-09 1993-03-04 High-performance, non-decaying RAM write cache protected accelerator system (high-perfor-mance non-volatile ram protected write cache accel-erator system) KR957000573A (en)

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US84853992A true 1992-03-09 1992-03-09
US848,539 1992-03-09
PCT/US1993/001911 WO1993018461A1 (en) 1992-03-09 1993-03-04 High-performance non-volatile ram protected write cache accelerator system

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US (1) US5701516A (en)
EP (1) EP0630499A4 (en)
JP (1) JPH07504527A (en)
KR (1) KR957000573A (en)
AU (1) AU662973B2 (en)
CA (1) CA2131627A1 (en)
WO (1) WO1993018461A1 (en)

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