KR950030246A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR950030246A
KR950030246A KR1019940009311A KR19940009311A KR950030246A KR 950030246 A KR950030246 A KR 950030246A KR 1019940009311 A KR1019940009311 A KR 1019940009311A KR 19940009311 A KR19940009311 A KR 19940009311A KR 950030246 A KR950030246 A KR 950030246A
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layer
etching
barrier layer
etching barrier
gate electrode
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KR100291823B1 (en
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김재갑
김대영
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 게이트전극 마스크를 이용하여 게이트 산화막패턴, 게이트전극, 충간절연막패턴 및 제1식각장벽층패턴을 형성하고 상기 게이트전극의 측벽과 노출된 반도체기판에 산화막을 성장시킨 다음, 저농도의 불순물을 주입하고 상기 게이트전극 마스크에 의하여 형성된 패턴의 측벽에 스페이서를 형성한 다음, 고농도의 불순물을 주입하고 자기정렬적으로 콘택홀을 형성함으로써 불순물 주입으로 인한 반도체기판의 손상을 방지하고 자기정렬적으로 콘택홀을 형성함으로써 고집적화를 가능하게 하여 반도체소자의 신뢰성 및 생산성을 향상시킬 수 있는 기술이다.The present invention relates to a method of fabricating a semiconductor device, wherein a gate oxide layer pattern, a gate electrode, an interlayer insulating layer pattern, and a first etching barrier layer pattern are formed on the semiconductor substrate by using a gate electrode mask. After the oxide film is grown on the semiconductor substrate, a low concentration of impurities are implanted, a spacer is formed on the sidewalls of the pattern formed by the gate electrode mask, a high concentration of impurities are implanted, and a contact hole is formed in a self-aligned manner. It is a technology that can improve the reliability and productivity of semiconductor devices by preventing the damage to the semiconductor substrate and forming contact holes in a self-aligned manner to enable high integration.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 제1실시예에 의한 반도체소자의 제조공정을 도시한 단면도.2A to 2E are sectional views showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Claims (9)

반도체소자의 제조방법에 있어서, 반도체기판 상부에 게이트산화막, 게이트전극용 전도층, 층간절연막 및 제1식각장벽층을 순차적으로 증착하는 공정과, 게이트전극 마스크를 사용하여 상기 제1식각장벽층, 층간절연막, 전도층 및 게이트산화막을 순차적으로 식각하여 제1식각장벽층패턴, 층간절연막패턴 및 게이트전극을 형성하여 상기 반도체기판의 예정된 부위를 노출시키는 공정과, 상기 게이트전극의 측벽과 노출된 반도체기판 상부에 산화막을 성장시키는 공정과, 상기 반도체기판에 저농도의 불순물을 주입하여 저농도의 소오스/드레인 전극을 형성하는 공정과, 전체구조상부에 제2식각장벽층과 절연막을 순차적으로 증착하는 공정과, 상기 제2식각장벽층을 식각장벽으로 하여 상기 절연막을 이방성식각하여 절연막 스페이서를 형성하고 상기 산화막을 식각장벽으로 하여 상기 제2식각장벽층을 식각하여 제2식각장벽층 스페이서를 형성한 다음, 고농도의 불순물을 주입하여 고농도의 소오스/드레인 전극을 형성하는 공정과, 전체구조상부에 평탄화층을 형성한 다음, 상기 평탄화층의 상부에 감광막을 이용하여 콘택마스크를 형성하는 공정과, 상기 콘택마스크를 이용하여 콘택지역에 있는 상기 평탄화충, 절연막 스페이서 및 산화막을 순차적으로 식각함으로써 제2식각장벽층 스페이스의 턱진부분을 형성하고 소오스/드레인 전극에 자기정렬된 콘택홀을 형성하는 공정을 포함하는 반도체소자의 제조방법.A method of manufacturing a semiconductor device, comprising: sequentially depositing a gate oxide film, a gate electrode conductive layer, an interlayer insulating film, and a first etch barrier layer on a semiconductor substrate, the first etch barrier layer using a gate electrode mask, Sequentially etching the interlayer insulating film, the conductive layer, and the gate oxide film to form a first etching barrier layer pattern, an interlayer insulating film pattern, and a gate electrode to expose a predetermined portion of the semiconductor substrate, and the sidewalls of the gate electrode and the exposed semiconductor. Growing an oxide film on the substrate, injecting a low concentration of impurities into the semiconductor substrate to form a low concentration source / drain electrode, and sequentially depositing a second etching barrier layer and an insulating film on the entire structure; Anisotropically etching the insulating film using the second etching barrier layer as an etching barrier to form an insulating film spacer; Etching the second etch barrier layer using an oxide layer as an etch barrier to form a second etch barrier layer spacer, and then implanting a high concentration of impurities to form a high concentration source / drain electrode; and a planarization layer over the entire structure. Forming a contact mask using a photoresist layer on the planarization layer, and sequentially etching the planarizing insect, the insulating layer spacer, and the oxide layer in the contact region using the contact mask. A method of manufacturing a semiconductor device, comprising forming a recessed portion of a layer space and forming a self-aligned contact hole in a source / drain electrode. 제1항에 있어서, 상기 제1, 2식각장벽층은 질화막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the first and second etching barrier layers use a nitride film. 제1항에 있어서, 상기 절연막은 산화막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the insulating film uses an oxide film. 제1항에 있어서, 상기 평탄화층은 BPSG의 단층구조 또는 USG/BPSG의 이중구조로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the planarization layer is formed of a single layer structure of BPSG or a double structure of USG / BPSG. 제1항에 있어서, 상기 산화막은 30Å∼300Å으로 하는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film is 30 mW to 300 mW. 제1항에 있어서, 상기 제2식각장벽층 스페이서 형성공정시 저부에 있는 상기 제1식각장벽층까지 일부 식각되도록 하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein a portion of the second etching barrier layer spacer is etched up to a portion of the first etching barrier layer at a bottom thereof. 제1항에 있어서, 상기 콘택마스크를 이용한 식각공정으로 제2식각장벽층 스페이서의 턱진부분을 형성한 다음, 상기 평탄화층을 마스크로 하여 상기 턱진 제2식각장벽층과 그 저부에 있는 산화막을 이방성식각함으로써 자기정렬된 콘택홀의 크기를 넓히는 것을 특징으로 하는 반도체소자의 제조방법.The etched portion of the second etch barrier layer spacer is formed by an etching process using the contact mask, and then the etched second etch barrier layer and the oxide layer on the bottom thereof are anisotropic using the planarization layer as a mask. A method of manufacturing a semiconductor device, characterized in that to increase the size of the self-aligned contact hole by etching. 제7항에 있어서, 상기 제2식각장벽층 스페이서의 턱진부분 식각공정시 상기 제1, 2식각장벽층 및 층간절연막이 일부 식각되는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 7, wherein the first and second etching barrier layers and the interlayer insulating layer are partially etched during the etching of the second etching barrier layer spacers. 반도체소자의 제조방법에 있어서, 반도체기판 상부에 게이트산화막, 게이트전극용 전도층, 층간절연막 및 제1식각장벽층을 순차적으로 증착하는 공정과, 게이트전극 마스크를 사용하여 제1식각장벽층패턴, 층간절연막패턴 그리고 게이트전극을 순차적으로 형성하여 상기 반도체기판을 노출시키는 공정과, 상기 게이트전극의 측벽과 노출된 반도체기판에 산화막을 성장시키고 상기 반도체기판에 저농도의 불순물을 주입시켜 저농도의 소오스/드레인 전극을 형성한 다음, 전체구조상부에 제2식각장벽층을 일정두께 증착하는 공정과, 상기 제2식각장벽층을 이방성식각하여 상기 제1식각장벽층, 층간절연막 및 게이트전극의 측벽에 형성된 산화막의 측벽에 제2식각장벽층 스페이서를 형성하는 공정과, 상기 제2식각장벽층 스페이서를 마스크로 하여 상기 반도체기판에 고농도의 불순물을 주입시켜 고농도의 소오스/드레인 전극을 형성하는 공정과, 전체구조상부에 평탄화층을 형성하고 상기 평탄화층 상부에 감광막을 이요하여 콘택마스크를 형성하는 공정과, 상기 콘택마스크를 사용하고 상기 제1식각장벽층과 제2식각장벽층 스페이서를 식각장벽으로 하여 상기 평탄화층과 산화막을 식각하므로써 소오스/드레인 전극이 노출된 자기정렬형 콘택홀을 형성하는 공정을 포함하는 반도체소자의 제조방법.A method of manufacturing a semiconductor device, comprising: sequentially depositing a gate oxide film, a gate electrode conductive layer, an interlayer insulating film, and a first etching barrier layer on a semiconductor substrate, a first etching barrier layer pattern using a gate electrode mask, Forming an interlayer insulating pattern and a gate electrode sequentially to expose the semiconductor substrate; and growing an oxide film on the sidewall of the gate electrode and the exposed semiconductor substrate and injecting a low concentration of impurities into the semiconductor substrate to inject a low concentration source / drain. Forming an electrode, and then depositing a second etching barrier layer on the entire structure to a predetermined thickness, and anisotropically etching the second etching barrier layer to form an oxide film formed on sidewalls of the first etching barrier layer, the interlayer insulating layer, and the gate electrode. Forming a second etching barrier layer spacer on a sidewall of the substrate; and using the second etching barrier layer spacer as a mask. Forming a high concentration source / drain electrode by injecting a high concentration of impurities into the semiconductor substrate, forming a planarization layer on the entire structure, and forming a contact mask by applying a photoresist on the planarization layer, and the contact mask. Forming a self-aligned contact hole exposing source / drain electrodes by etching the planarization layer and the oxide layer using the first etching barrier layer and the second etching barrier layer spacer as an etching barrier. Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019940009311A 1994-04-29 1994-04-29 Method for fabricating semiconductor device KR100291823B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100369355B1 (en) * 1999-06-28 2003-01-24 주식회사 하이닉스반도체 Method for fabricating highly integrated semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724625B1 (en) 2005-06-09 2007-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device
WO2019180913A1 (en) 2018-03-23 2019-09-26 三菱マテリアル株式会社 Method for manufacturing electronic-component-mounted module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100369355B1 (en) * 1999-06-28 2003-01-24 주식회사 하이닉스반도체 Method for fabricating highly integrated semiconductor device

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