KR950021275A - MOSFET manufacturing method - Google Patents

MOSFET manufacturing method Download PDF

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Publication number
KR950021275A
KR950021275A KR1019930031830A KR930031830A KR950021275A KR 950021275 A KR950021275 A KR 950021275A KR 1019930031830 A KR1019930031830 A KR 1019930031830A KR 930031830 A KR930031830 A KR 930031830A KR 950021275 A KR950021275 A KR 950021275A
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KR
South Korea
Prior art keywords
semiconductor substrate
forming
polysilicon layer
exposed
pattern
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KR1019930031830A
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Korean (ko)
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KR0125297B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Priority to KR1019930031830A priority Critical patent/KR0125297B1/en
Publication of KR950021275A publication Critical patent/KR950021275A/en
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Publication of KR0125297B1 publication Critical patent/KR0125297B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 모스펫(MOSFET)제조방법에 관한 것으로, 집적도가 높아짐에 따라 감소하는 채널길이가 작아져 발생되는 문제를 해결하기 위하여 반도체 기판에 돌출부를 제조한 다음, 돌출부가 감싸지도록 게이트 산화막과 게이트 전극을 형성하고, 게이트 전극과 소오스/드레인 영역에 실리사이드를 형성하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET in a semiconductor device. In order to solve the problem caused by a decrease in channel length, which decreases as the degree of integration increases, a gate oxide film is formed on the semiconductor substrate and then the protrusion is wrapped. And a gate electrode, and silicide is formed in the gate electrode and the source / drain regions.

Description

모스펫(MOSFET)제조방법MOSFET manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명에 의해 채널길이가 증대된 모스펫을 제조하는 단계를 도시한 단면도이다.2A to 2E are cross-sectional views illustrating steps of manufacturing a MOSFET having an increased channel length according to the present invention.

Claims (5)

반도체 기판 상부에 제1산화막을 형성하고, 그 상부에 감광막 패턴을 형성하고, 노출된 제1산화막과 그 하부의 반도체기판의 일정두께를 식각하여 돌출된 형태의 반도체 기판을 형성하는 단계와, 상기 감광막 패턴과 제1산화막을 제거하고, 전체적으로 게이트 산화막과 폴리실리콘층을 적층하는 단계와, 상기 폴리실리콘층의 돌출부를 감싸는 감광막패턴을 형성하고 노출되는 폴리실리콘층을 일정두께를 식각하는 단계와, 상기 감광막패턴을 제거한 후, 저농도 이온을 반도체 기판으로 주입하여 LDD영역을 형성하는 단계와, 상기 폴리실리콘층의 측벽에 PSG막 스페이서를 형성하고, 고농도 불순물을 반도체 기판으로 이온주입시켜 소오스/드레인 영역을 형성하는 단계와, 노출된 폴리실리콘층을 게이트 산화막이 노출되기까지 식각하여 게이트 전극용 폴리실리콘층 패턴을 형성하고 고온 공정으로 상기 PSG막 스페이서를 플로우시켜 상기 게이트 전극용 폴리실리콘층 패턴의 측면을 절연시키는 단계와, 전이금속을 상기 소오스/드레인 영역과 게이트 전극용 폴리실리콘층 패턴 상부에 선택적으로 형성하고, 열처리하여 실리사이드를 형성하는 단계를 포함하는 모스펫 제조방법.Forming a first oxide film on the semiconductor substrate, forming a photoresist pattern on the semiconductor substrate, etching a predetermined thickness of the exposed first oxide film and the semiconductor substrate under the semiconductor substrate to form a protruding semiconductor substrate; Removing the photoresist pattern and the first oxide layer, stacking the gate oxide layer and the polysilicon layer as a whole, forming a photoresist pattern surrounding the protrusion of the polysilicon layer, and etching a predetermined thickness of the exposed polysilicon layer; Removing the photoresist pattern, implanting low concentration ions into the semiconductor substrate to form an LDD region, forming a PSG film spacer on the sidewall of the polysilicon layer, and implanting high concentration impurities into the semiconductor substrate Forming an oxide layer and etching the exposed polysilicon layer until the gate oxide layer is exposed. Forming a silicon layer pattern and insulating a side surface of the polysilicon layer pattern for the gate electrode by flowing the PSG film spacer in a high temperature process; and forming a transition metal on the source / drain region and the polysilicon layer pattern for the gate electrode. Forming a silicide by selectively forming a heat treatment and forming a silicide; 제1항에 있어서, 상기 저농도 불순물을 이온주입할때 반도체 기판에 대해 경사지게 주입하는 것을 특징으로 하는 모스펫 제조방법.The method of claim 1, wherein the low concentration impurity is implanted at an angle with respect to the semiconductor substrate. 제1항에 있어서, 상기 게이트산화막을 형성하기 전에 반도체 기판으로 문턱전압 조절용 불순물을 이온주입하는 것을 특징으로 하는 모스펫 제조방법.The method of claim 1, wherein the impurity for adjusting the threshold voltage is implanted into the semiconductor substrate before the gate oxide layer is formed. 제1항에 있어서, 상기 PSG막 스페이서 대신에 BPSG막 스페이서로 형성하는 것을 특징으로 하는 모스펫 제조방법.The method of claim 1, wherein the MOSFET is formed of a BPSG film spacer instead of the PSG film spacer. 제1항에 있어서, 상기 폴리실리콘층의 측벽에 PSG막 스페이서를 형성하고, 노출되는 폴리실리콘층을 게이트 산화막이 노출되기까지 식각하여 게이트 전극용 폴리실리콘층 패턴을 형성하고, 고온 공정으로 상기 PSG막 스페이서를 플로우시켜 상기 게이트 전극용 폴리실리콘층 패턴의 측면을 절연시킨 다음, 고농도 불순물을 반도체 기판으로 이온주입시켜 소오스/드레인 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 모스펫 제조방법.The PSG film spacer of claim 1, wherein the PSG film spacers are formed on sidewalls of the polysilicon layer, and the exposed polysilicon layer is etched until the gate oxide film is exposed to form a polysilicon layer pattern for a gate electrode. Flowing a film spacer to insulate the side surface of the polysilicon layer pattern for the gate electrode, and ion implanting a high concentration of impurities into the semiconductor substrate to form a source / drain region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031830A 1993-12-31 1993-12-31 Fabrication method of mosfet KR0125297B1 (en)

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KR1019930031830A KR0125297B1 (en) 1993-12-31 1993-12-31 Fabrication method of mosfet

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Application Number Priority Date Filing Date Title
KR1019930031830A KR0125297B1 (en) 1993-12-31 1993-12-31 Fabrication method of mosfet

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KR950021275A true KR950021275A (en) 1995-07-26
KR0125297B1 KR0125297B1 (en) 1997-12-10

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KR100504546B1 (en) * 2000-07-24 2005-08-01 주식회사 하이닉스반도체 method for manufacturing of semiconductor device

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