KR950012469A - SRAM circuit - Google Patents

SRAM circuit Download PDF

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Publication number
KR950012469A
KR950012469A KR1019930021620A KR930021620A KR950012469A KR 950012469 A KR950012469 A KR 950012469A KR 1019930021620 A KR1019930021620 A KR 1019930021620A KR 930021620 A KR930021620 A KR 930021620A KR 950012469 A KR950012469 A KR 950012469A
Authority
KR
South Korea
Prior art keywords
bit line
data
writing
column
memory cell
Prior art date
Application number
KR1019930021620A
Other languages
Korean (ko)
Other versions
KR960006383B1 (en
Inventor
김경율
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019930021620A priority Critical patent/KR960006383B1/en
Publication of KR950012469A publication Critical patent/KR950012469A/en
Application granted granted Critical
Publication of KR960006383B1 publication Critical patent/KR960006383B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 에스램(SRAM) 회로에 관한 것으로, 종래에는 메모리셀에 라이트(WRITE)한 후 한참후에 워드라인이 컷오프되므로 이 기간동안 불필요한 동작전류가 흐르게 되는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM circuit. In the related art, since a word line is cut off after a long time after writing to a memory cell, an unnecessary operating current flows during this period.

따라서, 종래의 문제점을 해결하기 위하여 본 발명은 라이크사이클에서 보트라인 중 어느 하나가 로우상태로 천이될 때 이를 감지하여 워드라인신호와 칼럼선택신호를 위한 셀액세스 트랜지스터 및 칼럼트랜지스터를 컷오프시켜 메모리셀에 라이트한 후 바로 불필요한 동작전류가 흐르지 않도록 한다.Accordingly, in order to solve the conventional problem, the present invention senses when any one of the boat lines transitions to a low state in the like cycle, and cuts off the cell access transistor and the column transistor for the word line signal and the column selection signal, thereby reducing the memory cell. Do not allow unnecessary operating current to flow immediately after the writing.

Description

에스램 회로SRAM circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 에스램(SRAM)회로도.3 is an SRAM circuit diagram of the present invention.

Claims (1)

칼럼입력인에블(CIEB)신호에 따라 데이타입력을 논리조합하여 출력하는 논리조합부(1)와, 상기 논리 조합부(1)의 데이타출력을 비트라인(D)(DB)을 통해 다음단에 공급 또는 차단하는 데이타전송부(2)와, 상기 데이타전송부(2)의 비트라인을 통해 입력되는 데이타를 라이트(WRITE)하여 저장하는 메모리셀(3)과, 상기 데이타전송부(2)의 비트라인으로 공급되는 데이타의 천이상태를 감지하는 비트라인감지부(4)와, 상기 비트 라인감지부(4)의 감지신호에 따라 셀액세스 트랜지스터 및 칼럼트랜지스터의 동작을 제어하여 동작전류를 제한하는 전류제한부(5)로 구성된 에스램(SRAM)회로.A logic combining unit 1 for logically combining data input according to the column input enable signal and outputting the data output of the logical combining unit 1 through a bit line D (DB). A data transfer unit 2 for supplying or cutting off the data, a memory cell 3 for writing and storing data input through a bit line of the data transfer unit 2, and the data transfer unit 2 A current limiting an operating current by controlling operation of a cell access transistor and a column transistor according to a bit line detector 4 detecting a transition state of data supplied to a bit line of the bit line and a detection signal of the bit line detector 4. SRAM circuit consisting of a limiting section (5). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930021620A 1993-10-18 1993-10-18 Sram circuit KR960006383B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930021620A KR960006383B1 (en) 1993-10-18 1993-10-18 Sram circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021620A KR960006383B1 (en) 1993-10-18 1993-10-18 Sram circuit

Publications (2)

Publication Number Publication Date
KR950012469A true KR950012469A (en) 1995-05-16
KR960006383B1 KR960006383B1 (en) 1996-05-15

Family

ID=19366059

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930021620A KR960006383B1 (en) 1993-10-18 1993-10-18 Sram circuit

Country Status (1)

Country Link
KR (1) KR960006383B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422812B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Semiconductor memory device for minimizing constant current in write operation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422812B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Semiconductor memory device for minimizing constant current in write operation

Also Published As

Publication number Publication date
KR960006383B1 (en) 1996-05-15

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