KR940027325A

KR940027325A - Square wave oscillator

Info

Publication number: KR940027325A
Application number: KR1019930009538A
Authority: KR
Inventors: 김승윤
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1993-05-31
Filing date: 1993-05-31
Publication date: 1994-12-10

Abstract

본 발명은 구형파 발진기에서 특히 단일전원으로서 높은 전압레벨의 저주파수를 출력하도록 하는 구형파 발진기에 관한 것으로, 본 발명에 의한 구형파 발진기는 소정의 유기된 전압을 저장하는 캐패시터와 상기 캐패시터에 저장될 전압을 제 1 동작시 충전시키기 위한 충전수단과 상기 캐패시터에 저장된 전압을 제 2 동작시 방전시키기 위한 방전수단으로 이루어지는 발진부 및 이를 구비하는 구형파 발진기를 개시하고 있다. 이러한 본 발명의 구성을 통해 트랜스포머의 권선수를 최소화시키면서도 소망의 부하파형을 출력시킬 수 있게 된다. 또한 구형파의 발생시 각 부품에 걸리는 스트레스가 경감되며, 발진부의 내압을 최소화시켜 주게된다. 그리고 소망의 크기를 가지는 구형파의 발생을 위하여 트랜지스터와 캐패시터의 크기가 커져야 하는 부담이 방지되는 효과가 발생한다.The present invention relates to a square wave oscillator for outputting a low voltage of a high voltage level as a single power source, in particular, a square wave oscillator. An oscillator comprising a charging means for charging in one operation and a discharge means for discharging a voltage stored in the capacitor in a second operation, and a square wave oscillator having the same. Through the configuration of the present invention it is possible to output the desired load waveform while minimizing the number of turns of the transformer. In addition, when the square wave is generated, the stress on each part is reduced, and the internal pressure of the oscillation part is minimized. In addition, in order to generate a square wave having a desired size, the burden of increasing the size of the transistor and the capacitor is prevented.

Description

Square wave oscillator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 4 도는 본 발명에 의한 구형파 발진기의 발진부 구성의 일실시예를 보여주는 회로도, 제 5 도는 제 5a 도와 제 5b 도로 구성되며, 제 5a 도는 제 4 도의 발진부의 입력 파형을 보여주는 파형도, 제 5b 도는 제 4 도의 구성에 따른 부하파형을 보여주는 파형도, 제 6 도는 본 발명에 의한 구형파 발진기의 발진부 구성을 다른 실시예를 보여주는 회로도.4 is a circuit diagram showing an embodiment of the configuration of the oscillator of the square wave oscillator according to the present invention, FIG. Figure 4 is a waveform diagram showing a load waveform according to the configuration of Figure 4, Figure 6 is a circuit diagram showing another embodiment of the configuration of the oscillator of the square wave oscillator according to the present invention.

Claims

A square wave oscillator comprising: a capacitor for storing a voltage induced by an input voltage applied to a predetermined first node and a second node, charging means for charging a voltage to be stored in the capacitor during a first operation; And a discharge means for discharging the voltage stored in the capacitor during the second operation.

2. The method of claim 1, wherein said first operation is an operation when said input voltage becomes logic "high" (or logic "low"), and said second operation is said input voltage is logic "low" (or logic "). Square wave oscillator, characterized in that the operation when "high").

2. The apparatus of claim 1, wherein the charging means is formed in series between a first diode formed between the first node and one end of the capacitor and between the other end of the capacitor and the second node. Square wave oscillator, characterized in that consisting of a diode.

The method of claim 3, wherein the discharging means comprises: a first transistor having a base connected to the second node and supplying a voltage applied to one end of the capacitor to an input side of the third diode, and connected to the other end of the capacitor; A square wave oscillator comprising: a second transistor for discharging a voltage across the other end.

In a square wave oscillator having an oscillator for generating a square wave of a predetermined period, the oscillator comprises a capacitor for storing a voltage induced by an input voltage applied to a predetermined first node and a second node, the first node and the capacitor A first diode formed between one end of the second diode, a second diode and a third diode formed in series between the other end of the capacitor and the second node, and a base connected to the second node and applied to one end of the capacitor. And a second transistor connected to the other end of the capacitor to prevent a voltage applied to the other end of the capacitor, the first transistor supplying a voltage to an input side of the third diode.

※ Note: The disclosure is based on the initial application.