KR930014499A - Time axis correction circuit of video signal - Google Patents

Abstract

No content

Description

Timebase Correction Circuit of Youngsan Signal

As this is a public information case, the full text was not included.

1 is a video signal processing block diagram of a general video player.

2 is a block diagram of a time axis correction circuit of an image signal of the present invention.

3 is a detailed block diagram of a digital color burst separator in FIG.

4 is a detailed block diagram of a digital filter coefficient separating unit in FIG.

5 is a detailed block diagram of a digital filter in FIG.

6 is a group delay characteristic diagram of a digital filter.

* Explanation of symbols for main parts of the drawings

21: A / D converter 22: horizontal synchronous separator

23: digital color burst separator 24: 910 AFC

25: digital filter coefficient generator 26: write address generator

27: read address generator 28: filter coefficient memory

29: reference clock generator 30: reference horizontal synchronization generator

31: time axis error detection unit 32: memory

33: Digital Filter 34: D / A Converter

Claims (3)

An analog (A) / digital (D) converter 21 for converting a playback video signal PBS into a digital video signal, and a horizontal sync separator for separating a horizontal sync signal H _rep from the playback video signal PBS. And a digital color burst separator 23 for receiving the A / D converted reproduction signal and the horizontal synchronization signal H _rep and outputting a color burst signal C _b and a color burst gate signal C _bg . And a 910AFC (24) generating an oscillation clock signal (W _CK ) of 910fsc by receiving the horizontal synchronizing signal (H _rep ), and extracting a phase error from the color burst signal (C _b ). A digital filter coefficient generator 25 to be stored in (28), a write address generator 26 for receiving the clock signal W _CK and oscillating a write address signal WA, and a reference clock generator 29 Read from the clock signal R _CK to generate the read address signal RA A reference generator 27 receives the clock signal R _CK and generates a reference horizontal synchronization signal H _ref to generate a reference horizontal synchronization signal H _ref , the horizontal synchronization signal H _rep , and the reference horizontal signal. The digital-converted reproduced image according to the time axis error detection unit 31 that receives the synchronization signal H _ref and detects the time axis error and outputs the same to the rotation servo, and the write address signal WA and the read address signal RA. Memory 32 for writing and reading signals, and reading the phase error from the filter coefficient memory 28 to adjust the group delay of the reproduced video signal read from the memory 32 to perform fine time-base correction. (33) and a D / A converter (34) for converting an output signal of the digital filter (33) into an analog signal. According to claim 1, wherein the count output (C _OUT ) generated by up-counting the counter (23A) with a tip section signal of the horizontal sync signal (H _rep ) in the comparator (23B), (23C), The upper comparator 23B outputs a high potential when its output value C _OUT is greater than "N", and the lower comparator 23C also has an output value C _OUT of the counter 23A greater than "N + N _cb ". When it is large, the output of the "N + N _cb " output at high potential, and the outputs of the comparators 23B and 23C are exclusively logically operated through the exclusive OOR gate, and the result value of the data selector 23D is An output selection signal, and the data selector 23D is a color burst signal C as a sampled reproduction signal output to the A / D converter 21 while the output of the exclusive orifice EXOR is high potential. _b) a power, and a period while the other outputs a low potential that particular digital color separation section configured to burst 23 Time base correction circuit of a video signal as set. 2. The difference between two samples according to claim 1, wherein a delay signal between samples is generated through the latches 25A-25C connected in series, and then the magnitude comparison is performed between the burst samples skipped by the absolute comparison units 25D and 25E, respectively. The average error in the period divided by 1/2 after adding the output value of the absolute value comparator 25G is obtained by supplying it to the calculating unit 25G again and calculating the average error in the color burst gate signal C. _bg ) to accumulate and add the burst sine wave number to obtain an average value, and output the filter coefficient from the ARC SIN ROM 25I to the filter coefficient ROM 25I to reduce the group delay by the phase difference. A time axis correction circuit for a video signal, characterized by comprising a digital filter coefficient generator (25). ※ Note: The disclosure is based on the initial application.