KR930011490A - Frame Synchronization Signal Selection Generation Circuit of Wireless Receiver - Google Patents
Frame Synchronization Signal Selection Generation Circuit of Wireless Receiver Download PDFInfo
- Publication number
- KR930011490A KR930011490A KR1019910021169A KR910021169A KR930011490A KR 930011490 A KR930011490 A KR 930011490A KR 1019910021169 A KR1019910021169 A KR 1019910021169A KR 910021169 A KR910021169 A KR 910021169A KR 930011490 A KR930011490 A KR 930011490A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- synchronization
- frame synchronization
- synchronization signal
- wireless receiver
- Prior art date
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- Mobile Radio Communication Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
시분할 다중 억세스 방식의 무선 수신기에서 무선 채널로 부터 검출되는 프레임 동기신호를 중앙처리장치가 필요할 때에만 선택 발생한다.In a time division multiple access wireless receiver, a frame synchronization signal detected from a wireless channel is selected and generated only when the CPU is needed.
따라서 소프트웨어가 필요한 때만 프레임 동기신호를 발생시켜 중앙처리장치에 전송함으로써 시스템의 효율을 향상시킨다.Therefore, the frame synchronization signal is generated only when software is required and transmitted to the central processing unit, thereby improving the efficiency of the system.
이를 위하여 수신 클럭 신호를 일정 분주하여 완료시마다 동기 발생 억제 신호를 발생하고, 중앙처리장치의 어드레스 및 데이타 신호에 의해 액티브되며 상기 동기 발생 억제 신호에 의해 비 액티브되는 동기 발생신호를 발생한다. 상기 동기 발생신호가 액티브될 경우에만 검출되는 프레임 동기신호를 선택 발생시켜 상기 중앙처리장치로 전송한다.To this end, the reception clock signal is divided by a predetermined amount to generate a synchronization generation suppression signal upon completion, and generates a synchronization generation signal that is activated by the address and data signals of the central processing unit and inactivated by the synchronization generation suppression signal. The frame synchronization signal detected only when the synchronization generation signal is activated is generated and transmitted to the CPU.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 프레임 동기신호 선택 발생 회로의 회로도.2 is a circuit diagram of a frame synchronizing signal selection generating circuit according to the present invention.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910021169A KR930011490A (en) | 1991-11-25 | 1991-11-25 | Frame Synchronization Signal Selection Generation Circuit of Wireless Receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910021169A KR930011490A (en) | 1991-11-25 | 1991-11-25 | Frame Synchronization Signal Selection Generation Circuit of Wireless Receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR930011490A true KR930011490A (en) | 1993-06-24 |
Family
ID=67356227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910021169A KR930011490A (en) | 1991-11-25 | 1991-11-25 | Frame Synchronization Signal Selection Generation Circuit of Wireless Receiver |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930011490A (en) |
-
1991
- 1991-11-25 KR KR1019910021169A patent/KR930011490A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |