KR930000207B1 - 논리 전가산기 회로 - Google Patents

논리 전가산기 회로 Download PDF

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Publication number
KR930000207B1
KR930000207B1 KR1019850000755A KR850000755A KR930000207B1 KR 930000207 B1 KR930000207 B1 KR 930000207B1 KR 1019850000755 A KR1019850000755 A KR 1019850000755A KR 850000755 A KR850000755 A KR 850000755A KR 930000207 B1 KR930000207 B1 KR 930000207B1
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KR
South Korea
Prior art keywords
signal
inverted
gate
logic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019850000755A
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English (en)
Korean (ko)
Other versions
KR850006089A (ko
Inventor
루이스 반 메르베르겐 요젭
요제피우스 마리아 벤드릭 헨드리쿠스
피터 요하네스 마티스 벨텐 프란시스쿠스
요하누스 안토니우스 반 비크 프란시스쿠스
Original Assignee
엔. 브이. 필립스 글로아이람펜파브리켄
아이. 엠. 레르너
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Publication date
Application filed by 엔. 브이. 필립스 글로아이람펜파브리켄, 아이. 엠. 레르너 filed Critical 엔. 브이. 필립스 글로아이람펜파브리켄
Publication of KR850006089A publication Critical patent/KR850006089A/ko
Application granted granted Critical
Publication of KR930000207B1 publication Critical patent/KR930000207B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
KR1019850000755A 1984-02-09 1985-02-06 논리 전가산기 회로 Expired - Fee Related KR930000207B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8400408A NL8400408A (nl) 1984-02-09 1984-02-09 Logische optelschakeling.
NL8400408 1984-02-09

Publications (2)

Publication Number Publication Date
KR850006089A KR850006089A (ko) 1985-09-28
KR930000207B1 true KR930000207B1 (ko) 1993-01-14

Family

ID=19843459

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850000755A Expired - Fee Related KR930000207B1 (ko) 1984-02-09 1985-02-06 논리 전가산기 회로

Country Status (8)

Country Link
US (1) US4730266A (https=)
EP (1) EP0155019B1 (https=)
JP (1) JPS60181925A (https=)
KR (1) KR930000207B1 (https=)
CA (1) CA1229172A (https=)
DE (1) DE3581094D1 (https=)
IE (1) IE57290B1 (https=)
NL (1) NL8400408A (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3687408D1 (de) * 1985-09-30 1993-02-11 Siemens Ag Mehrstelliger carry-ripple-addierer in cmos-technik mit zwei typen von addiererzellen.
DE3687778D1 (en) * 1985-09-30 1993-03-25 Siemens Ag Addierzelle fuer carry-ripple-addierer in cmos-technik.
US4831578A (en) * 1985-11-25 1989-05-16 Harris Semiconductor (Patents) Inc. Binary adder
US4766565A (en) * 1986-11-14 1988-08-23 International Business Machines Corporation Arithmetic logic circuit having a carry generator
US4893269A (en) * 1988-04-29 1990-01-09 Siemens Aktiengesellschaft Adder cell for carry-save arithmetic
US5130575A (en) * 1989-09-20 1992-07-14 International Business Machines Corporation Testable latch self checker
US5479356A (en) * 1990-10-18 1995-12-26 Hewlett-Packard Company Computer-aided method of designing a carry-lookahead adder
JPH04172011A (ja) * 1990-11-05 1992-06-19 Mitsubishi Electric Corp 半導体集積回路
US5208490A (en) * 1991-04-12 1993-05-04 Hewlett-Packard Company Functionally complete family of self-timed dynamic logic circuits
US5389835A (en) * 1991-04-12 1995-02-14 Hewlett-Packard Company Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression
US5250860A (en) * 1992-06-25 1993-10-05 International Business Machines Corporation Three-level cascode differential current switch
US5740201A (en) * 1993-12-10 1998-04-14 International Business Machines Corporation Dual differential and binary data transmission arrangement
US6088763A (en) * 1998-03-16 2000-07-11 International Business Machines Corporation Method and apparatus for translating an effective address to a real address within a cache memory
JP3264250B2 (ja) 1998-07-10 2002-03-11 日本電気株式会社 加算回路
WO2008038387A1 (fr) * 2006-09-28 2008-04-03 Fujitsu Limited Circuit à retenue anticipée, circuit de génération de retenue, procédé de retenue anticipée et procédé de génération de retenue

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3932734A (en) * 1974-03-08 1976-01-13 Hawker Siddeley Dynamics Limited Binary parallel adder employing high speed gating circuitry
US3970833A (en) * 1975-06-18 1976-07-20 The United States Of America As Represented By The Secretary Of The Navy High-speed adder
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
JPS55136726A (en) * 1979-04-11 1980-10-24 Nec Corp High voltage mos inverter and its drive method
JPS5731042A (en) * 1980-07-31 1982-02-19 Toshiba Corp Multiplaying and dividing circuits
EP0052157A1 (de) * 1980-11-15 1982-05-26 Deutsche ITT Industries GmbH Binärer MOS-Carry-Look-Ahead-Paralleladdierer
US4417314A (en) * 1981-07-14 1983-11-22 Rockwell International Corporation Parallel operating mode arithmetic logic unit apparatus
US4425623A (en) * 1981-07-14 1984-01-10 Rockwell International Corporation Lookahead carry circuit apparatus
JPS58211252A (ja) * 1982-06-03 1983-12-08 Toshiba Corp 全加算器
US4504924A (en) * 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates

Also Published As

Publication number Publication date
JPS60181925A (ja) 1985-09-17
IE57290B1 (en) 1992-07-15
US4730266A (en) 1988-03-08
EP0155019B1 (en) 1990-12-27
CA1229172A (en) 1987-11-10
KR850006089A (ko) 1985-09-28
IE850283L (en) 1985-08-09
JPH0438009B2 (https=) 1992-06-23
NL8400408A (nl) 1985-09-02
EP0155019A1 (en) 1985-09-18
DE3581094D1 (de) 1991-02-07

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