KR920020323A - 중앙연산처리장치 - Google Patents

중앙연산처리장치 Download PDF

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Publication number
KR920020323A
KR920020323A KR1019920005801A KR920005801A KR920020323A KR 920020323 A KR920020323 A KR 920020323A KR 1019920005801 A KR1019920005801 A KR 1019920005801A KR 920005801 A KR920005801 A KR 920005801A KR 920020323 A KR920020323 A KR 920020323A
Authority
KR
South Korea
Prior art keywords
address
processing unit
central processing
signal
arithmetic operators
Prior art date
Application number
KR1019920005801A
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English (en)
Other versions
KR950008221B1 (ko
Inventor
다카시 가와사키
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920020323A publication Critical patent/KR920020323A/ko
Application granted granted Critical
Publication of KR950008221B1 publication Critical patent/KR950008221B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

내용 없음

Description

중앙연산처리장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 프로세서에 따른 1실시예의 구성을 나타낸 블럭도,
제2도는 제1도에 도시된 동일어드레서신호 생성회로의 상세한 회로도,
제3도는 캐시 메모리의 일례를 나타낸 개념도.

Claims (1)

  1. 복수의 연산기(3,4)와, 이들 복수으 연산기(3,4)로부터 출력되는 어드레스신호의 임의의 비트를 비교해서 동일어드레스라는 것을 나타내는 동일 웨이 히트 신호를 생성하는 기억장치(1) 및, 상기 복수의 연산기(3,4)로부터 출력되는 어드레스신호의 일부 비트와 상기 동일 웨이 히트 신호로부터 동일어드레스의 동시액세스신호를 생성하여 상기 기억장치(1)에 동일어드레스의 동시액세스라는 것을 통지하는 액세스신호 생성회로(2)로 구성되어 있는 것을 특징으로 하는 중앙연산처리장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005801A 1991-04-24 1992-04-08 중앙연산 처리장치 KR950008221B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-094068 1991-04-24
JP3094068A JP2703418B2 (ja) 1991-04-24 1991-04-24 中央演算処理装置

Publications (2)

Publication Number Publication Date
KR920020323A true KR920020323A (ko) 1992-11-21
KR950008221B1 KR950008221B1 (ko) 1995-07-26

Family

ID=14100195

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005801A KR950008221B1 (ko) 1991-04-24 1992-04-08 중앙연산 처리장치

Country Status (3)

Country Link
US (1) US5742790A (ko)
JP (1) JP2703418B2 (ko)
KR (1) KR950008221B1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081873A (en) * 1997-06-25 2000-06-27 Sun Microsystems, Inc. In-line bank conflict detection and resolution in a multi-ported non-blocking cache
US6272597B1 (en) * 1998-12-31 2001-08-07 Intel Corporation Dual-ported, pipelined, two level cache system
US6928525B1 (en) * 2000-04-28 2005-08-09 Hewlett-Packard Development Company, L.P. Per cache line semaphore for cache access arbitration
US7117315B2 (en) * 2002-06-27 2006-10-03 Fujitsu Limited Method and apparatus for creating a load module and a computer product thereof
US7533232B2 (en) * 2003-11-19 2009-05-12 Intel Corporation Accessing data from different memory locations in the same cycle
US8886895B2 (en) * 2004-09-14 2014-11-11 Freescale Semiconductor, Inc. System and method for fetching information in response to hazard indication information
US7434009B2 (en) * 2004-09-30 2008-10-07 Freescale Semiconductor, Inc. Apparatus and method for providing information to a cache module using fetch bursts
US8117400B2 (en) * 2006-10-20 2012-02-14 Freescale Semiconductor, Inc. System and method for fetching an information unit
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953073A (en) * 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US4853846A (en) * 1986-07-29 1989-08-01 Intel Corporation Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
JPH0668735B2 (ja) * 1987-02-09 1994-08-31 日本電気アイシーマイコンシステム株式会社 キヤツシユメモリ−
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH01309159A (ja) * 1988-06-07 1989-12-13 Fujitsu Ltd マルチポートメモリ
JPH0215342A (ja) * 1988-07-04 1990-01-19 Matsushita Electric Ind Co Ltd メモリ装置
US4905141A (en) * 1988-10-25 1990-02-27 International Business Machines Corporation Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
JP2822588B2 (ja) * 1990-04-30 1998-11-11 日本電気株式会社 キャッシュメモリ装置

Also Published As

Publication number Publication date
US5742790A (en) 1998-04-21
KR950008221B1 (ko) 1995-07-26
JPH04323747A (ja) 1992-11-12
JP2703418B2 (ja) 1998-01-26

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