KR920010435B1 - Semiconductor integrated circuit - Google Patents

Abstract

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Description

[Name of invention]

Semiconductor integrated circuit

[Brief Description of Drawings]

1 is a circuit diagram showing a conventional CMOS inverter,

2 is a cross-sectional view illustrating the structure of a conventional CMOS inverter;

3, 4, 5, and 6 are cross-sectional views showing embodiments of the present invention in the order of manufacturing processes;

7 is a bird's eye view showing a first embodiment of the present invention;

8 is a cross-sectional view of a substrate used in the second embodiment of the present invention;

9 is a cross-sectional view of a second embodiment of the present invention;

10 is a cross-sectional view of a substrate used in the third embodiment of the present invention;

11 is a cross-sectional view of a third embodiment of the present invention;

12 is a cross-sectional view of a fourth embodiment of the present invention;

13 is a bird's eye view showing a fifth embodiment of the present invention;

14 is a bird's eye view of a sixth embodiment of the present invention;

Detailed description of the invention

[Technical Field]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits having p-channel FETs (field effect transistors) and n-channel FETs (C-MOS circuits: Complementary-MOS circuits).

[Background]

As a representative example of a semiconductor integrated circuit having an n-channel FET and a p-channel FET, there is a CMOS integrated circuit using an insulated gate field effect transistor (MOS transistor) as the FET.

The basic configuration of a CMOS integrated circuit is an inverter circuit composed of an n-channel MOS transistor 1 and a p-channel MOS transistor 2 as shown in the circuit diagram of FIG. In FIG. 1, (3) is an input terminal, (4) is an output terminal, (5) is a Vsseks character, and (6) is a Vcc terminal.

1 shows an n-channel MOS transistor 1 and p respectively formed in the p-type well region 9 and n-type well region 11 formed in the Si substrate 10 as shown in FIG. It consists of the channel MOS transistor 2. Although both p-type and n-type well regions are formed here, since the Si substrate 10 can also serve as either side, at least either side can cope with only one well.

In FIG. 2, an n ^- type well and a p ^- type well are formed on an n ^- type substrate. In Fig. 2, reference numeral 7 denotes an n ^F type region, 8 denotes a p ⁺ type region, 12 denotes a field insulating film for device isolation, 13 denotes a gate electrode, and 14 denotes an insulating film. 90) is a p-type region, and 91 is an n-type region.

The conventional CMOS structure is formed in a plane as shown in FIG. 2 and has a wide field oxide film 12 for electrically separating the n-channel MOS transistor 1 and the p-channel MOS transistor 2 from each other. In addition, since p-type wells and n-type wells have high impurity concentrations, it is necessary to isolate both wells when the breakdown voltage between them becomes a problem. In any of the above cases, high integration of the CMOS device is hindered. For example, in an integrated circuit having a gate length of about 2 μm, the width of the separation field oxide film 12 between the wells is about 10 μm, and about 1 μm is required about 5 μm.

The above known CMOS technology is described in Japanese Patent Laid-Open No. 49-44555 or Japanese Patent Laid-Open No. 49-33229. The so-called vertical MOS or V-gooive MOS having a similar structure in appearance is described in Japanese Patent Laid-Open No. 43-26823 or Japanese Patent Laid-Open No. 43-456.

[Initiation of invention]

It is an object of the present invention to provide a finer structure of separation between wells, which has been one of the biggest obstacles to the densification of semiconductor integrated circuits of conventional CMOS structures.

The gist of the present invention is formed by opposing a p well (n channel formation region) and an n well (p channel formation region), and providing a thin insulating region between both wells to increase the density of the CMOS integrated circuit.

According to the present invention, since the n-channel and p-channel MOS transistors are isolated by thin insulating regions, not only have a particularly significant effect on the high integration of CMOS integrated circuits and the prevention of latch leakage harmful to CMOS, but also particularly high transfer to minute regions. A transistor having conductance can be formed.

Best Mode of the Invention

[Examples of Figs. 3 to 7]

Hereinafter, a first embodiment of the present invention is shown in Figs. In addition, in all the drawings for demonstrating an embodiment, the thing which has the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

The first embodiment of the present invention is an example when the protruding pillars 18 and 19 are formed on the Si substrate 10. As shown in FIG. ³ , the impurity concentration is 10 by ion implantation or thermal diffusion, which is often used for the n-type Si substrate 10 (concentration of about 1-100 μm, about 1 × 10 ¹⁴ to 1x10 ¹⁷ cm ^-3 ). ^An n ⁺ type region 15 and a p ⁺ type region 16 of ²⁰ cm ⁻³ or more are formed. The n ⁺ type region 15 had a depth of about 0.2 to 1 μm and a p ⁺ type region of about 0.4 to 1.5 μm. At this time, since the Si substrate 10 was n-type, the periphery below the n ⁺ type region 15 was surrounded by the p-type well region 9. The p-type well region 9 has a depth of about 1 to 5 mu m. If the p-type well region 9 is self-aligned using a mask for forming the n ⁺ -type region 15, an extra region for matching the mask is not necessary and can be formed at a high density. Even if the same mask is used, the p-type well region 9 and the n ⁺ -type region 15 are formed to be surrounded by diffusion of impurities. Then, n ^- type or p ^- type epitaxial layer 17 is grown. The epitaxial layer 17 is formed to a thickness of about 0.5 to 2㎛. Then, as shown in FIG. 4, the protruding pillars 18 and 19 are formed by dry etching, and p-type dopandt and n-type dopant are ion-implanted, respectively, to thereby epi. The impurities added to the tactile layer 17 are canceled or increased so that the impurity concentrations are all desired values in the range of 10 ¹⁴ to 10 ¹⁷ cm ^-3 . As a result, the p-type protrusion pillar 18 and the n-type protrusion pillar 19 are formed.

Of course, when dry etching or ion implantation is carried out, a well-known photolithography technique is used to make a etch-resistant film or an ion-implantable film into a desired shape and use it as a so-called mask.

Thereafter, the insulating insulating film 20 for separation is formed between the two protruding pillars by thermal oxidation or CVD. This is the thickness between the p-type region 18 and the n-type region 19, and is formed at about 0.1 to 1 mu m.

When using the CVD method, the insulating insulating film 20 is evenly deposited on the main surface of the protruding pillar. Therefore, when the gap between the projection pillars 18 and 19 is deposited until the gap is buried, and then the solution etching or dry etching is performed as a whole, the insulating film 20 remains only in the space portion as shown in FIG. You can do that.

When the thermal oxide film is formed, the oxide film grows on both of the protruding pillars 18 and 19, and thermal oxidation is stopped at the seam seam where both sides stick, and then isotropic etching is performed to peel off the entire oxide film. Remove

Since the oxide film 20 is protected by the protruding pillars 18 and 19 and is not etched, the structure shown in FIG. 4 is obtained.

Thereafter, as shown in FIG. 5, a field oxide film 12 having a thickness of 200 to 100 nm is formed in a separation region by a LOCOS (Local Oxidation of Silicon) method or the like, and a gate oxide film 21 having a thickness of 5 to 100 nm is formed. It is formed by thermal oxidation. In this case, an oxide film such as silicon nitride film (Si ₃ N ₄ ) may be formed and oxidized in addition to the portion of the field oxide film 12.

After that, a film of polycrystalline Si, a high melting point metal, or a silicide thereof is deposited on the whole by sputtering or CVD, leaving a resist resin for dry etching on the wiring portion thereof, and then performing strong dry etching on the whole. do. Then, the remainder of the etching is generated in the side wall portions of the protruding pillars 18 and 19, which becomes the gate 13, and the thickness is about 0.1 to 0.8 mu m. The n ⁺ type region 161 was formed by ion implantation, diffusion, or the like, and the depth thereof was set to about 0.1 to 0.5 mu m.

Thereafter, as shown in FIG. 6, an interlayer insulating film 22 represented by CVD / PSG is deposited to a thickness of 0.5 to 1.0 mu m, a connection hole 24 is formed in a desired portion, and an electrode represented by A1 ( 231 to 233 are formed. As a result, the electrodes 231, 232, and 233 become the Vss terminal, the output terminal, and the Vcc terminal, respectively.

A bird's-eye view of the cross-sectional view of the structure of this embodiment shown in FIG. 5 is shown in FIG. The flat part 131 of the gate 13 is a part used for wiring and connection with an electrode.

[Examples of Figs. 8 and 9]

In the second embodiment of the present invention, when the same element as that of the first embodiment is formed on the insulating substrate, the n ⁺ type region 15 does not need to be electrically separated from the substrate 10, so that the density can be further increased. There is a number.

That is, as shown in FIG. 8, a thin Si substrate layer 101 is formed on the entire surface on the sapphire or single crystal spinel substrate 25, and the n ⁺ type region 15 and the p ⁺ type region 16 are formed in this layer. ), And the structure shown in FIG. 9 can be obtained by the same process as that described in FIGS. At this time, since the n ⁺ type region 15 and the p ⁺ type region 16 are completely separated by the insulating film 20 or the insulating substrate 25, it is not necessary to form the p type well 9 and the like. The interference effect of can be made very small. In FIG. 9, the field oxide film 12 can be thickened until it penetrates the Si substrate 101. In this way, separation from other elements can be made more complete.

The insulating film 20 must reach the insulating substrate 25 so as to adversely affect the Si substrate 101.

Therefore, when the insulating film 20 is formed by the CVD method, the Si substrate 101 needs to be etched before deposition.

[Examples of FIGS. 10 and 11]

In the third embodiment of the present invention, as shown in FIG. 10, an insulating substrate 25 such as a thermal oxide film, sapphire, spunnel, etc. is formed on the Si substrate 10 as an insulating substrate, and the Si substrate 10 is exposed. A silicon on insulator (SOI) -Si substrate 102 formed by a liquid lateral epitaxial growth method using a laser or a stream-heater in a seeded region 26 may be used. Although the SOI-monocrystalline Si substrate 102 can be formed without using the vertical region 26, it is generally possible to form a high quality crystal substrate 102 using the vertical region.

Thereafter, similarly to the embodiment of FIG. 9 described above, the integrated circuit of FIG. 11 can be formed. In FIG. 11, the vertical region 26 is omitted.

In this embodiment, since there is a Si substrate 10, a resistor, a capacitor, or the like may be formed on the substrate portion, and the CMOS transistor of the present invention formed by sandwiching the insulating film 25 therebetween may be used in combination. In addition, since the MOS transistor is formed on the surface of the Si substrate 10, and the CMOS transistor of the present invention can be formed over the insulating film 25 therebetween, the transistor of two layers can be formed, thereby increasing the function or the degree of integration. Can improve.

[Example 12]

In the embodiment of Fig. 11, the n ⁺ type regions 16 are all formed in the SOI-Si substrate layer 102, but either one may be formed in the vertical region 26. This embodiment is shown in FIG. In this way, one region (n ⁺ type region in FIG. 12) can be connected to the Si substrate 10, which is convenient when such a welding is used.

In the fourth embodiment of the present invention, the n-type protrusions 19 and the p-type protrusions 18 correspond to n-type wells and p-type wells of CMOS, respectively. It is isolated by the insulating film 20, and is significantly smaller than the width of 5 to 10 mu m of the isolation region of the conventional CMOS structure shown in FIG.

[Example 13]

In the embodiment of the present invention described above, the isolation region is filled with the insulating film 20, but the region may be filled with a material such as Si thermal oxide film SiO ² and single crystal Si. What is necessary is just to operate as an insulating area as a whole, The constituent material is not restrict | limited.

FIG. 13 shows a fifth embodiment of the present invention. This means that the isolation insulating region 20 of the embodiment shown in FIG. 6 is composed of the gate oxide film 21 and the gate 13, and the side surfaces of the Si protrusion pillars 18 and 19 are both gate oxide film 21. ), The gate 13 is embedded in an area sandwiched between the two protruding pillars. At this time, since the entire side surfaces of the protruding pillars 18 and 19 serve as transistor channels, a transistor having a large transfer conductance in a minute region can be obtained.

That is, in FIG. 6, only the interface between the protruding pillar 18 and the insulating film 21 serves as a channel. In this embodiment, since the gate 13 is present in the insulating film 20, The channel can also be formed on the side facing the channel.

Of course, the n ⁺ type region 15 must also exist up to the channel forming region. Specifically, the constitutions of FIGS. 9, 11, and 12 may be used. Similarly, the entire surface around the protruding pillar 18 can be used as a channel. The above is also applicable to the protruding pillar 19 in the same manner.

[Example 14]

14 shows a sixth embodiment of the present invention. Until now, in the embodiment of the present invention, p-type and n-type protrusion pillars 18 and 19 were each separated from each other, but the present embodiment has a plurality of p-type protrusion pillars and a plurality of n-type protrusion pillars. This is the case where they form a beam shape by being continuous with each other. A thick field oxide film 12 is also formed in a portion necessary for separation from an adjacent CMOS inverter. The gate oxide film 21 is formed on the side of the protruding beam, respectively, and the gate 13 is formed over the beam. 14 shows a case where two CMOS inverters are formed.

In the above embodiment, the p-type well region 9 must be formed. However, if the substrate 10 has a high resistance, the p-type well region 9 can be omitted. At this time, the substrate should be 100Ω ⁺ cm or more, preferably 1KΩ ⁺ cm or so.

The substrate concentration is 1x10 ¹³ -1x10 ¹⁺ cm ^-3 .

[Industry availability]

In the conventional CMOS transistor formed on the Si substrate, the n-channel and p-channel transistors interfere with each other, causing a so-called latch over, and the integrated circuit becomes inoperable or damaged.

CMOS transistors have become central transistors in MOS integrated circuits, which account for most of the semiconductor industry.

However, the advantages of CMOS transistors have been greatly diminished because these latches are one of the major factors that hinder the densification of CMOS integrated circuits.

The present invention not only eliminates this obstacle of the CMOS transistor, but also forms a channel in the vertical direction, so that a large current driving capability can be provided with a small planar area, which is more suitable for higher density than in the prior art, and is a CMOS integrated circuit. Applicable to the first half. Furthermore, the industrial value is enormous since it is possible to provide effective densification techniques for most MOS integrated circuits.

Claims (5)

A substrate having a semiconductor layer on at least a first major surface thereof, a first region of a first conductivity type formed in the semiconductor layer, a second region of a second conductivity type formed in the semiconductor layer, and formed in a columnar shape and having the first region A second semiconductor protrusion pillar region of the first conductive type formed in a columnar shape and formed in contact with at least a portion of the first semiconductor protrusion pillar of the second degree typical formed in contact with at least a portion thereof; A first separation region formed between the first semiconductor protrusion pillar region and the second semiconductor protrusion pillar region, a third region of the first conductivity type formed in the first semiconductor protrusion pillar region, and formed in the second semiconductor protrusion pillar region A first gate electrode formed on the first semiconductor protruding pillar region through a fourth region of a second conductivity type and a first gate insulating layer facing the first isolation region, and the first separation zero The semiconductor integrated circuit through a second gate insulating film that is opposite consisting of a second gate electrode formed on the second semiconductor region in the pillar. The semiconductor integrated circuit according to claim 1, wherein the substrate is an insulator and the first isolation region is in contact with the substrate. The semiconductor integrated circuit according to claim 1, wherein the substrate has a semiconductor layer formed on the semiconductor substrate via a first insulating film, and the first isolation region is in contact with the first insulating film. The semiconductor integrated circuit of claim 1, wherein the first isolation region comprises a first insulating layer, a second insulating layer, and a third gate electrode. A substrate having a semiconductor layer on at least a first major surface thereof, a first region of a first conductivity type formed in the semiconductor layer, a second region of a second conductivity type formed in the semiconductor layer, and formed in a columnar shape and having the first region And a second semiconductor protrusion pillar region of the first conductive type formed in a columnar shape with the first semiconductor protrusion pillar region of the second conductivity type formed to be in contact with at least a portion thereof. The first semiconductor projection pillar region formed in the first semiconductor projection pillar region, the fourth semiconductor region of the second conductivity formation formed in the second semiconductor projection pillar region, and the first semiconductor projection pillar region via a first insulating film. A first gate electrode formed thereon and a second gate electrode formed on the second semiconductor protrusion pillar region via a second insulating film, and a first isolation region formed between the first semiconductor protrusion pillar region and the second semiconductor protrusion pillar region. In a semiconductor integrated circuit, the substrate is an insulator, and the first isolation region is in contact with the substrate.

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