KR910016119A - Failure Distribution Control Device for Digital Distribution Line - Google Patents

Failure Distribution Control Device for Digital Distribution Line Download PDF

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Publication number
KR910016119A
KR910016119A KR1019900002650A KR900002650A KR910016119A KR 910016119 A KR910016119 A KR 910016119A KR 1019900002650 A KR1019900002650 A KR 1019900002650A KR 900002650 A KR900002650 A KR 900002650A KR 910016119 A KR910016119 A KR 910016119A
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KR
South Korea
Prior art keywords
circuit
signal
current
ground fault
phase
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Application number
KR1019900002650A
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Korean (ko)
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KR920009852B1 (en
Inventor
이주역
임태현
Original Assignee
김광우
주식회사 진광
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Priority to KR1019900002650A priority Critical patent/KR920009852B1/en
Publication of KR910016119A publication Critical patent/KR910016119A/en
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Publication of KR920009852B1 publication Critical patent/KR920009852B1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/26Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured

Abstract

내용 없음No content

Description

계수형 배전선로 고장구간 제어장치Failure Distribution Control Device for Digital Distribution Line
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
첨부된 도면은 본 발명에 다른 계수형 배전선로 고장구간 제어장치의 회로도이다.The accompanying drawings are circuit diagrams of an apparatus for controlling fault zones according to the present invention.

Claims (1)

  1. 회로차단기 또는 리크로져의 후단부와 부하의 전단부에 설치되어 부하에 과부하가 발생될시 상전류를 발생하는 상전류 전압발생회로(4)와, 상전류전압발생시 동작하여 하이신호를 발생하는 상동작레벨회로(9)와, 상기 상동작레벨회로(9)에서 출력된 신호에 의해 상전류의 이상상태를 검출하는 고장검출기억회로(10)와, 상기의 고장검출기억회로(10)의 동작시 상타이밍신호를 발생하는 상타이밍회로(11) 및, 상기 회로(11)에서 출력된 신호에 의해 동작하여 트립코일(TC)을 작동시키기 위한 출력을 발생하는 상출력회로(12)로된 과부하 검출부와, 지락에 의한 전류발생시 지락전류를 생성하는 지락전류전압발생회로(26)와, 지락전류전압 발생시 동작하여 하이신호를 생성하는 지락동작 레벨회로(27)와, 상기의 지락동작레벨회로(27)에서 출력된 신호에 의해 지락전류의 이상상태를 검출하는 고장검출기억회로(28)와, 상기의 고장검출 기억회로(28)의동작시 지락타이밍 신호를 발생하는 지락타이밍회로(29)및, 상기의 지락타이밍회로에서 출력된 신호에 의해 동작하여 트립코일(TC)을 작동시키기 위한 출력을 발생시키는 지락출력회로(30)로된 지락상태 검출부와, 선로의 전류를 감지하는 선로전류감지부(14)와, 감지된 선로전류를 지연시켜 선로에 흐르는 돌입전류를 억제하기 위해 돌입전류억제회로(25)와, 상기의 상전류전압과 소정의 로크레벨전압을 비교하는 로크 동작레벨 비교회로(19)와, 상기의 비교된 로크레벨신호에 의해 동작하여 로크상태를 검출하는 로크검출기억회로(20)와, 상기 로크검출기억회로의 동작시 로크타이밍신호를 발생하는 로크타이밍회로(21) 및, 상기 로크타이밍회로에서 출력된 신호에 의해 동작하여 트립코일(TC)을 작동시키기 위한 출력회로(22)로 구성시켜서 된 배전선로 고장구간 제어장치에 있어서 ; 부하에 과부하가 인가된 상태에서 입력측이 정전되었을 경우에는 상기의 고장검출기억회로(10)의 출력과, 상기 선로전류감지부(14)의 출력신호에 의해 동작하여 펄스를 발생하기위한 펄스발생회로(15)와, 상기의 펄스발생회로에서 발생된 펄스신호에 의해 동작하여 1회 카운팅을 수행하며, 입력측의정전이 계속될 경우에는 상기의 펄스발생회로에서 발생된 펄스신호에 의해 2회 카운팅을 하여 트립코일(TC)을 구동하기위한 카운터회로(16)와, 상기의 펄스발생회로(15)에서 1개의 펄스신호가 발생된 후 입력측이 정상으로 복귀되었을 경우상기의 카운터회로의 동작을 리셋트시키기 위한 시간지연회로(17) 및 상기 지연회로(17)에 의해 동작하여 상기 카운터회로(16)에 의한 2회 카운팅전에는 트립코일구동회로(13)에 신호를 제공하지 않도록 하여 트립코일(TC)의 구동을 정지시키기 위한 리셋회로(18)로 구성시켜서 됨을 특징으로 하는 계수형 배전선로 고장구간 제어장치.It is installed at the rear end of the circuit breaker or recloser and the front end of the load, and the phase current voltage generation circuit 4 which generates phase current when the load is overloaded, and the phase operation level circuit which operates when the phase current voltage is generated to generate high signal (9), a fault detection memory circuit 10 for detecting an abnormal state of phase current by a signal output from the phase operation level circuit 9, and an phase timing signal during operation of the fault detection memory circuit 10 described above. An overload detection section comprising a phase timing circuit 11 generating a phase and a phase output circuit 12 generating an output for operating the trip coil TC by operating by a signal output from the circuit 11, and a ground fault. Outputs from a ground fault current voltage generating circuit 26 for generating a ground fault current when a current is generated by the ground fault, a ground fault operating level circuit 27 for generating a high signal by operating when a ground fault current voltage is generated, and the ground fault operating level circuit 27 described above. By old signal A fault detection memory circuit 28 for detecting an abnormal state of the current, a ground fault circuit 29 for generating a ground timing signal during operation of the fault detection memory circuit 28, and the above ground fault timing circuit. A ground fault detection section comprising a ground fault output circuit 30 that operates by a signal to generate an output for operating the trip coil TC, a line current detection section 14 for detecting current of the line, and a sensed line current The inrush current suppression circuit 25, the lock operation level comparison circuit 19 for comparing the phase current voltage and the predetermined lock level voltage to delay the inrush current flowing in the line, and the above-described compared lock level. A lock detection memory circuit 20 that operates by a signal to detect a lock state, a lock timing circuit 21 that generates a lock timing signal upon operation of the lock detection memory circuit, and a signal output from the lock timing circuit. of It operates according to the failure to by an output circuit 22 for operating the trip coil (TC) distribution line interval control device; When the input side is out of power in the state where the load is overloaded, the pulse generating circuit for generating a pulse by operating by the output of the fault detection memory circuit 10 and the output signal of the line current sensing unit 14 is generated. (15) and counting is performed once by operating on the pulse signal generated by the above-mentioned pulse generating circuit, and counting twice by the pulse signal generated by the above-mentioned pulse generating circuit when power failure on the input side is continued. The counter circuit 16 for driving the trip coil TC and the operation of the counter circuit when the input side returns to normal after one pulse signal is generated in the pulse generating circuit 15. The trip coil TC is operated by the time delay circuit 17 and the delay circuit 17 so as not to provide a signal to the trip coil drive circuit 13 before counting twice by the counter circuit 16. Of A counting distribution line fault section control device, characterized in that it comprises a reset circuit (18) for stopping driving.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002650A 1990-02-28 1990-02-28 Automatic section switch KR920009852B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002650A KR920009852B1 (en) 1990-02-28 1990-02-28 Automatic section switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002650A KR920009852B1 (en) 1990-02-28 1990-02-28 Automatic section switch

Publications (2)

Publication Number Publication Date
KR910016119A true KR910016119A (en) 1991-09-30
KR920009852B1 KR920009852B1 (en) 1992-10-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900002650A KR920009852B1 (en) 1990-02-28 1990-02-28 Automatic section switch

Country Status (1)

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KR (1) KR920009852B1 (en)

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Publication number Publication date
KR920009852B1 (en) 1992-10-31

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