KR910008380B1 - Adress generator circuit for zoom function - Google Patents

Abstract

The address generator for the zoom function comprises a decoder (14) generating a zoom control signal, and the first and the secodn position control selection signals by decoding the input zoom function command and zoom position data at a microprocessor (13) multiplexers (15,16,17,18) transmiting the row and column addresses, a chrominance subcarrter and a horizontal synchronous signals, and vertical (19) and horizontal (20) counters transmitting the row and column addresses to the field memory.

Description

Address Generation Circuit for Zoom Function

1 is a conventional enlarged section centered state diagram.

2 is a circuit diagram of one embodiment of the present invention.

3 is an enlarged section center point and a memory read start point.

* Explanation of symbols for main parts of the drawings

13: micom 14: command decoder

15-18: 1-4 Multiplexer 19: Vertical Counter

20: horizontal counter 24: row address

25: column address

The present invention relates to a zoom function circuit for enlarging a screen of a section of a single screen displayed on a screen of a monitor to a full screen size in a digital image processing apparatus, and in particular, an operator of a screen of a section to be enlarged. To adjust the circuit according to the selection of

In general, a digital image processing apparatus temporarily stores one field of image data in a field memory, reads it out, converts it into an analog image signal, and displays it on a monitor through a monitor driver.

In addition, the zoom function refers to an enlarged screen of a section of one screen displayed on the screen of the monitor to one screen. In order to perform the zoom function, the digital image processing apparatus reads out the image data stored at some address interval address among the image data stored in the field memory, converts the image data into an analog image signal, and outputs the image to the monitor through the monitor driver. It will enlarge to size.

However, the conventional zooming function is based on the entirety of five points (hereinafter referred to as the center point of the magnification section) displayed on the screen for selecting the zooming function as shown in FIG. 1, for example. Since an arbitrary one of the 1/4 parts of the screen is selected and the screen is enlarged 4 times to display the full screen, there is a problem in that the selection section of the screen to be enlarged is limited.

However, as described above, since the zoom function allows the user to enlarge and view a desired portion, it is well known that the larger the center point of the enlargement, the more free selection the enlargement section can be.

Therefore, an object of the present invention is to set the horizontal and vertical address to select the screen around the center of any magnification section for at least six magnification section center points, the image data stored in the address address of a certain section stored according to the operator's selection The present invention provides an address generating circuit for a zoom function that can enlarge a partial section screen to a full screen by reading a.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 2 is a circuit diagram of an embodiment of the present invention, in which a zoom control signal and first, Inputs a command decoder 14 for generating a 2 zoom position selection signal and a first-fourth row address generation control signal generated from the microcomputer 13 and selects a first position applied from the command decoder 14. A first multiplexer 15 for selecting and outputting one row address among the first to fourth row address generation control signals according to a logic state of the signals C1 and C2, and a second generation signal generated from the microcomputer 13; The first-fourth column address generation control signals are inputted according to a logic state of the second position selection signals C3 and C4 inputted from the command decoder 14. A second multiplexer 16 which selects and outputs one column address, and a color subcarrier 8 and a 1 / constant color subcarrier 9 (hereinafter referred to as Fsc / n) from a division circuit (not shown). A third multiplexer 17 for selectively outputting the color carrier 8 or the Fsc / n 9 according to the logic state of the zoom control signal 1 applied from the command decoder 14, and A horizontal synchronizing signal 11 and a 1 / constant horizontal synchronizing signal 10 (hereinafter referred to as Hsyn / n) are inputted from the frequency divider circuit and the zoom control signal 1 applied from the comment decoder 14 A fourth multiplexer 18 for selectively outputting the horizontal synchronizing signal 11 or Hsyn / n 10 according to the logic state, and a vertical synchronizing signal 12 applied from the frequency divider circuit to the load terminal LD1. Input the output of the first multiplexer 15 and then horizontally from the fourth multiplexer 18 to the clock terminal CLK1. Whenever the synchronization signal 11 or the Hsyn / n 10 is applied, the row address 24 is generated by adding one by one to the data input from the first multiplexer 15 to generate the field address (not shown). The output of the second multiplexer 16 is inputted by a vertical counter 19 for outputting the signal and a horizontal synchronization signal 11 applied from the frequency divider circuit to the load terminal LD2, and then the third multiplexer 17. Whenever the color subcarrier 8 or the Fsc / n (9) is applied from the clock terminal CLK2 to the clock terminal CLK2, the column address 25 is generated by counting one by one to the data input from the second multiplexer 16. It consists of the horizontal counter 20 which outputs to a memory.

FIG. 3A shows each section that can be enlarged around the points when nine enlarged section center points 1-9 are set, for example, and FIG. 3B shows each point 1-9 of FIG. 3A. The memory read start point (S1-S9) is shown when the screen is enlarged.

The present invention will be described in detail based on the above configuration.

First, assume that the Fsc / n (9) input to the third multiplexer 17 is divided into two color subcarriers 8 (n = 2), and the Hsyn / n (10) input to the fourth multiplexer 18 is performed. Is assumed to be two divisions of the horizontal synchronizing signal 11 (n = 2).

If it is assumed as described above, the size that is enlarged to the size of the monitor screen is a section corresponding to 1/4 of the monitor screen.

When the viewer is watching a television broadcast program, the user inputs only the zoom function and the information about the section of the monitor screen to be enlarged in order to enlarge a section of the screen displayed on the monitor screen. The zoom position data is generated and synchronized to a predetermined clock pulse to form a serial form, and then transmitted to the command decoder 14. The micom 13 also applies a strobe signal to the command decoder 14.

At this time, the command decoder 14 decodes the zoom function command and zoom position data to generate a zoom control signal 1 using the zoom function command data, and selects first and second zoom positions using the zoom position data. Generate signals C1-C4. The zoom control signal 1 is applied to the third and fourth multiplexers 17 and 18 and the first zoom position selection signals C1 and C2 are the two selection terminals LS1 and LS2 of the first multiplexer 15. The second zoom position selection signals C3 and C4 are output to the two selection terminals LS3 and LS4 of the second multiplexer 16, respectively.

A first row address generation control signal indicating the vertical positions of the starting points S1 and S2 and S3 shown in FIG. 3B through the four bus lines 2-4 and 21, and a second indicating the vertical positions of S4, S5 and S6 A row address generation control signal, a third row address generation control signal indicating the vertical positions of S7 and S8 and S9 and a fourth row address generation control signal for row address generation control in a state in which the zoom function is not executed (Normal Mode) The first multiplexer 15 for inputting the first multiplexer 15 selects one of the first to third row address generation control signals based on a logic value of the two bits of the first zoom position selection signals C1 and C2. Pass it to the input port of.

In addition, the second multiplexer 16 which inputs two-bit 2-zoom position selection signals C3 and C4 from the command decoder 14 also depends on the logic value of the second zoom position selection signals C3 and C4. First column address generation control signal indicating the horizontal positions of the starting points S1, S4 and S7 input through the four bus lines 5-7 and 22, and second column address generation indicating the horizontal positions of the starting points S2, S5 and S8 The horizontal counter by selecting one of the control signal, the third column address generation control signal indicating the horizontal positions of the start points S3 and S6 and S9 and the fourth column address generation control signal for the column address generation control when the zoom function is not executed. Transfer it to the input port of (20).

On the other hand, the third multiplexer 17, which inputs the zoom control signal 1 from the command decoder 14, receives the color part carrier 8 and Fsc / that are pressurized from the division circuit by the logic state of the zoom control signal 1. The Fsc / 2 (9) is selected from 2 (9) and output to the clock terminal CLK2 of the horizontal counter 20. In addition, the fourth multiplexer 18 for inputting the horizontal synchronizing signal 11 or the Hsyn2 10 from the frequency division circuit also performs the horizontal synchronizing according to the logic state of the zoom control signal 1 applied from the command decoder 14. The Hsyn / 2 (10) is selected from the signal 11 and the Hsyn / 2 (10) and output to the clock terminal CLK2 of the vertical counter 19.

Then, the vertical counter 19 applies one of the first to third row address generation control signals applied from the first multiplexer 15 to the load terminal LD1 from the frequency divider circuit 12. Input during the retrace period of time, and each time Hsyn / 2 (10) is applied from the fourth multiplexer 18 to the clock terminal CLK1 during the vertical injector period by one to the input row address generation control signal. This adds a row address 24 that changes by one every two horizontal syringes and outputs it to the field memory through the output port.

On the other hand, the horizontal counter 20 also retraces the horizontal synchronization signal 11 to which one of the first to third column address generation control signals applied from the second multiplexer 16 is applied from the frequency divider circuit to the load terminal LD2. After inputting for a period, whenever a pulse of Fsc / 2 (9) is applied from the third multiplexer 17 to the clock terminal CLK2 during the horizontal syringe interval, 1 is input to the input column address generation control signal. By counting each bit, a column address 25 that increases by one every two periods of the color carrier 8 is generated and output to the field memory through the output port. At this time, the field memory reads out image data stored in a storage area corresponding to a quarter of the screen for one field period by the columns and row addresses 25 and 24 of the horizontal counter 20 and the vertical counter 19. The same image data is read out every two horizontal scanning periods, and the image data is read out once every two periods of the color carrier.

As described above, the memory read start points 1-9 determined by the first to third row addresses and the first to third column addresses are shown in the table.

In the above table, S1-S9 in parentheses means the center point of the section to be enlarged.

If the zoom function is not selected, the first and second multiplexers 15 and 16 select the fourth row address and the fourth column address, and input them to the resin and the horizontal counters 19 and 20, respectively. And the clocks input to the fourth multiplexers 17 and 18 are the color carrier 8 and the horizontal synchronization signal 11, respectively.

As described above, the present invention can increase the number of center points of the enlargement section, thereby further subdividing the enlargement section. As a result, the user can select a more satisfactory point because the selection range becomes wider when the user selects the enlargement section. have.

Claims (1)

An image processing apparatus having a microcomputer 13, a field memory, and a divider circuit, and setting a plurality of magnification center points on a screen to realize a zoom function, wherein a zoom function command and zoom position data are inputted from the microcomputer 13 A command decoder 14 for generating a zoom control signal 1 and first and second zoom position selection signals by decoding, and a low advance generation control signal for the center point of each magnification section are input from the microcomputer 13, and the A first multiplexer 15 for selecting and outputting one row address among the row address generation control signals according to a logic state of the first position selection signal applied from the command decoder unit 14, and for each center section center point; Logic state of a second position selection signal inputted from the microcomputer 13 and a column address generation control signal from the command decoder 14 Accordingly, the second multiplexer 16 which selects and outputs one column address among the column address generation control signals, and the color part carrier 8 and the color part carrier 9 of 1 / predetermined period are inputted from the frequency divider circuit. A third multiplexer 17 for selectively outputting the color carrier 8 or 1 / constant color carrier 9 according to the logic state of the zoom control signal 1 applied from the decoder 14, and The horizontal synchronizing signal 11 is inputted from the frequency divider circuit and the horizontal synchronizing signal 11 according to the logic state of the zoom control signal 1 applied from the command decoder 14 by inputting the horizontal synchronizing signal 10 of 1 / constant. 4th multiplexer 15 by means of a fourth multiplexer 18 for selectively outputting 1 / a constant receive signal and a vertical synchronization signal 12 applied from the frequency divider circuit to the load terminal LD1. Input the output of the fourth multi Whenever the horizontal synchronizing signal 11 or the 1 / constant horizontal synchronizing signal 10 is applied from the lexer 18 to the clock terminal CLK1, counting is performed by adding 1 to the data input from the first multiplexer 15. By the vertical counter 19 which generates a row address 24 and outputs it to the field memory, and the horizontal synchronization signal 11 applied from the division circuit to the load terminal LD2. A second output multiplexer (16) is generated whenever a color subcarrier 8 or a 1 / constant color subcarrier 9 is applied from the third multiplexer 17 to the clock terminal CLK2. And a horizontal counter (20) which generates a column address (25) by counting the data inputted from the data by 1) and outputs it to the field memory.

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