KR910002555B1 - Cache memory circuit using dual port memories - Google Patents
Cache memory circuit using dual port memoriesInfo
- Publication number
- KR910002555B1 KR910002555B1 KR8803329A KR880003329A KR910002555B1 KR 910002555 B1 KR910002555 B1 KR 910002555B1 KR 8803329 A KR8803329 A KR 8803329A KR 880003329 A KR880003329 A KR 880003329A KR 910002555 B1 KR910002555 B1 KR 910002555B1
- Authority
- KR
- South Korea
- Prior art keywords
- cache memory
- memory circuit
- dual port
- port memories
- memories
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0853—Cache with multiport tag or data arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62073010A JPS63240651A (ja) | 1987-03-28 | 1987-03-28 | キヤツシユメモリ |
JP62-73010 | 1987-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880011673A KR880011673A (ko) | 1988-10-29 |
KR910002555B1 true KR910002555B1 (en) | 1991-04-24 |
Family
ID=13505941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR8803329A KR910002555B1 (en) | 1987-03-28 | 1988-03-26 | Cache memory circuit using dual port memories |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0287844A3 (ko) |
JP (1) | JPS63240651A (ko) |
KR (1) | KR910002555B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02224043A (ja) * | 1988-11-15 | 1990-09-06 | Nec Corp | キャッシュメモリ |
JP3102594B2 (ja) * | 1991-02-19 | 2000-10-23 | 松下電器産業株式会社 | キャッシュメモリ装置 |
DE69615279T2 (de) * | 1995-06-06 | 2002-06-27 | Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto | Cache-Speicheranordnung mit gleichzeitigem Etikettenvergleich |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4527238A (en) * | 1983-02-28 | 1985-07-02 | Honeywell Information Systems Inc. | Cache with independent addressable data and directory arrays |
US4718039A (en) * | 1984-06-29 | 1988-01-05 | International Business Machines | Intermediate memory array with a parallel port and a buffered serial port |
-
1987
- 1987-03-28 JP JP62073010A patent/JPS63240651A/ja active Pending
-
1988
- 1988-03-25 EP EP19880104885 patent/EP0287844A3/en not_active Withdrawn
- 1988-03-26 KR KR8803329A patent/KR910002555B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0287844A3 (en) | 1990-09-26 |
EP0287844A2 (en) | 1988-10-26 |
JPS63240651A (ja) | 1988-10-06 |
KR880011673A (ko) | 1988-10-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060410 Year of fee payment: 16 |
|
LAPS | Lapse due to unpaid annual fee |