KR910000522Y1 - Sonic data separating circuit from digital input signal - Google Patents

Abstract

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Description

Voice data signal separation circuit of digital input signal

1 is an explanatory diagram showing a frame configuration of a digital input signal.

2 is an embodiment of a voice data signal separation circuit of the present invention.

FIG. 3 is an explanatory diagram showing parallel data signals inputted with 1 x 16 latches of FIG.

4A-4I are operational waveform diagrams of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: PLL 20: Clock Generator

30 latch 40 demodulator

50: sync detector 60: flip-flop

70: 1 × 32 latch 80: 1 × 16 latch

The present invention relates to a voice data signal separation circuit of a digital input signal which separates and outputs only a voice data signal from a digital input signal in a digital device such as a digital audio tape recorder and a digital amplifier.

Looking at the frame configuration of the digital input signal processed by the digital device, as shown in FIG. That is, the digital input signal is composed of 32 time slots, of which 0-3 time slots are synchronous signal areas, 4-11 time slots are sub-code signal areas, and 12-27 time slots are voice data signal areas. The 28-31 time slot is an information data signal area. In the voice data signal region of the 12-27 time slot, the voice data signal is bi-phase modulated, and the digital input signal having such a configuration is input into two lines, a signal line and a ground line. There is no clock line for supplying a clock signal.

When the voice data signal is separated from the digital input signal in the voice data signal region of 12-27 timeslot, it is conventionally separated using a custom integrated device. However, custom integrated devices are very expensive and have a problem of increasing the production cost of the device.

Therefore, an object of the present invention is to provide a voice data signal separation circuit having a simple configuration for separating a voice data signal from a digital input signal without using a custom integrated device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings of FIGS. 2 to 4.

2 is a circuit diagram of a voice data signal separation circuit of the present invention, in which a digital input signal DI is simultaneously connected to a demodulator 40 and a synchronous detection 50 through a latch 30 driven by a PLL 10. The demodulator 40 applies the output data DA to the 1 × 32 latch 70 so as to detect only the voice data signals in parallel by the 1 × 16 latch 80 and output them in series.

In this case, the 1 × 32 latch 70 and the 1 × 16 latch 80 receive the clock signal CLK from the clock generator 20 connected to the PLL 10 and use the same as a transfer signal. The load clock signal of the output signal (B, M, W) of the synchronous detector 50 is connected to the or gate (OR2) to drive the flip-flop 60 to determine the left and right channel data application signal (LRCK) Configure. In this configuration, since there is no separate clock line, the digital input signal DI input as shown in FIG. 4A is input to the clock generator 20 through the PLL 10, as shown in FIG. 4I. Generate a clock signal CLK.

The latch 30 operates according to the output signal of the PLL 10 so that the digital input signal DI is input to the demodulator 40 and the synchronous detector 50 through the latch 30. Then, since the demodulator 40 inversely modulates the phase-modulated digital input signal DI and outputs the 1 × 32 latch 70, the 1 × 32 latch 70 outputs the 1 × 32 latch 70. Since the 1 × 32 latch 70 is output by inversely modulating the phase-modulated digital signal DI, the 1 × 32 latch 70 outputs the digital signal DI output from the demodulator 40 to the clock generator 20. The shift is made in accordance with the output clock signal CLK.

When the sync detector 50 detects the sync signal and outputs the output signals B, M, and W as shown in FIGS. 4B-4D, the output signals B, M, and W output the oragate ORI. As shown in FIG. 4E, the logic terminal 1 is applied to the load terminal LD of the 1 × 32 latch 70, so that the 1 × 16 latch 80 is connected to the 1 × 32 latch 70 as shown in FIG. 3. After the voice data signals located at Q23-Q8 in parallel are loaded in parallel, they are output in series as shown in FIG. 4F according to the clock signal CLK of the clock generator 20.

Here, since the position where the synchronization signal is actually detected is the third time slot of the next frame, the subcode is included in the contents Q0-Q7 of the 1 × 32 latch 70 at the moment when the synchronization signal is detected. Voice data is located in Q8-Q23, information data is located in Q24-Q27, and the synchronization signal of the next frame is located in Q28-Q31.

Therefore, at this time, the data loaded into the 1 × 16 latch 80 is the voice data signal of the frame preceding the synchronization signal, and the data following the synchronization signal is loaded into the 1 × 32 latch 70 again.

Here, the digital input signal DI will be described. In the digital audio tape recorder, a synchronous signal is inserted as a B signal every 192 bits, has a B synchronous signal, and alternates W and M synchronous signals from the next frame. A synchronous signal detected using one unit of 192 bits always appears in the order of B → W → M → W → M → W.

Therefore, the output signals B, W, and M detected by the synchronous detector 50 are used as the ORA gate OR1 as the parallel load signal of the 1 × 16 latch 80, and the left and right channel data application signals LRCK are used. In order to generate the output signal (B, M) to the OR gate (OR2), as shown in Figure 4g and the logic signal and the output signal (W), respectively, the input terminals (R, S) of the flip-flop (60) As shown in FIG. 4h, the left and right channel data applying signals LRCK are generated as the output signals.

As described above, according to the present circuit, the conventional custom integrated circuit that separates the voice data signal from the digital input signal can be coped with the original design circuit, thereby improving the cost increase factor of the product using the expensive custom integrated device. It has an effect.

Claims (1)

A PLL 10 for detecting a phase of an input digital input signal DI, a clock generator 20 for generating a clock signal CLK according to an output signal of the PLL 10, and a PLL 10; A latch 30 for storing and outputting the digital input signal DI according to the output signal, a demodulator 40 for demodulating the output signal of the latch 30, and a synchronization signal from the output signal of the latch 30. The synchronous detector 50 which detects and outputs the output signals B, M and W, and the output signal of the OR gate OR2 which is set by the output signal W and logically sums the output signals B and M. The flip-flop 60 resets the left and right channel data applying signals LRCK and resets the output signal of the demodulator 40 according to the clock signal CLK and outputs the output signal in parallel. A latch 70 and a 1 × 16 latch 80 for loading the audio data signals of Q23-Q8 of the 1 × 32 latch 70 and outputting them serially in accordance with the clock signal CLK; And an OR gate (OR1) for logically adding the output signals (B, M, W) and applying them to the 1 × 16 latches (80) as load signals.