KR900019233A - 주변회로에서의 접촉 홀의 형상 및 종횡비를 개선하기 위해 셀 트랜지스터위에 형성되는 콘덴서를 구비하는 메모리 셀과 그 주변 회로로 구성되는 다이내믹 랜덤 액세스 메모리장치와 그 제조방법 - Google Patents

주변회로에서의 접촉 홀의 형상 및 종횡비를 개선하기 위해 셀 트랜지스터위에 형성되는 콘덴서를 구비하는 메모리 셀과 그 주변 회로로 구성되는 다이내믹 랜덤 액세스 메모리장치와 그 제조방법

Info

Publication number
KR900019233A
KR900019233A KR1019900006624A KR900006624A KR900019233A KR 900019233 A KR900019233 A KR 900019233A KR 1019900006624 A KR1019900006624 A KR 1019900006624A KR 900006624 A KR900006624 A KR 900006624A KR 900019233 A KR900019233 A KR 900019233A
Authority
KR
South Korea
Prior art keywords
peripheral circuit
manufacturing
random access
improve
contact hole
Prior art date
Application number
KR1019900006624A
Other languages
English (en)
Other versions
KR940000307B1 (ko
Inventor
신이찌로우 이께마스
Original Assignee
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤 filed Critical 후지쓰 가부시끼가이샤
Publication of KR900019233A publication Critical patent/KR900019233A/ko
Application granted granted Critical
Publication of KR940000307B1 publication Critical patent/KR940000307B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019900006624A 1989-05-10 1990-05-10 주변회로에서의 접촉 홀의 형상 및 종횡비를 개선하기 위해 셀 트랜지스터위에 형성되는 콘덴서를 구비하는 메모리 셀과 그 주변 회로로 구성되는 다이내믹 랜덤 액세스 메모리장치와 그 제조방법 KR940000307B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-116402 1989-05-10
JP1116402A JPH0824169B2 (ja) 1989-05-10 1989-05-10 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
KR900019233A true KR900019233A (ko) 1990-12-24
KR940000307B1 KR940000307B1 (ko) 1994-01-14

Family

ID=14686160

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900006624A KR940000307B1 (ko) 1989-05-10 1990-05-10 주변회로에서의 접촉 홀의 형상 및 종횡비를 개선하기 위해 셀 트랜지스터위에 형성되는 콘덴서를 구비하는 메모리 셀과 그 주변 회로로 구성되는 다이내믹 랜덤 액세스 메모리장치와 그 제조방법

Country Status (5)

Country Link
US (2) US5637522A (ko)
EP (1) EP0398569B1 (ko)
JP (1) JPH0824169B2 (ko)
KR (1) KR940000307B1 (ko)
DE (1) DE69031243T2 (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2818964B2 (ja) * 1990-03-30 1998-10-30 三菱電機株式会社 積層構造の電荷蓄積部を有する半導体記憶装置の製造方法
DE4143485C2 (de) * 1990-03-30 1995-09-28 Mitsubishi Electric Corp Zusammengesetzte Kondensatorstruktur
KR100249268B1 (ko) * 1990-11-30 2000-03-15 가나이 쓰도무 반도체 기억회로장치와 그 제조방법
KR920017248A (ko) * 1991-02-18 1992-09-26 문정환 반도체 메모리 소자의 커패시터 제조방법
US5270243A (en) * 1993-03-22 1993-12-14 Industrial Technology Research Institute Dram peripheral circuit contact aspect ratio improvement process
KR0140644B1 (ko) * 1994-01-12 1998-06-01 문정환 반도체 메모리장치 및 그 제조방법
JP3146962B2 (ja) * 1995-12-14 2001-03-19 日本電気株式会社 半導体記憶装置およびその製造方法
FR2752336B1 (fr) * 1996-08-09 1999-05-14 Sgs Thomson Microelectronics Condensateur dans un circuit integre
JPH10242419A (ja) * 1997-02-27 1998-09-11 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
FR2784799B1 (fr) * 1998-10-14 2003-10-03 St Microelectronics Sa Cellule memoire
JP3957945B2 (ja) 2000-03-31 2007-08-15 富士通株式会社 半導体装置及びその製造方法
FR2816110B1 (fr) * 2000-10-27 2003-03-21 St Microelectronics Sa Lignes de bit en memoire dram
KR100526889B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 핀 트랜지스터 구조
KR100647775B1 (ko) * 2004-12-01 2006-11-23 엘지.필립스 엘시디 주식회사 박막 트랜지스터 기판 및 제조 방법
KR100693812B1 (ko) * 2006-02-11 2007-03-12 삼성전자주식회사 반도체 장치 및 그 제조 방법, 반도체 장치의 센스 앰프 및그 형성 방법
KR101110543B1 (ko) * 2010-04-21 2012-02-09 주식회사 하이닉스반도체 고집적 반도체 장치
US8431995B2 (en) * 2010-05-13 2013-04-30 International Business Machines Corporation Methodology for fabricating isotropically recessed drain regions of CMOS transistors
US8716798B2 (en) 2010-05-13 2014-05-06 International Business Machines Corporation Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors
US9443872B2 (en) * 2014-03-07 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
JPS59231851A (ja) * 1983-06-14 1984-12-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリセル
JPS61125152A (ja) * 1984-11-22 1986-06-12 Fujitsu Ltd 半導体装置の製造方法
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
US4793975A (en) * 1985-05-20 1988-12-27 Tegal Corporation Plasma Reactor with removable insert
JPH0712058B2 (ja) * 1985-06-27 1995-02-08 株式会社東芝 半導体装置およびその製造方法
EP0224213A3 (en) * 1985-11-22 1987-10-28 Nec Corporation Semiconductor memory device
JPH0736437B2 (ja) * 1985-11-29 1995-04-19 株式会社日立製作所 半導体メモリの製造方法
JPH0815207B2 (ja) * 1986-02-04 1996-02-14 富士通株式会社 半導体記憶装置
JPH0789569B2 (ja) * 1986-03-26 1995-09-27 株式会社日立製作所 半導体集積回路装置及びその製造方法
JPS62259464A (ja) * 1986-05-02 1987-11-11 Toshiba Corp 半導体記憶装置の製造方法
JPS63237439A (ja) * 1987-03-26 1988-10-03 Fujitsu Ltd 半導体装置
JPS63299166A (ja) * 1987-05-29 1988-12-06 Fujitsu Ltd 半導体装置
JP2615076B2 (ja) * 1987-09-19 1997-05-28 株式会社日立製作所 半導体集積回路装置の製造方法
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
DE3802903A1 (de) * 1988-02-01 1989-08-10 Siemens Ag Einrichtung zur uebertragung von sprache
JP2631713B2 (ja) * 1988-08-25 1997-07-16 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0398569A2 (en) 1990-11-22
US5693970A (en) 1997-12-02
US5637522A (en) 1997-06-10
DE69031243T2 (de) 1997-12-04
KR940000307B1 (ko) 1994-01-14
DE69031243D1 (de) 1997-09-18
JPH02295163A (ja) 1990-12-06
JPH0824169B2 (ja) 1996-03-06
EP0398569B1 (en) 1997-08-13
EP0398569A3 (en) 1991-09-11

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