KR900019156A - 반도체장치의 제법 및 그 제법에 따른 반도체장치 - Google Patents
반도체장치의 제법 및 그 제법에 따른 반도체장치 Download PDFInfo
- Publication number
- KR900019156A KR900019156A KR1019900007522A KR900007522A KR900019156A KR 900019156 A KR900019156 A KR 900019156A KR 1019900007522 A KR1019900007522 A KR 1019900007522A KR 900007522 A KR900007522 A KR 900007522A KR 900019156 A KR900019156 A KR 900019156A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- spacer
- post
- phosphorus
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims 4
- 125000006850 spacer group Chemical group 0.000 claims 5
- 238000007254 oxidation reaction Methods 0.000 claims 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 3
- 229910052698 phosphorus Inorganic materials 0.000 claims 3
- 239000011574 phosphorus Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 반도체장치의 제1실시예의 공정단면도, 제2도는 본 발명에 따른 반도체장치의 제2실시예의 공정단면도
Claims (3)
- 반도체기판(107)상의 후산화막(105)상에 형성된 다결정스페이서(101)를 에칭하여 LDD구조를 갖춘 반도체 장치를 제조하는 제법에 있어서, 상기 다결정 스페이서(101)에 대해 인등의 불순물을 도우프하고, 또한 그 인을 열확산시키고 나서 상기 스페이서(101)을 에칭하는 것을 특징으로 하는 반도체장치의 제법
- 제1항에 있어서, 상기 반도체기판(107)의 후산화막이 2회의 다른 조건의 후산화처리에 의해 형성된 2중구조(105, 105')로 되어 있는 것을 특징으로 하는 반도체장치의 제법
- 반도체기판(107)상의 후산화막(105)상에 형성된 다결정 스페이서(101)에 대해 인등의 불순물을 도우프하고, 또한 그 인등의 불순물을 열확산시키고 나서 스페이서(101)을 에칭하여 제조된 LDD구조를 갖는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1128652A JPH0779101B2 (ja) | 1989-05-24 | 1989-05-24 | 半導体装置の製法 |
JP1-128652 | 1989-05-24 | ||
JP89-128652 | 1989-05-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900019156A true KR900019156A (ko) | 1990-12-24 |
KR930010975B1 KR930010975B1 (ko) | 1993-11-18 |
Family
ID=14990105
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900007522A KR930010975B1 (ko) | 1989-05-24 | 1990-05-24 | 반도체장치의 제법 및 그 제법에 따른 반도체장치 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0399529B1 (ko) |
JP (1) | JPH0779101B2 (ko) |
KR (1) | KR930010975B1 (ko) |
DE (1) | DE69032736T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100448087B1 (ko) * | 1997-06-30 | 2004-12-03 | 삼성전자주식회사 | 트랜지스터의스페이서제조방법 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06334135A (ja) * | 1993-05-20 | 1994-12-02 | Nec Corp | 相補型misトランジスタの製造方法 |
BE1007672A3 (nl) * | 1993-10-27 | 1995-09-12 | Philips Electronics Nv | Hoogfrequent halfgeleiderinrichting met beveiligingsinrichting. |
KR20060134190A (ko) * | 2004-03-31 | 2006-12-27 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | 측벽 스페이서 제조 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE8201678L (sv) * | 1982-03-17 | 1983-09-18 | Asea Ab | Sett att framstella foremal av mjukmagnetiskt material |
JPS59138379A (ja) * | 1983-01-27 | 1984-08-08 | Toshiba Corp | 半導体装置の製造方法 |
DE3530065C2 (de) * | 1984-08-22 | 1999-11-18 | Mitsubishi Electric Corp | Verfahren zur Herstellung eines Halbleiters |
JPS6194326A (ja) * | 1984-10-16 | 1986-05-13 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPH0740604B2 (ja) * | 1985-07-30 | 1995-05-01 | ソニー株式会社 | Mos半導体装置の製造方法 |
EP0218408A3 (en) * | 1985-09-25 | 1988-05-25 | Hewlett-Packard Company | Process for forming lightly-doped-grain (ldd) structure in integrated circuits |
-
1989
- 1989-05-24 JP JP1128652A patent/JPH0779101B2/ja not_active Expired - Lifetime
-
1990
- 1990-05-23 DE DE69032736T patent/DE69032736T2/de not_active Expired - Fee Related
- 1990-05-23 EP EP90109896A patent/EP0399529B1/en not_active Expired - Lifetime
- 1990-05-24 KR KR1019900007522A patent/KR930010975B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100448087B1 (ko) * | 1997-06-30 | 2004-12-03 | 삼성전자주식회사 | 트랜지스터의스페이서제조방법 |
Also Published As
Publication number | Publication date |
---|---|
DE69032736D1 (de) | 1998-12-10 |
KR930010975B1 (ko) | 1993-11-18 |
DE69032736T2 (de) | 1999-05-06 |
EP0399529A1 (en) | 1990-11-28 |
EP0399529B1 (en) | 1998-11-04 |
JPH02308532A (ja) | 1990-12-21 |
JPH0779101B2 (ja) | 1995-08-23 |
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J2X1 | Appeal (before the patent court) |
Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL |
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G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20091028 Year of fee payment: 17 |
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EXPY | Expiration of term |