KR890011246A - Memory circuit of teletex system - Google Patents

Memory circuit of teletex system Download PDF

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Publication number
KR890011246A
KR890011246A KR870013815A KR870013815A KR890011246A KR 890011246 A KR890011246 A KR 890011246A KR 870013815 A KR870013815 A KR 870013815A KR 870013815 A KR870013815 A KR 870013815A KR 890011246 A KR890011246 A KR 890011246A
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KR
South Korea
Prior art keywords
address
data
buffer
signal
operation mode
Prior art date
Application number
KR870013815A
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Korean (ko)
Inventor
오범석
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR870013815A priority Critical patent/KR890011246A/en
Publication of KR890011246A publication Critical patent/KR890011246A/en

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Abstract

내용 없음No content

Description

텔리텍스 시스템의 메모리 회로Memory circuit of teletex system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

제2도는 제1도에 대한 타이밍도.2 is a timing diagram relative to FIG.

Claims (1)

문서화일을 송수신하는 텔리텍시스템에 있어서, 버퍼(11)를 사용하여 데이터를 입출력하고 버퍼(12)를 사용하여 데이터를 저장 또는 독출하기 위한 제1어드레스와 주변기기의 제어를 위한 제3어드레스를 출력하며 버퍼(13)을 사용하여 데이터를 저장 및 둑출하기 위한 제어신호들을 출력하는 퍼스널 콤퓨터 확장 슬롯(10)과, 모뎀을 통해 송수신할 데이터를 버퍼(14)를 거쳐 저장 또는 독출하기 위해 제2어드레스와 제2리드 및 라이트 신호를 발생하는 랩비 제어수(30)와, 상기 랩비제어부(30)와, 퍼스널 컴퓨터 확장슬롯(10)의 데이터를 저장하기 위한 제2메모리 회로(400)와, 상기 랩비제어부(30)의 제2리드 및 라이트 신호와 상기 버퍼(13)을 통해 입력되는 퍼스널 콤퓨터 확장슬롯(10)의 제1리드 및 라이트 신호로 상기 제2메모리 회로(400)을 리드 또는 라이트상태로 인에이블시키기 위한 제3리드 및 라이트신호와 제2메모리회로(400)을 저장 독출하는 데이터의 입출력 방향을 제어하기 위한 데이터 방향 제어신호와 상기 랩비제어부(30)가 데이터를 저장 도는 독출하기원하는 제2요구신호와 어드레스 선택신호를 발생하는 메모리제어부(50)를 구비하여 상기 버퍼(12)를 통해 입력되는 퍼스널 콤퓨터 확장슬롯(10)의 제3어드레스를 디코딩하여 퍼스널 콤퓨터 확장슬롯(10)의 동작모드인가 랩비제어부 동작모드인가를 판단함으로 버퍼(11)를 제어하기 위한 동작모드제어신호를 발생하는 동작모드 제어수단과, 상기 제2메모리 제어부(50)의 어드레스 선택신호로 상기 랩비 제어부(30)의 제2어드레스나 상기 버퍼(12)를 통해 입력되는 제1어드레스를 선택 전송하는 어드레스 선택수단과, 상기 동작모드 제어수단의 동작모드제어신호와 상기 버퍼(13)을 통해 입력되는 제1요구신호 및 게이팅 펄스신호, 리플레쉬신호와 제2메모리 제어부(50)의 제2요구신호 및 데이터 방향제어신호로 상기 어드레스 선택수단에 의해 선택된 제1어드레스 또는 제2어드레스를 이용 상기 제2메모리회로(400)에 로우어드레스(Row Address)와 컬럼어드레스 (Colunm Address)를 인에블하여 저장 또는 독출할 데이어의 입출력 타임 및 방향을 제어하는 제2메모리 회로(400) 제어수단으로 이루어지는 제2메모리 제어회로 (410)로 구성함을 특징으로 하는 텔리텍스 시스템의 메모리 회로.In a Teletec system for transmitting and receiving a document file, a buffer 11 is used to input and output data, and a buffer 12 is used to output a first address for storing or reading data and a third address for controlling a peripheral device. And a personal computer expansion slot (10) for outputting control signals for storing and extracting data using the buffer (13), and a second address for storing or reading data to be transmitted / received through a modem through the buffer (14). And a lap ratio control number 30 for generating a second read and write signal, a lap ratio controller 30, a second memory circuit 400 for storing data of the personal computer expansion slot 10, and the lap ratio The second memory circuit 400 is read or written with the second lead and write signals of the controller 30 and the first lead and write signals of the personal computer expansion slot 10 input through the buffer 13. The data direction control signal for controlling the input / output direction of the third read and write signal for enabling the data and the data for storing and reading the second memory circuit 400 and the lap ratio controller 30 may store or read data. A memory controller 50 for generating a second request signal and an address selection signal to decode a third address of the personal computer expansion slot 10 input through the buffer 12 to decode a third address of the personal computer expansion slot 10; An operation mode control means for generating an operation mode control signal for controlling the buffer 11 by determining whether the operation mode or the lap ratio control unit is an operation mode, and the lap ratio control unit 30 by the address selection signal of the second memory controller 50; Address selection means for selecting and transmitting a second address or a first address input through the buffer 12, and an operation mode control signal of the operation mode control means. A first request signal, a gating pulse signal, a refresh signal, a second request signal of the second memory controller 50, and a data direction control signal inputted through the call and the buffer 13; The first and second addresses are used to control the input / output time and direction of a data to be stored or read by enabling a low address and a column address in the second memory circuit 400. 2. A memory circuit of a teletex system, characterized in that it comprises a second memory control circuit (410) consisting of control means (2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR870013815A 1987-12-04 1987-12-04 Memory circuit of teletex system KR890011246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870013815A KR890011246A (en) 1987-12-04 1987-12-04 Memory circuit of teletex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR870013815A KR890011246A (en) 1987-12-04 1987-12-04 Memory circuit of teletex system

Publications (1)

Publication Number Publication Date
KR890011246A true KR890011246A (en) 1989-08-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR870013815A KR890011246A (en) 1987-12-04 1987-12-04 Memory circuit of teletex system

Country Status (1)

Country Link
KR (1) KR890011246A (en)

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