KR20240051800A - Semiconductor system - Google Patents

Abstract

The semiconductor system outputs a command address and data, as well as a write clock and an inverted write clock for latching the data, through a channel, and outputs the write clock at a first set level during the pre-level period by reflecting the characteristic information of the channel. A controller that outputs the inverted light clock at a second setting level by reflecting the characteristic information of the channel, and periodically toggles and outputs the light clock and the inverted light clock during a toggle period, and the light clock and the inverted light clock It includes a semiconductor device that is synchronized with and latches and stores the data.

Description

Semiconductor system{SEMICONDUCTOR SYSTEM}

The present invention relates to a semiconductor system that latches and stores data in synchronization with a write clock.

Recently, as the operating speed of semiconductor systems increases, there is a trend to require high speed data transfer rates between semiconductor devices included in the semiconductor system. New technologies are applied to meet high-speed data transfer rates or high-bandwidth data for serial input and output between semiconductor devices.

For example, clock dividing techniques are used to input and output high-speed data. When the clock is divided, multi-phase clocks with different phases are generated, and data is parallelized or serialized using this to input and output data at high speed.

The present invention provides a semiconductor system that generates a light clock at a set level during a pre-level period and then periodically toggles during a toggle period to latch and store data.

For this purpose, the present invention outputs a command address and data, and a write clock and an inverted write clock for latching the data through a channel, and during the pre-level period, the light clock is adjusted to the first setting level by reflecting the characteristic information of the channel. output, output the inverted light clock at a second setting level by reflecting the characteristic information of the channel, and periodically toggle and output the light clock and the inverted light clock during a toggle period, and the light clock and the A semiconductor system including a semiconductor device that latches and stores the data in synchronization with an inverted write clock is provided.

In addition, the present invention outputs a command address and data and a write clock and an inverted write clock for latching the data through a channel, and first sets the write clock based on a code signal input through the channel during the pre-level period. level and outputs the inverted light clock at a second set level, a controller that outputs the light clock and the inverted light clock that are periodically toggled during the toggle period, and the light clock and the inverted light clock input during the toggle period. Provided is a semiconductor system including a semiconductor device that detects a write clock, outputs the code signal, and latches and stores the data in synchronization with the write clock and the inverted write clock.

According to the present invention, the ISI phenomenon of the channel can be reduced by generating a light clock at a set level in accordance with the characteristic information of the channel during the free level period and then periodically toggling the light clock during the toggle period.

In addition, according to the present invention, the light clock is generated at a set level according to the characteristic information of the channel during the free level period, and then the light clock is periodically toggled during the toggle period, thereby creating the effect of stably generating the light clock. .

In addition, according to the present invention, there is an effect of performing a stable data input/output operation by inputting and outputting data in synchronization with a light clock that is stably toggled after performing the pre-level adjustment operation.

1 is a block diagram showing the configuration of a semiconductor system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of a controller included in the semiconductor system shown in FIG. 1 according to an embodiment.
FIG. 3 is a circuit diagram showing the configuration of a level driving circuit included in the light clock generation circuit shown in FIG. 2 according to an embodiment.
FIG. 4 is a circuit diagram showing the configuration of a transmission circuit included in the light clock generation circuit shown in FIG. 2 according to an embodiment.
FIG. 5 is a block diagram showing the configuration of a semiconductor device included in the semiconductor system shown in FIG. 1 according to an embodiment.
FIG. 6 is a diagram illustrating an operation for generating a write clock and an inverted write clock in a semiconductor system according to various embodiments.
Figure 7 is a block diagram showing the configuration of a semiconductor system according to another embodiment of the present invention.
FIG. 8 is a block diagram showing the configuration of a controller included in the semiconductor system shown in FIG. 7 according to an embodiment.
FIG. 9 is a block diagram showing the configuration of a semiconductor device included in the semiconductor system shown in FIG. 7 according to an embodiment.
FIG. 10 is a block diagram showing the configuration of a sensing circuit included in the semiconductor device shown in FIG. 9 according to an embodiment.
FIG. 11 is a diagram for explaining the operation of the sensing circuit shown in FIG. 10.
FIG. 12 is a diagram illustrating the configuration of an electronic system to which the semiconductor system shown in FIGS. 1 to 11 is applied according to an embodiment.

The term "preset" means that when a parameter is used in a process or algorithm, the value of the parameter is predetermined. Depending on the embodiment, the value of the parameter may be set when a process or algorithm starts or may be set during a section in which the process or algorithm is performed.

Terms such as “first” and “second” used to distinguish various components are not limited by the components. For example, a first component may be named a second component, and conversely, the second component may be named a first component.

When one component is said to be “connected” or “connected” to another component, it should be understood that it may be connected directly or may be connected through another component in the middle. On the other hand, the descriptions “directly connected” and “directly connected” should be understood to mean that one component is directly connected to another component without an intervening component.

“Logic high level” and “logic low level” are used to describe logic levels of signals. Signals with a “logic high level” are distinguished from signals with a “logic low level.” For example, when a signal with a first voltage corresponds to a “logic high level,” a signal with a second voltage may correspond to a “logic low level.” According to one embodiment, the “logic high level” may be set to a voltage greater than the “logic low level.” Meanwhile, the logic levels of signals may be set to different logic levels or opposite logic levels depending on the embodiment. For example, a signal having a logic high level may be set to have a logic low level depending on the embodiment, and a signal having a logic low level may be set to have a logic high level depending on the embodiment.

Hereinafter, the present invention will be described in more detail through examples. These examples are only for illustrating the present invention, and the scope of rights protection of the present invention is not limited by these examples.

As shown in FIG. 1, the semiconductor system 1 according to an embodiment of the present invention may include a controller 10 and a semiconductor device 20. The controller 10 and the semiconductor device 20 may be connected through a channel (CH1).

The channel CH1 may include a first pad 11, a second pad 12, a third pad 13, a fourth pad 14, and a fifth pad 15 connected to the controller 10. there is. The channel CH1 may include a sixth pad 21, a seventh pad 22, an eighth pad 23, a ninth pad 24, and a tenth pad 25 connected to the semiconductor device 20. You can. The channel CH1 is a first transmission line (L11) connected between the first pad 11 and the sixth pad 21, and a second transmission line connected between the second pad 12 and the seventh pad 22. line L12, a third transmission line L13 connected between the third pad 13 and the eighth pad 23, and a fourth transmission line connected between the fourth pad 14 and the ninth pad 24. It may include a line L14 and a fifth transmission line L15 connected between the fifth pad 15 and the tenth pad 25.

The controller 10 may output a command address (CA) to the semiconductor device 20 through the first transmission line L11 connected between the first pad 11 and the sixth pad 21. The controller 10 may output the clock CLK to the semiconductor device 20 through the second transmission line L12 connected between the second pad 12 and the seventh pad 22. The controller 10 may output a write clock (WCK) to the semiconductor device 20 through the third transmission line L13 connected between the third pad 13 and the eighth pad 23. The controller 10 may output the inverted write clock (WCKB) to the semiconductor device 20 through the fourth transmission line (L14) connected between the fourth pad 14 and the ninth pad 24. The controller 10 may output data (DATA) to the semiconductor device 20 through the fifth transmission line L15 connected between the fifth pad 15 and the tenth pad 25. The command address (CA) may be set to a plurality of bits including commands and addresses for controlling the operation of the semiconductor device 20. The clock CLK may be set as a signal that is toggled periodically to synchronize the controller 10 and the semiconductor device 20. Write clock (WCK) and reverse write clock (WCKB) can be set as signals that are toggled periodically to latch data (DATA). Data (DATA) can be set as general data including a number of bits.

The controller 10 may include a light clock control circuit 120 and a light clock generation circuit 130.

The light clock control circuit 120 may generate an enable signal (PREN in FIG. 2) that occurs during the pre-level section. The write clock control circuit 120 may generate a pre-inverted write clock (PWCK in FIG. 2) and a pre-inverted write clock (PWCKB in FIG. 2) during the pre-level section and the toggle section. The light clock control circuit 120 may generate first to fourth code signals (CODE<1:4> in FIG. 2) including characteristic information of the channel CH1. The characteristic information of the channel (CH1) includes the PVT change amount and transmission speed for the first to tenth pads (11 to 15, 21 to 25) and the first to fifth transmission lines (L11 to L15) included in the channel (CH1). may include. PVT change can refer to the change in characteristics according to process, voltage, and temperature. The transmission speed may refer to the transmission speed of signals input and output from the first to tenth pads (11 to 15, 21 to 25) and the first to fifth transmission lines (L11 to L15).

The light clock generation circuit 130 generates a light clock having a first set level based on the enable signal (PREN in FIG. 2) and the first to fourth code signals (CODE<1:4> in FIG. 2) during the pre-level section. (WCK) and an inverted write clock (WCKB) having a second set level can be output through the channel (CH1). The light clock generation circuit 130 may output a light clock (WCK) and an inverted write clock (WCKB) that are periodically toggled during the toggle period through a channel (CH1). The first set level may be set to a voltage level higher than the ground voltage (VSS in FIG. 3), and the second set level may be set to a voltage level lower than the power supply voltage (VDD in FIG. 3). Light clock (WCK) and reverse light clock (WCKB) may be generated with opposite phases to each other during the toggle period.

The controller 10 generates a light clock (WCK) with a first set level during the pre-level period based on the first to fourth code signals (CODE<1:4> in FIG. 2) including characteristic information of the channel (CH1). A reverse write clock (WCKB) having a second set level can be output to the semiconductor device 20. The controller 30 inverts the light clock (WCK) that is toggled periodically during the toggle period based on the first to fourth code signals (CODE<1:4> in FIG. 2) containing characteristic information of the channel (CH1). A light clock (WCKB) can be output to the semiconductor device 20.

The semiconductor device 20 may include a write clock buffer circuit 330.

The light clock buffer circuit 330 can receive a light clock (WCK) and an inverted write clock (WCKB). The write clock buffer circuit 330 can buffer the write clock (WCK) and the inverted write clock (WCKB) input during the toggle period and transfer them to a circuit for latching data (DATA).

The semiconductor device 20 can perform a write operation based on a command address (CA) that is input in synchronization with the clock (CLK). The semiconductor device 20 can latch data (DATA) in synchronization with the write clock (WCK) and the reverse write clock (WCKB) during the toggle period in the write operation. The semiconductor device 20 can store latched data (DATA) during a write operation.

FIG. 2 is a block diagram showing the configuration of the controller 10 included in the semiconductor system 1 according to an embodiment. The controller 10 may include an operation control circuit 110, a write clock control circuit 120, a write clock generation circuit 130, and a data generation circuit 140.

The operation control circuit 110 may be connected to the first pad 11 and the second pad 12. The operation control circuit 110 may output the first to Lth command addresses (CA<1:L>) for performing a write operation through the first pad 11. The control circuit 110 may output a periodically toggled clock (CLK) through the second pad 12. The first to Lth command addresses (CA<1:L>) may include “L” bits, and the bit number “L” of the first to Lth command addresses (CA<1:L>) is a positive integer. It can be set to .

The light clock control circuit 120 may generate an enable signal (PREN) that occurs at a logic high level during the pre-level section. The write clock control circuit 120 includes a pre-write clock (PWCK) generated at the ground voltage (VSS in FIG. 3) level and a pre-reverse write clock (PWCKB) generated at the power voltage (VDD in FIG. 3) level during the pre-level section. can be created. The write clock control circuit 120 may generate a preset write clock (PWCK) and a preset write clock (PWCKB) that are toggled periodically during the toggle period. The pre-write clock (PWCK) and pre-reverse write clock (PWCKB) can be toggled to a voltage level between the power supply voltage (VDD in FIG. 3) and the ground voltage (VSS in FIG. 3) during the toggle period. The light clock control circuit 120 may generate first to fourth code signals CODE<1:4> including characteristic information of the channel CH1. The characteristic information of the channel (CH1) includes the PVT change amount and transmission speed for the first to tenth pads (11 to 15, 21 to 25) and the first to fifth transmission lines (L11 to L15) included in the channel (CH1). may include.

The light clock generation circuit 130 may include a level driving circuit 131 and a transmission circuit 132.

The level driving circuit 131 may be connected to the third pad 13 and the fourth pad 14. The level driving circuit 131 may drive the third pad 13 based on the enable signal PREN during the pre-level period. The level driving circuit 131 may drive the fourth pad 14 based on the enable signal PREN during the pre-level period. The driving force that drives the third pad 13 and the fourth pad 14 in the level driving circuit 131 will be described in detail with reference to FIG. 3 described later.

The transmission circuit 132 may be connected to the third pad 13 and the fourth pad 14. The transmission circuit 132 drives the third pad 13 based on the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the pre-level section. can do. The transmission circuit 132 drives the fourth pad 14 based on the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the pre-level section. can do. The transmission circuit 132 drives the third pad 13 based on the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the toggle period. You can. The transmission circuit 132 drives the fourth pad 14 based on the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the toggle period. You can. The driving force that drives the third pad 13 and the fourth pad 14 in the transmission circuit 132 will be described in detail with reference to FIG. 4 described later.

The light clock generation circuit 130 may be connected to the third pad 13 and the fourth pad 14. The write clock generation circuit 130 generates an enable signal (PREN), a pre-write clock (PWCK), a pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the pre-level section. Based on this, a light clock (WCK) having a first set level can be output through the third pad 13. The write clock generation circuit 130 generates an enable signal (PREN), a pre-write clock (PWCK), a pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the pre-level section. Based on this, an inverted write clock (WCKB) having a second set level can be output through the fourth pad 14. The light clock generation circuit 130 generates a light clock that is periodically toggled based on the preset write clock (PWCK), preset write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the toggle period. (WCK) can be output through the third pad 13. The light clock generation circuit 130 is a reverse light that is periodically toggled based on the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and first to fourth code signals (CODE<1:4>) during the toggle period. The clock (WCKB) can be output through the fourth pad 14.

FIG. 3 is a circuit diagram showing the configuration of the level driving circuit 131 included in the light clock generation circuit 130 according to one embodiment. The level driving circuit 131 may include a first driving circuit 210 and a second driving circuit 220.

The first driving circuit 210 may be connected to the third pad 13. The first driving circuit 210 is implemented with an NMOS transistor (210_1) connected between the power supply voltage (VDD) and the node (nd210) and an NMOS transistor (210_2) connected between the node (nd210) and the ground voltage (VSS). You can. Node nd210 may be connected to the third pad 13. The NMOS transistor 210_1 is turned on when the enable signal PREN is at a logic high level and receives charge from the power supply voltage VDD to the node nd210 to drive the third pad 13 with the first pull-up driving force. You can. The NMOS transistor 210_2 may be turned off by the ground voltage (VSS).

The second driving circuit 220 may be connected to the fourth pad 14. The second driving circuit 220 is implemented with an NMOS transistor (220_1) connected between the power supply voltage (VDD) and the node (nd220) and an NMOS transistor (220_2) connected between the node (nd220) and the ground voltage (VSS). You can. Node nd220 may be connected to the fourth pad 14. The NMOS transistor 220_1 may be turned off by the ground voltage (VSS). The NMOS transistor 220_2 is turned on when the enable signal PREN is at a logic high level and discharges the charge of the node nd210 to the ground voltage VSS to drive the fourth pad 14 with the first pull-down driving force. You can.

FIG. 4 is a circuit diagram showing the configuration of the transmission circuit 132 included in the light clock generation circuit 130 according to one embodiment. The transmission circuit 132 may include a light clock driving circuit 230 and an inverted light clock driving circuit 240.

The light clock driving circuit 230 may be connected to the third pad 13. The light clock driving circuit 230 may include a first driver 231, a second driver 232, a third driver 233, and a fourth driver 234.

The first driver 231 is connected in series with the NMOS transistor 231_1 and NMOS transistor 231_2 between the power supply voltage (VDD) and the node (nd230) and between the node (nd230) and the ground voltage (VSS). It can be implemented with the NMOS transistor 231_3 and NMOS transistor 231_4. Node nd230 may be connected to the third pad 13. The NMOS transistor 231_1 may be turned on when the first code signal CODE<1> occurs at a logic high level. The NMOS transistor 231_2 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 231_1 and NMOS transistor 231_2 are turned on, charge is supplied to the node nd230 from the power supply voltage VDD to drive the third pad 13 with the second pull-up driving force. The NMOS transistor 231_3 may be turned on when the first code signal CODE<1> occurs at a logic high level. The NMOS transistor 231_4 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 231_3 and NMOS transistor 231_4 are turned on, the charge of the node nd230 is discharged to the ground voltage VSS to drive the third pad 13 with the second pull-down driving force.

The second driver 232 is connected in series with the NMOS transistor 232_1 and NMOS transistor 232_2 between the power supply voltage (VDD) and the node (nd230) and between the node (nd230) and the ground voltage (VSS). It can be implemented with the NMOS transistor 232_3 and NMOS transistor 232_4. The NMOS transistor 232_1 may be turned on when the second code signal CODE<2> occurs at a logic high level. The NMOS transistor 232_2 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 232_1 and NMOS transistor 232_2 are turned on, charge is supplied to the node nd230 from the power supply voltage VDD to drive the third pad 13 with the third pull-up driving force. The NMOS transistor 232_3 may be turned on when the second code signal CODE<2> occurs at a logic high level. The NMOS transistor 232_4 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 232_3 and NMOS transistor 232_4 are turned on, the charge of the node nd230 is discharged to the ground voltage VSS to drive the third pad 13 with the third pull-down driving force.

The third driver 233 is connected in series with the NMOS transistor 233_1 and NMOS transistor 233_2 between the power supply voltage (VDD) and the node (nd230) and between the node (nd230) and the ground voltage (VSS). It can be implemented with the NMOS transistor 233_3 and NMOS transistor 233_4. The NMOS transistor 233_1 may be turned on when the third code signal CODE<3> occurs at a logic high level. The NMOS transistor 233_2 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 233_1 and NMOS transistor 233_2 are turned on, charge is supplied to the node nd230 from the power supply voltage VDD to drive the third pad 13 with the fourth pull-up driving force. The NMOS transistor 233_3 may be turned on when the third code signal CODE<3> occurs at a logic high level. The NMOS transistor 233_4 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 233_3 and NMOS transistor 233_4 are turned on, the charge of the node nd230 is discharged to the ground voltage VSS, thereby driving the third pad 13 with the fourth pull-down driving force.

The fourth driver 234 is connected in series with the NMOS transistor 234_1 and NMOS transistor 234_2 between the power supply voltage (VDD) and the node (nd230) and between the node (nd230) and the ground voltage (VSS). It can be implemented with the NMOS transistor 234_3 and NMOS transistor 234_4. The NMOS transistor 234_1 may be turned on when the fourth code signal CODE<4> occurs at a logic high level. The NMOS transistor 234_2 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 234_1 and NMOS transistor 234_2 are turned on, charge is supplied to the node nd230 from the power supply voltage VDD to drive the third pad 13 with the fifth pull-up driving force. The NMOS transistor 234_3 may be turned on when the fourth code signal CODE<4> occurs at a logic high level. The NMOS transistor 234_4 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 234_3 and NMOS transistor 234_4 are turned on, the charge of the node nd230 is discharged to the ground voltage VSS, thereby driving the third pad 13 with the fifth pull-down driving force.

The inverted light clock driving circuit 240 may be connected to the fourth pad 14. The inverted light clock driving circuit 240 may include a fifth driver 241, a sixth driver 242, a seventh driver 243, and an eighth driver 244.

The fifth driver 241 has an NMOS transistor (241_1) and an NMOS transistor (241_2) connected in series between the power supply voltage (VDD) and the node (nd240) and between the node (nd240) and the ground voltage (VSS). It can be implemented with the NMOS transistor 241_3 and NMOS transistor 241_4. Node nd240 may be connected to the fourth pad 14. The NMOS transistor 241_1 may be turned on when the first code signal CODE<1> occurs at a logic high level. The NMOS transistor 241_2 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 241_1 and NMOS transistor 241_2 are turned on, charge is supplied to the node nd240 from the power supply voltage VDD to drive the fourth pad 14 with the sixth pull-up driving force. The NMOS transistor 241_3 may be turned on when the first code signal CODE<1> occurs at a logic high level. The NMOS transistor 241_4 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 241_3 and NMOS transistor 241_4 are turned on, the charge of the node nd240 is discharged to the ground voltage VSS, thereby driving the fourth pad 14 with the sixth pull-down driving force.

The sixth driver 242 is connected in series with the NMOS transistor 242_1 and NMOS transistor 242_2 between the power supply voltage (VDD) and the node (nd240) and between the node (nd240) and the ground voltage (VSS). It can be implemented with the NMOS transistor 242_3 and NMOS transistor 242_4. The NMOS transistor 242_1 may be turned on when the second code signal CODE<2> occurs at a logic high level. The NMOS transistor 242_2 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 242_1 and NMOS transistor 242_2 are turned on, charge is supplied to the node nd240 from the power supply voltage VDD to drive the fourth pad 14 with the seventh pull-up driving force. The NMOS transistor 242_3 may be turned on when the second code signal CODE<2> occurs at a logic high level. The NMOS transistor 242_4 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 242_3 and NMOS transistor 242_4 are turned on, the charge of the node nd240 is discharged to the ground voltage VSS, thereby driving the fourth pad 14 with the seventh pull-down driving force.

The seventh driver 243 is connected in series with the NMOS transistor 243_1 and NMOS transistor 243_2 between the power supply voltage (VDD) and the node (nd240) and between the node (nd240) and the ground voltage (VSS). It can be implemented with the NMOS transistor 243_3 and NMOS transistor 243_4. The NMOS transistor 243_1 may be turned on when the third code signal CODE<3> occurs at a logic high level. The NMOS transistor 243_2 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 243_1 and NMOS transistor 243_2 are turned on, charge is supplied to the node nd240 from the power supply voltage VDD to drive the fourth pad 14 with the eighth pull-up driving force. The NMOS transistor 243_3 may be turned on when the third code signal CODE<3> occurs at a logic high level. The NMOS transistor 243_4 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 243_3 and NMOS transistor 243_4 are turned on, the charge of the node nd240 is discharged to the ground voltage VSS, thereby driving the fourth pad 14 with the eighth pull-down driving force.

The eighth driver 244 is connected in series with the NMOS transistor 244_1 and NMOS transistor 244_2 between the power supply voltage (VDD) and the node (nd240) and between the node (nd240) and the ground voltage (VSS). It can be implemented with the NMOS transistor 244_3 and NMOS transistor 244_4. The NMOS transistor 244_1 may be turned on when the fourth code signal CODE<4> occurs at a logic high level. The NMOS transistor 244_2 may be turned on when the inverting pre-write clock (PWCKB) occurs at a logic high level. When the NMOS transistor 244_1 and NMOS transistor 244_2 are turned on, charge is supplied to the node nd240 from the power supply voltage VDD to drive the fourth pad 14 with the ninth pull-up driving force. The NMOS transistor 244_3 may be turned on when the fourth code signal CODE<4> occurs at a logic high level. The NMOS transistor 244_4 may be turned on when the pre-write clock (PWCK) occurs at a logic high level. When the NMOS transistor 244_3 and NMOS transistor 244_4 are turned on, the charge of the node nd240 is discharged to the ground voltage VSS to drive the fourth pad 14 with the ninth pull-down driving force.

Meanwhile, the level driving circuit 131 and the transmission circuit 132 shown in FIG. 3 are implemented as separate circuits, but in another embodiment of the present invention, the level driving circuit 131 is included in the transmission circuit 132. It can be implemented as much as possible. For example, when the NMOS transistors included in the first to fourth drivers 231 to 234 and connected in series between the node nd230 and the ground voltage VSS drive the third pad 13 with a pull-down driving force. Any one of the NMOS transistors connected in series between the power supply voltage (VDD) and the node (nd230) may be turned on to drive the third pad 13 with a pull-up driving force. In addition, when the NMOS transistors included in the fifth to eighth drivers 241 to 244 and connected in series between the power supply voltage (VDD) and the node (nd240) drive the fourth pad 14 with the pull-up driving power, the node ( One of the NMOS transistors between nd240) and the ground voltage (VSS) may be turned on to drive the fourth pad 14 with a pull-up-down driving force.

FIG. 5 is a block diagram showing the configuration of the semiconductor device 20 included in the semiconductor system 1 according to an embodiment. The semiconductor device 20 may include a command generation circuit 310, an address generation circuit 320, a write clock buffer circuit 330, a frequency divider circuit 340, a data processing circuit 350, and a core circuit 360. You can.

The command generation circuit 310 may be connected to the sixth pad 21 and the seventh pad 22. The command generation circuit 310 is synchronized with the clock (CLK) input through the seventh pad 22 and generates the first to Lth command addresses (CA<1:L>) input through the sixth pad 21. Based on this, an internal command (ICMD) can be created. The command generation circuit 310 generates an internal command (ICMD) when the first to Lth command addresses (CA<1:L>) input in synchronization with the clock (CLK) are a logic level combination for performing a write operation. can do. The command generation circuit 310 is implemented to generate an internal command (ICMD) for performing a write operation, but may be implemented to generate a plurality of internal commands for performing various operations depending on the embodiment.

The address generation circuit 320 may be connected to the sixth pad 21 and the seventh pad 22. The address generation circuit 320 is synchronized with the clock (CLK) input through the seventh pad 22 and generates the first to Lth command addresses (CA<1:L>) input through the sixth pad 21. Based on this, the first to M internal addresses (IADD<1:M>) can be generated. The address generation circuit 320 decodes the first to Lth command addresses (CA<1:L>) that are input in synchronization with the clock (CLK) and generates selectively enabled first to Mth internal addresses (IADD<1). :M>) can be created. The first to M internal addresses (IADD<1:M>) may include “M” bits, and the number of bits “M” of the first to M internal addresses (IADD<1:M>) is a positive integer. It can be set to .

The light clock buffer circuit 330 may be connected to the eighth pad 23 and the ninth pad 24. The light clock buffer circuit 330 may generate an input write clock (I_WCK) by buffering the light clock (WCK) input through the eighth pad 23 during the toggle period. The write clock buffer circuit 330 may generate an inverted input write clock (I_WCKB) by buffering the inverted write clock (WCKB) input through the ninth pad 24 during the toggle period.

The frequency divider circuit 340 divides the frequencies of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) into the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and A fourth internal clock (QBCLK) can be generated. The frequency divider circuit 340 has a frequency of 1/2 the input write clock (I_WCK) and the inverted input write clock (I_WCKB) and sequentially generates a first internal clock (ICLK), a second internal clock (QCLK), and a second internal clock (ICLK). 3 internal clock (IBCLK) and fourth internal clock (QBCLK) can be generated. The phases of the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and the fourth internal clock (QBCLK) may each be generated with different phases.

The data processing circuit 350 may be connected to the tenth pad 25. The data processing circuit 350 is synchronized with the first internal clock (ICLK), second internal clock (QCLK), third internal clock (IBCLK), and fourth internal clock (QBCLK) and inputs through the tenth pad (25). The first to Nth internal data (ID<1:N>) can be generated based on the first to Nth data (DATA<1:N>). The data processing circuit 350 is synchronized with the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and the fourth internal clock (QBCLK) and inputs the first to Nth signals in series. The bits of the data (DATA<1:N>) can be latched and aligned to generate first to Nth internal data (ID<1:N>) generated in parallel. For example, the data processing circuit 350 latches the first data (DATA<1>) input to the rising edge of the first internal clock (ICLK), and latches the first data (DATA<1>) input to the rising edge of the second internal clock (QCLK). Latch the second data (DATA<2>), latch the third data (DATA<3>) input to the rising edge of the third internal clock (IBCLK), and latch the third data (DATA<3>) input to the rising edge of the fourth internal clock (QBCLK). The fourth input data (DATA<4>) can be latched. The data processing circuit 350 sorts the latched first to fourth data (DATA<1:4>) to generate first to fourth internal data (ID<1:4>) generated in parallel at the same time. can do.

The core circuit 360 may be implemented as a general memory circuit including a plurality of memory cells (not shown). The core circuit 360 connects the first to M memory cells (not shown) selected from a plurality of memory cells (not shown) based on the internal command (ICMD) and the first to M internal addresses (IADD<1:M>). The Nth internal data (ID<1:N>) can be saved. The core circuit 360 is implemented to perform a write operation, but depending on the embodiment, it may be implemented to perform an active operation, a read operation, a precharge operation, and a refresh operation.

The operation of generating a write clock and an inverted write clock in a semiconductor system according to various embodiments will be described with reference to FIG. 6 as follows.

First, the normal operation of generating a write clock (WCK) and an inverted write clock (WCKB) in a semiconductor system is explained as follows.

In the first section (P1), the controller of the semiconductor system fixes the write clock (WCK) to the ground voltage (VSS) level and outputs the inverted write clock (WCKB) by fixing it to the power supply voltage (VDD) level. The first section (P1) is set as a section before data for performing a write operation is output from the controller.

In the second section (P2), the controller of the semiconductor system outputs a write clock (WCK) and an inverted write clock (WCKB) that are periodically toggled from the power supply voltage (VDD) level to the ground voltage (VSS) level. In the second section (P2), the semiconductor device of the semiconductor system latches, sorts, and stores data output from the controller in synchronization with the periodically toggled write clock (WCK) and inverted write clock (WCKB). The second section (P2) is set as a light operation section that stores data output from the controller.

When performing the normal operation of generating a light clock in a semiconductor system, the ISI (Inter Symbol Interface) phenomenon of the channel occurs due to reflection and distortion of the channel at the starting point of the second section (P2). This may cause defects in the data latch operation.

Next, the frequency adjustment operation (Half Rate) that generates the write clock (WCK) and reverse write clock (WCKB) in the semiconductor system is explained as follows.

In the first section (P1), the controller of the semiconductor system operates the light clock (WCK) and reverse light with a frequency of 1/2 times (Half Rate) the frequency at which the light clock (WCK) and reverse light clock (WCKB) toggle. Outputs clock (WCKB). The first section (P1) is set as a section before data for performing a write operation is output from the controller.

In the second section (P2), the controller of the semiconductor system outputs a write clock (WCK) and an inverted write clock (WCKB) that are periodically toggled from the power supply voltage (VDD) level to the ground voltage (VSS) level. In the second section (P2), the semiconductor device of the semiconductor system latches, sorts, and stores data output from the controller in synchronization with the periodically toggled write clock (WCK) and inverted write clock (WCKB). The second section (P2) is set as a light operation section that stores data output from the controller.

When a semiconductor system performs a frequency adjustment operation (Half Rate) that generates a write clock (WCK) and an inverted write clock (WCKB), the ISI (Inter Symbol Interface) phenomenon of the channel is reduced compared to normal operation (Normal operation), but it is still the second At the starting point of the section P2, the ISI (Inter Symbol Interface) phenomenon of the channel may occur due to channel reflection and distortion, which may cause defects in the data latch operation.

Next, the pre-level adjustment operation (Pre Level) for generating the write clock (WCK) and the inverted write clock (WCKB) in the semiconductor system 1 according to an embodiment of the present invention will be described as follows.

In the first section (P1), the controller of the semiconductor system reflects the characteristics of the channel and generates the voltage level of the write clock (WCK) as a first set level that is higher (+△) than the ground voltage (VSS) level and inverts the write clock. The voltage level of (WCKB) is generated and output as a second set level that is lower (-△) than the power supply voltage (VDD) level. The first section (P1) is before the data for performing the write operation is output from the controller. The section in which the write clock (WCK) is generated at the first setting level and the reverse write clock (WCKB) is generated at the second setting level in the first section (P1) is set as the free level section. The voltage level of the first set level, which is increased (+△) compared to the ground voltage (VSS) level, and the voltage level of the second set level, which is decreased (-△), is set to have various voltage levels depending on the embodiment. In addition, the voltage level of increase (+△) and the voltage level of decrease (-△ may be different voltage levels. For example, when the voltage level of increase (+△) is +20mV, the voltage level of decrease (-△ )'s voltage level may be -10mV.

Meanwhile, in the pre-level control operation (Pre Level), the voltage level of the light clock (WCK) is generated as a first set level that is increased (+△) higher than the ground voltage (VSS) level, and the voltage level of the inverted light clock (WCKB) is increased. It is implemented to generate and output a second set level that is lower (-△) than the power supply voltage (VDD) level, but depending on the embodiment, the voltage level of the write clock (WCK) is lower (-△) than the power supply voltage (VDD) level. It can be implemented to generate and output a first set level, and generate and output a second set level that increases the voltage level of the inverted write clock (WCKB) to the ground voltage (VSS) level (+△). In addition, the pre-level adjustment operation In (Pre Level), the voltage level of the write clock (WCK) is generated as the first set level with a voltage level close to the ground voltage (VSS), and the voltage level of the inverted write clock (WCKB) is generated as a first set level with a voltage level close to the power supply voltage (VDD). It may be implemented to generate a second set level having a voltage level.

In the second section (P2), the controller of the semiconductor system outputs a write clock (WCK) and an inverted write clock (WCKB) that are periodically toggled from the power supply voltage (VDD) level to the ground voltage (VSS) level. In the second section (P2), the semiconductor device of the semiconductor system latches, sorts, and stores data output from the controller in synchronization with the periodically toggled write clock (WCK) and inverted write clock (WCKB). The second section (P2) is set as a light operation section that stores data output from the controller. The second section (P2) is set as a toggle section in which the write clock (WCK) and the reverse write clock (WCKB) toggle periodically.

When performing a pre-level adjustment operation (Pre Level) to generate a light clock in the semiconductor system (1), reflection and distortion of the channel are prevented at the starting point of the second section (P2), and the ISI (ISI) of the channel is prevented. Inter Symbol Interface) phenomenon can be reduced.

The semiconductor system 1 of the present invention is implemented to perform a pre-level adjustment operation (Pre Level) of the light clock (WCK), but depending on the embodiment, a clock signal ( It can be implemented to perform a pre-level adjustment operation (Pre Level) of the clock.

The semiconductor system 1 according to an embodiment of the present invention generates a write clock (WCK) and a reverse write clock (WCKB) at a set level in accordance with the characteristic information of the channel during the pre-level period, and then periodically during the toggle period. The Inter Symbol Interface (ISI) of the channel can be reduced by generating a toggling write clock (WCK) and an inverted write clock (WCKB). The semiconductor system (1) generates the light clock (WCK) and inverted light clock (WCKB) at a set level according to the characteristic information of the channel during the pre-level section, and then periodically toggles the light clock (WCK) and inverted light clock (WCKB) during the toggle section. By generating the light clock (WCKB), the light clock (WCK) and reverse write clock (WCKB) can be reliably generated. The semiconductor system 1 can perform stable data input/output operations by inputting and outputting data in synchronization with the stably toggled write clock (WCK) and inverted write clock (WCKB) after performing the pre-level control operation. .

Figure 7 is a block diagram showing the configuration of a semiconductor system 2 according to another embodiment of the present invention. As shown in FIG. 7, the semiconductor system 2 according to another embodiment of the present invention may include a controller 30 and a semiconductor device 40. The controller 30 and the semiconductor device 40 may be connected through a channel (CH2).

The channel (CH2) includes the first pad 31, the second pad 32, the third pad 33, the fourth pad 34, the fifth pad 35, and the sixth pad connected to the controller 30. (36) may be included. The channel CH2 includes the seventh pad 41, eighth pad 42, ninth pad 43, 10th pad 44, 11th pad 45, and 12th pad connected to the semiconductor device 40. It may include a pad 46. The channel (CH2) is a first transmission line (L31) connected between the first pad 31 and the seventh pad 41, and a second transmission line connected between the second pad 32 and the eighth pad 42. Line L32, a third transmission line L33 connected between the third pad 33 and the ninth pad 43, and a fourth transmission line connected between the fourth pad 34 and the tenth pad 44. Line L34, the fifth transmission line L35 connected between the fifth pad 35 and the eleventh pad 45, and the sixth transmission line connected between the sixth pad 36 and the twelfth pad 46. It may include line (L36).

The controller 30 may output a command address (CA) to the semiconductor device 40 through the first transmission line L31 connected between the first pad 31 and the seventh pad 41. The controller 30 may output the clock CLK to the semiconductor device 40 through the second transmission line L32 connected between the second pad 32 and the eighth pad 42. The controller 30 may output a write clock (WCK) to the semiconductor device 40 through the third transmission line (L33) connected between the third pad 33 and the ninth pad 43. The controller 30 may output the inverted write clock (WCKB) to the semiconductor device 40 through the fourth transmission line (L34) connected between the fourth pad 44 and the tenth pad 44. The controller 30 may output data (DATA) to the semiconductor device 40 through the fifth transmission line L35 connected between the fifth pad 45 and the eleventh pad 45. The controller 30 may receive the code signal CODE from the semiconductor device 40 through the sixth transmission line L36 connected between the sixth pad 46 and the twelfth pad 46.

The command address (CA) may be set to a plurality of bits including commands and addresses for controlling the operation of the semiconductor device 40. The clock CLK may be set as a signal that is toggled periodically to synchronize the controller 30 and the semiconductor device 40. Write clock (WCK) and reverse write clock (WCKB) can be set as signals that are toggled periodically to latch data (DATA). Data (DATA) can be set as general data including a number of bits. The code signal (CODE) can be set as a signal containing characteristic information of the channel (CH2) by detecting the number of toggling times of the write clock (WCK) and the inverted write clock (WCKB).

The controller 30 may include a light clock generation circuit 430.

The light clock generation circuit 430 generates a light clock (WCK) with a first set level and an inverted light clock with a second set level based on the enable signal (PREN in FIG. 8) and the code signal (CODE) during the pre-level section. (WCKB) can be output through channel (CH2). The light clock generation circuit 430 can output a light clock (WCK) and an inverted write clock (WCKB) that are periodically toggled during the toggle period through a channel (CH2). The first set level may be set to a voltage level higher than the ground voltage (VSS in FIG. 3), and the second set level may be set to a voltage level lower than the power supply voltage (VDD in FIG. 3). Light clock (WCK) and reverse light clock (WCKB) may be generated with opposite phases to each other during the toggle period.

The controller 30 generates a write clock (WCK) with a first set level and an inverted write clock (WCKB) with a second set level during the pre-level period based on the code signal (CODE) including the characteristic information of the channel (CH2). can be output to the semiconductor device 40. The controller 30 outputs a write clock (WCK) and an inverted write clock (WCKB) that are periodically toggled during the toggle period based on the code signal (CODE) containing the characteristic information of the channel (CH2) to the semiconductor device 40. can do.

The semiconductor device 40 may include a write clock buffer circuit 530 and a detection circuit 540.

The write clock buffer circuit 530 can receive a write clock (WCK) and an inverted write clock (WCKB). The write clock buffer circuit 530 can buffer the write clock (WCK) and the inverted write clock (WCKB) input during the toggle period and transfer them to a circuit for latching data (DATA).

The detection circuit 540 generates a code signal (CODE) by detecting the number of toggles of the light clock (WCK) and the reverse light clock (WCKB) input during the toggle period, and transmits the code signal (CODE) to the channel (CH2). It can be printed through.

The semiconductor device 40 can perform a write operation based on the command address (CA) input in synchronization with the clock (CLK). The semiconductor device 40 can latch data (DATA) in synchronization with the write clock (WCK) and the reverse write clock (WCKB) during the toggle period in the write operation. The semiconductor device 40 can store latched data (DATA) during a write operation. The semiconductor device 40 detects the number of toggles of the write clock (WCK) and the inverted write clock (WCKB) input during the toggle period and sends a code signal (CODE) containing characteristic information of the channel (CH2) to the controller 30. It can be output as .

FIG. 8 is a block diagram showing the configuration of the controller 30 included in the semiconductor system 2 according to one embodiment. The controller 30 may include an operation control circuit 410, a write clock control circuit 420, a write clock generation circuit 430, and a data generation circuit 440.

The operation control circuit 410 may be connected to the first pad 31 and the second pad 32. The operation control circuit 410 may output the first to Lth command addresses (CA<1:L>) for performing a write operation through the first pad 31. The control circuit 410 may output a periodically toggled clock (CLK) through the second pad 32. The first to Lth command addresses (CA<1:L>) may include “L” bits, and the bit number “L” of the first to Lth command addresses (CA<1:L>) is a positive integer. It can be set to .

The light clock control circuit 420 may generate an enable signal (PREN) that occurs at a logic high level during the pre-level section. The write clock control circuit 420 includes a pre-write clock (PWCK) generated at the ground voltage (VSS in FIG. 3) level and a pre-reverse write clock (PWCKB) generated at the power voltage (VDD in FIG. 3) level during the pre-level section. can be created. The write clock control circuit 420 may generate a preset write clock (PWCK) and a preset write clock (PWCKB) that are toggled periodically during the toggle period. The pre-write clock (PWCK) and pre-reverse write clock (PWCKB) can be toggled to a voltage level between the power supply voltage (VDD in FIG. 3) and the ground voltage (VSS in FIG. 3) during the toggle period.

The light clock generation circuit 430 may include a level driving circuit 431 and a transmission circuit 432.

The level driving circuit 431 may be connected to the third pad 33 and the fourth pad 34. The level driving circuit 431 may drive the third pad 33 based on the enable signal PREN during the pre-level period. The level driving circuit 431 may drive the fourth pad 34 based on the enable signal PREN during the pre-level period. Since the level driving circuit 431 is implemented with the same circuit as the level driving circuit 131 shown in FIG. 3 and performs the same operation, detailed description will be omitted.

The transmission circuit 432 may be connected to the third pad 33, fourth pad 34, and sixth pad 36. The transmission circuit 432 transmits the preset write clock (PWCK), the preset write clock (PWCKB), and the first to fourth code signals (CODE<1:4>) input through the sixth pad 36 during the pre-level section. Based on this, the third pad 33 can be driven. The transmission circuit 432 transmits the preset write clock (PWCK), the preset write clock (PWCKB), and the first to fourth code signals (CODE<1:4>) input through the sixth pad 36 during the pre-level section. Based on this, the fourth pad 34 can be driven. The transmission circuit 432 transmits the preset write clock (PWCK), the preset write clock (PWCKB), and the first to fourth code signals (CODE<1:4>) input through the sixth pad 36 during the toggle period. Based on this, the third pad 33 can be driven. The transmission circuit 432 transmits the preset write clock (PWCK), the preset write clock (PWCKB), and the first to fourth code signals (CODE<1:4>) input through the sixth pad 36 during the toggle period. Based on this, the fourth pad 34 can be driven. Since the transmission circuit 432 is implemented with the same circuit as the transmission circuit 132 shown in FIG. 4 and performs the same operation, detailed description is omitted.

The light clock generation circuit 430 may be connected to the third pad 33, fourth pad 34, and sixth pad 36. The write clock generation circuit 430 generates the first to fourth codes input through the enable signal (PREN), pre-write clock (PWCK), pre-reverse write clock (PWCKB), and sixth pad 36 during the pre-level section. Based on the signal (CODE<1:4>), a light clock (WCK) having a first set level can be output through the third pad 33. The write clock generation circuit 430 generates the first to fourth codes input through the enable signal (PREN), pre-write clock (PWCK), pre-reverse write clock (PWCKB), and sixth pad 36 during the pre-level section. Based on the signal (CODE<1:4>), an inverted write clock (WCKB) having a second set level can be output through the fourth pad 44. The write clock generation circuit 430 generates the first to fourth code signals (CODE<1:4>) input through the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and the sixth pad 36 during the toggle period. ) A light clock (WCK) that is toggled periodically based on can be output through the third pad 33. The write clock generation circuit 430 generates the first to fourth code signals (CODE<1:4>) input through the pre-write clock (PWCK), pre-reverse write clock (PWCKB), and the sixth pad 36 during the toggle period. ) A reversed write clock (WCKB) that is toggled periodically based on can be output through the fourth pad 34.

The data generation circuit 440 may be connected to the fifth pad 35. The data generation circuit 440 may output first to Nth data (DATA<1:N>) for performing a write operation through the fifth pad 35. The first to Nth data (DATA<1:N>) may include “N” bits, and the number of bits “N” of the first to Nth data (DATA<1:N>) is set to a positive integer. It can be.

FIG. 9 is a block diagram showing the configuration of the semiconductor device 40 included in the semiconductor system 2 according to one embodiment. The semiconductor device 40 includes a command generation circuit 510, an address generation circuit 520, a write clock buffer circuit 530, a detection circuit 540, a frequency divider circuit 550, a data processing circuit 560, and a core circuit. It may include (570).

The command generation circuit 510 may be connected to the seventh pad 41 and the eighth pad 42. The command generation circuit 510 is synchronized with the clock (CLK) input through the eighth pad 42 and generates the first to Lth command addresses (CA<1:L>) input through the seventh pad 41. Based on this, an internal command (ICMD) can be created. The command generation circuit 510 generates an internal command (ICMD) when the first to Lth command addresses (CA<1:L>) input in synchronization with the clock (CLK) are a logic level combination for performing a write operation. can do. The command generation circuit 510 is implemented to generate an internal command (ICMD) for performing a write operation, but may be implemented to generate a plurality of internal commands for performing various operations depending on the embodiment.

The address generation circuit 520 may be connected to the seventh pad 41 and the eighth pad 42. The address generation circuit 520 is synchronized with the clock (CLK) input through the eighth pad 42 and generates the first to Lth command addresses (CA<1:L>) input through the seventh pad 41. Based on this, the first to M internal addresses (IADD<1:M>) can be generated. The address generation circuit 520 decodes the first to Lth command addresses (CA<1:L>) that are input in synchronization with the clock (CLK) and generates selectively enabled first to Mth internal addresses (IADD<1). :M>) can be created. The first to M internal addresses (IADD<1:M>) may include “M” bits, and the number of bits “M” of the first to M internal addresses (IADD<1:M>) is a positive integer. It can be set to .

The light clock buffer circuit 530 may be connected to the ninth pad 43 and the tenth pad 44. The light clock buffer circuit 530 may generate an input write clock (I_WCK) by buffering the light clock (WCK) input through the ninth pad 43 during the toggle period. The write clock buffer circuit 530 may generate an inverted input write clock (I_WCKB) by buffering the inverted write clock (WCKB) input through the tenth pad 44 during the toggle period.

The sensing circuit 540 may be connected to the twelfth pad 46. The detection circuit 540 can generate the first to fourth code signals (CODE<1:4>) by detecting the number of toggling of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) during the toggle period. . The detection circuit 540 detects the number of toggles of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) to generate first to fourth code signals (CODE<1:4) including characteristic information of the channel (CH2). >) can be created. The sensing circuit 540 may output the first to fourth code signals (CODE<1:4>) through the twelfth pad 46. The detection circuit 540 is implemented to generate the first to fourth code signals (CODE<1:4>) by detecting the number of toggling of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) during the toggle period. However, depending on the embodiment, it can be implemented to generate the first to fourth code signals (CODE<1:4>) through various methods.

The frequency divider circuit 550 divides the frequencies of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) into the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and A fourth internal clock (QBCLK) can be generated. The frequency divider circuit 550 has a frequency equal to 1/2 that of the input write clock (I_WCK) and the inverted input write clock (I_WCKB) and sequentially generates a first internal clock (ICLK), a second internal clock (QCLK), and a second internal clock (QCLK). 3 internal clock (IBCLK) and fourth internal clock (QBCLK) can be generated. The phases of the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and the fourth internal clock (QBCLK) may each be generated with different phases.

The data processing circuit 560 may be connected to the 11th pad 45. The data processing circuit 560 is synchronized with the first internal clock (ICLK), second internal clock (QCLK), third internal clock (IBCLK), and fourth internal clock (QBCLK) and inputs through the eleventh pad 45. The first to Nth internal data (ID<1:N>) can be generated based on the first to Nth data (DATA<1:N>). The data processing circuit 560 is synchronized with the first internal clock (ICLK), the second internal clock (QCLK), the third internal clock (IBCLK), and the fourth internal clock (QBCLK) and inputs the first to Nth signals in series. The bits of the data (DATA<1:N>) can be latched and aligned to generate first to Nth internal data (ID<1:N>) generated in parallel. For example, the data processing circuit 560 latches the first data (DATA<1>) input to the rising edge of the first internal clock (ICLK), and latches the first data (DATA<1>) input to the rising edge of the second internal clock (QCLK). Latch the second data (DATA<2>), latch the third data (DATA<3>) input to the rising edge of the third internal clock (IBCLK), and latch the third data (DATA<3>) input to the rising edge of the fourth internal clock (QBCLK). The fourth input data (DATA<4>) can be latched. The data processing circuit 360 sorts the latched first to fourth data (DATA<1:4>) to generate first to fourth internal data (ID<1:4>) generated in parallel at the same time. can do.

The core circuit 570 may be implemented as a general memory circuit including a plurality of memory cells (not shown). The core circuit 570 connects the first to M memory cells (not shown) selected from a plurality of memory cells (not shown) based on the internal command (ICMD) and the first to M internal addresses (IADD<1:M>) The Nth internal data (ID<1:N>) can be saved. The core circuit 570 is implemented to perform a write operation, but depending on the embodiment, it may be implemented to perform an active operation, a read operation, a precharge operation, and a refresh operation.

FIG. 10 is a block diagram showing the configuration of the sensing circuit 540 included in the semiconductor device 40 according to one embodiment. The detection circuit 540 may include a counter 541 and a comparison circuit 542.

The counter 541 may generate the first to Kth counting signals (CNT<1:K>) based on the number of toggles of the input write clock (I_WCK) and the inverted input write clock (I_WCKB). The counter 541 may generate first to Kth counting signals (CNT<1:K>) that are sequentially counted whenever the input write clock (I_WCK) and the inverted input write clock (I_WCKB) are toggled. The first to Kth counting signals (CNT<1:K>) may include “K” bits, and the number of bits “K” of the first to Kth counting signals (CNT<1:K>) is a positive integer. It can be set to .

The comparison circuit 542 generates first to fourth code signals (CODE< 1:4>) can be created. When the first to Kth counting signals (CNT<1:K>) are counted lower than the first to Kth reference counting signals (REC<1:K>), the comparison circuit 542 The code signal (CODE<1:4>) can be upcounted. The comparison circuit 542 is the first to fourth counting signals when the first to Kth counting signals (CNT<1:K>) are counted the same number of times as the first to Kth reference counting signals (REC<1:K>). Code signals (CODE<1:4>) can be down-counted. The comparison circuit 542 performs the first to fourth counting signals when the first to Kth counting signals (CNT<1:K>) are counted a higher number of times than the first to Kth reference counting signals (REC<1:K>). Code signals (CODE<1:4>) can be down-counted. The first to Kth reference counting signals (REC<1:K>) may be set as signals containing reference information about the preset PVT change amount and preset transmission rate of the channel (CH2). The first to Kth reference counting signals (REC<1:K>) may be set as signals stored in a mode register set (MRS) included in the semiconductor device 40. The first to Kth reference counting signals (REC<1:K>) may include “K” bits, and the number of bits “K” of the first to Kth reference counting signals (REC<1:K>) is a positive number. It can be set to an integer of .

The operation of the detection circuit 540 according to another embodiment of the present invention will be described with reference to FIG. 11, where the first to fourth code signals (CODE < 1) are detected by detecting the number of toggling times of the light clock (WCK) during the toggle period. The operation of creating :4>) is explained as follows.

Prior to explanation, the light clock (WCK) generated by the first to Kth reference counting signals (REC<1:K>) including reference information for the preset PVT change amount and preset transmission rate of the channel (CH2) The case where the pulse width of is the first pulse width (W1) is explained as an example as follows. At this time, the light clock (WCK) is toggled 6 times during the set time (T).

First, the case where the pulse width of the write clock (WCK) is generated as the second pulse width (W2) is explained as follows.

When the pulse width of the light clock (WCK) is generated as the second pulse width (W2), the light clock (WCK) is toggled 12 times during the set time (T). The detection circuit 540 detects 12 toggling times of the light clock (WCK) and down-counts the first to fourth code signals (CODE<1:4>). The detection circuit 540 downcounts the first to fourth code signals CODE<1:4> until the clock WCK is toggled six times.

Each time the first to fourth code signals (CODE<1:4>) are down-counted (DOWN), the driving force for driving the write clock (WCK) decreases, and the pulse width of the write clock (WCK) gradually increases.

Next, the case where the pulse width of the write clock (WCK) is generated as the third pulse width (W3) is explained as follows.

When the pulse width of the light clock (WCK) is generated as the third pulse width (W3), the light clock (WCK) is toggled four times during the set time (T). The detection circuit 540 detects the number of toggling of the light clock (WCK) four times and up-counts (UP) the first to fourth code signals (CODE<1:4>). The detection circuit 540 upcounts (UP) the first to fourth code signals (CODE<1:4>) until the clock (WCK) is toggled six times.

Each time the first to fourth code signals (CODE<1:4>) are up-counted (UP), the driving force for driving the write clock (WCK) increases, and the pulse width of the write clock (WCK) gradually decreases.

The semiconductor system 2 according to another embodiment of the present invention generates a write clock (WCK) and a reverse write clock (WCKB) at a set level in accordance with the characteristic information of the channel during the pre-level period, and then periodically during the toggle period. The Inter Symbol Interface (ISI) of the channel can be reduced by generating a toggling write clock (WCK) and an inverted write clock (WCKB). The semiconductor system (2) generates a light clock (WCK) and an inverted light clock (WCKB) at a set level according to the characteristic information of the channel during the free level section, and then periodically toggles the light clock (WCK) and inverted light clock (WCKB) during the toggle section. By generating the light clock (WCKB), the light clock (WCK) and reverse write clock (WCKB) can be reliably generated. The semiconductor system 2 can perform stable data input/output operations by inputting and outputting data in synchronization with the stably toggled write clock (WCK) and inverted write clock (WCKB) after performing the pre-level control operation. .

Figure 12 is a block diagram showing the configuration of an electronic system 1000 according to an embodiment of the present invention. As shown in FIG. 12, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

The host 1100 and the semiconductor system 1200 may transmit signals to each other using an interface protocol. Interface protocols used between the host 1100 and the semiconductor system 1200 include Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and Peripheral Component Interconnect - Express (PCI-E). , Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), serial attached SCSI (SAS), and Universal Serial Bus (USB).

The semiconductor system 1200 may include a controller 1300 and semiconductor devices 1400 (1:K). The controller 1300 may control the semiconductor devices 1400(1:K) so that the semiconductor devices 1400(1:K) perform a write operation. The controller 1300 generates the light clock (WCK) and reverse light clock (WCKB) at a set level in accordance with the characteristic information of the channel during the free level section, and then periodically toggles the light clock (WCK) and reverse light during the toggle section. A clock (WCKB) can be generated. Each of the semiconductor devices 1400 (1:K) can latch data (DATA) in synchronization with a write clock (WCK) and an inverted write clock (WCKB), and store the latched data (DATA) in an aligned manner.

The controller 1300 may be implemented as the controller 10 shown in FIG. 1 or the controller 30 shown in FIG. 7. Each of the semiconductor devices 140 (1:K) may be implemented as the semiconductor device 20 shown in FIG. 1 or the semiconductor device 40 shown in FIG. 7. The semiconductor semiconductor devices 20 and 40 each include dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). Memory) can be implemented as one of the following.

The semiconductor system 1200 generates a light clock (WCK) and an inverted light clock (WCKB) at a set level according to the characteristic information of the channel during the pre-level section, and then periodically toggles the light clock (WCK) and inverted light clock (WCKB) during the toggle section. By generating a light clock (WCKB), the ISI (Inter Symbol Interface) of the channel can be reduced. The semiconductor system 1200 generates a light clock (WCK) and an inverted light clock (WCKB) at a set level according to the characteristic information of the channel during the pre-level section, and then periodically toggles the light clock (WCK) and inverted light clock (WCKB) during the toggle section. By generating the light clock (WCKB), the light clock (WCK) and reverse write clock (WCKB) can be reliably generated. After performing the pre-level adjustment operation, the semiconductor system 1200 can perform stable data input/output operations by inputting and outputting data in synchronization with the stably toggled write clock (WCK) and inverted write clock (WCKB). .

Embodiment 1
1. Semiconductor system 10. Controller
20. Semiconductor device 110. Operation control circuit
120. Light clock control circuit 130. Light clock generation circuit
131. Level driving circuit 132. Transmission circuit
140. Data generation circuit 210. First driving circuit
220. Second driving circuit 230. Light clock driving circuit
240. Inverted light clock driving circuit 310. Command generation circuit
320. Address generation circuit 330. Light clock buffer circuit
340. Frequency divider circuit 350. Data processing circuit
360. Core circuit
Second embodiment
2. Semiconductor system 30. Controller
40. Semiconductor device 410. Operation control circuit
420. Light clock control circuit 430. Light clock generation circuit
431. Level driving circuit 432. Transmission circuit
440. Data generation circuit 510. Command generation circuit
520. Address generation circuit 530. Light clock buffer circuit
540. Sensing circuit 550. Frequency dividing circuit
560. Data processing circuit 570. Core circuit

Claims (24)

A command address and data, as well as a write clock and an inverted write clock for latching the data are output through a channel, and during the pre-level period, the write clock is output at a first set level by reflecting the characteristic information of the channel, and the inverted light is output. a controller that outputs a clock at a second set level by reflecting the characteristic information of the channel, and periodically toggles and outputs the light clock and the inverted light clock during a toggle period; and
A semiconductor system comprising a semiconductor device that latches and stores the data in synchronization with the write clock and the inverted write clock.
According to claim 1,
The semiconductor system wherein the controller outputs the write clock at the first set level during the pre-level period based on a code signal reflecting characteristic information of the channel, and outputs the inverted write clock at the second set level.
According to claim 2,
The semiconductor system wherein the channel includes a plurality of pads and a plurality of transmission lines, and the characteristic information of the channel includes a PVT change amount and a transmission speed for the plurality of pads and the plurality of transmission lines.
According to claim 1,
The semiconductor system wherein the controller outputs the write clock at the level of a ground voltage and outputs the inverted write clock at the level of the power supply voltage when the data is not output.
The method of claim 1, wherein the controller
an operation control circuit that outputs the command address for controlling the operation of the semiconductor device through the channel;
a write clock control circuit that generates an enable signal generated during the pre-level section and generates a pre-inverted write clock, a pre-inverted write clock, and a code signal during the pre-level section and the toggle section;
During the pre-level period, the light clock having the first set level and the inverted write clock having the second set level are output through the channel based on the enable signal and the code signal, and during the toggle period. a write clock generation circuit that outputs the write clock and the inverted write clock, which are periodically toggled based on the preset write clock, the preset invert write clock, and the code signal, through the channel; and
A semiconductor system including a data generation circuit that outputs the data through the channel.
The method of claim 5, wherein the light clock control circuit
During the pre-level period, the pre-write clock is generated at a ground voltage level, the pre-invert write clock is generated at a power voltage level, and during the toggle period, the pre-write clock and the pre-invert write clock are periodically toggled. A semiconductor system that outputs.
The method of claim 5, wherein the light clock generation circuit is
a level driving circuit connected to a first pad through which the write clock is output and a second pad through which the inverted write clock is output, and driving the first pad and the second pad when the enable signal is enabled; and
It is connected to the first pad and the second pad, and drives the first pad and the second pad based on the pre-transition write clock, the pre-inversion write clock, and the code signal to generate the write clock and the inversion write clock. A semiconductor system that includes a transmission circuit that generates
The method of claim 7, wherein the level driving circuit is
a first driving circuit that receives charge from a power supply voltage and drives the first pad with a first pull-up driving force when the enable signal is enabled; and
A semiconductor system comprising a second driving circuit that discharges the charge of the second pad to a ground voltage and drives the second pad with a first pull-down driving force when the enable signal is enabled.
The method of claim 8, wherein the transmission circuit is
During the pre-level period, a second pull-down driving force is set according to the logic level combination of the code signal, and the first pad is driven with the second pull-down driving force according to the logic level combination of the pre-write clock and the invert pre-write clock. a light clock driving circuit that generates the light clock; and
During the pre-level period, a second pull-up driving force is set according to the logic level combination of the code signal, and the second pad is driven with the second pull-up driving force according to the logic level combination of the pre-write clock and the invert pre-write clock. A semiconductor system including an inverted write clock driving circuit that generates the inverted write clock.
According to clause 9,
The light clock is generated at the first set level by driving the first pad with the first pull-up driving force and the second pull-down driving force during the free level period,
The semiconductor system wherein the inverted write clock is generated at the second set level by driving the second pad with the first pull-down driving force and the second pull-up driving force during the free level period.
According to clause 9,
The light clock driving circuit generates the light clock that is toggled by driving the first pad according to the logic level combination of the code signal and the logic level combination of the pre-write clock and the inversion pre-write clock during the toggle period, and ,
The inverting light clock driving circuit drives the second pad according to the logic level combination of the code signal, the pre-write clock, and the logic level combination of the inversion pre-write clock during the toggle period to toggle the inverting light. A semiconductor system that generates clocks.
A command address and data, and a write clock and an inverted write clock for latching the data are output through a channel, and the write clock is output at a first set level based on a code signal input through the channel during the free level section. A controller that outputs an inverted light clock at a second set level, and outputs the inverted light clock and the inverted light clock that are periodically toggled during a toggle period. and
A semiconductor system comprising a semiconductor device that detects the write clock and the inverted write clock input during the toggle period, outputs the code signal, and latches and stores the data in synchronization with the write clock and the inverted write clock.
According to claim 12,
A semiconductor system wherein the semiconductor device detects the number of toggling times of the write clock and the inverted write clock input through the channel during the toggle period and generates the code signal including characteristic information of the channel.
According to claim 13,
The semiconductor system wherein the channel includes a plurality of pads and a plurality of transmission lines, and the characteristic information of the channel includes a PVT change amount and a transmission speed for the plurality of pads and the plurality of transmission lines.
The method of claim 12, wherein the controller
an operation control circuit that outputs the command address for controlling the operation of the semiconductor device through the channel;
a write clock control circuit that generates an enable signal generated during the pre-level section and generates a pre-inverted write clock and a pre-inverted write clock during the pre-level section and the toggle section;
During the pre-level period, the light clock having the first set level and the inverted write clock having the second set level are output through the channel based on the enable signal and the code signal, and during the toggle period. a write clock generation circuit that outputs the write clock and the inverted write clock, which are periodically toggled based on the preset write clock, the preset invert write clock, and the code signal, through the channel; and
A semiconductor system including a data generation circuit that outputs the data through the channel.
16. The method of claim 15, wherein the light clock control circuit
During the pre-level period, the pre-write clock is generated at a ground voltage level, the pre-invert write clock is generated at a power voltage level, and during the toggle period, the pre-write clock and the pre-invert write clock are periodically toggled. A semiconductor system that outputs.
16. The method of claim 15, wherein the write clock generation circuit is
a level driving circuit connected to a first pad through which the write clock is output and a second pad through which the inverted write clock is output, and driving the first pad and the second pad when the enable signal is enabled; and
It is connected to the first pad and the second pad, and drives the first pad and the second pad based on the pre-transition write clock, the pre-inversion write clock, and the code signal to generate the write clock and the inversion write clock. A semiconductor system that includes a transmission circuit that generates
The method of claim 17, wherein the level driving circuit is
a first driving circuit that receives charge from a power supply voltage and drives the first pad with a first pull-up driving force when the enable signal is enabled; and
A semiconductor system comprising a second driving circuit that discharges the charge of the second pad to a ground voltage and drives the second pad with a first pull-down driving force when the enable signal is enabled.
The method of claim 18, wherein the transmission circuit is
During the pre-level period, a second pull-down driving force is set according to the logic level combination of the code signal, and the first pad is driven with the second pull-down driving force according to the logic level combination of the pre-write clock and the invert pre-write clock. a light clock driving circuit that generates the light clock; and
During the pre-level period, a second pull-up driving force is set according to the logic level combination of the code signal, and the second pad is driven with the second pull-up driving force according to the logic level combination of the pre-write clock and the inverted pre-write clock. A semiconductor system including an inverted write clock driving circuit that generates the inverted write clock.
According to claim 19,
The light clock is generated at the first set level by driving the first pad with the first pull-up driving force and the second pull-down driving force during the free level period,
The semiconductor system wherein the inverted write clock is generated at the second set level by driving the second pad with the first pull-down driving force and the second pull-up driving force during the free level period.
According to claim 19,
The light clock driving circuit generates the light clock that is toggled by driving the first pad according to the logic level combination of the code signal and the logic level combination of the pre-write clock and the inversion pre-write clock during the toggle period, and ,
The inverting light clock driving circuit drives the second pad according to the logic level combination of the code signal, the pre-write clock, and the logic level combination of the inversion pre-write clock during the toggle period to toggle the inverting light. A semiconductor system that generates clocks.
The method of claim 12, wherein the semiconductor device
a light clock buffer circuit that buffers the light clock and the inverted light clock input during the toggle period to generate an input light clock and an inverted input write clock;
a detection circuit that generates the code signal by detecting the number of toggling times of the input write clock and the inverted input write clock during the toggle period;
a frequency divider circuit that divides the frequencies of the input write clock and the inverted input write clock to generate first to fourth internal clocks;
a data processing circuit that is synchronized with the first to fourth internal clocks and latches the data to generate internal data; and
A semiconductor system comprising an internal command generated from the command address and a core circuit that stores the internal data at a location selected by the internal address.
The method of claim 22, wherein the sensing circuit is
a counter that generates a counting signal that is sequentially counted each time the input write clock and the inverted input write clock are toggled; and
A semiconductor system comprising a comparison circuit that compares a reference counting signal and the counting signal to generate the code signal.
According to claim 23,
The comparison circuit up-counts the counting signal when the counting signal is counted lower than the reference counting signal, and down-counts the counting signal when the counting signal is counted the same or higher than the reference counting signal. A semiconductor counting system.

Images