KR20240046824A - Local passive matrix display - Google Patents

Abstract

A display may be formed by an array of light emitting diodes mounted on the surface of a display substrate. The light emitting diodes may be inorganic light emitting diodes formed from discrete crystalline semiconductor structures. An array of pixel control circuits can be used to control light emission from light emitting diodes. Each pixel control circuit may be configured to control one or more respective passive matrices. To control partial pixel cells within a display, a donor pixel control circuit within a partial pixel cell can control pixels within a receptor partial pixel cell without pixel control circuitry. To mitigate the size of the inactive area of the display, fanout signal lines for the display may be formed in the light-emitting active area of the display. Fanout signal lines may be formed between the row of pixel control circuits and the bottom edge of the light emitting active area.

Description

Local passive matrix display

This application is related to U.S. Patent Application No. 17/894,935, filed on August 24, 2022, U.S. Patent Application No. 17/894,942, filed on August 24, 2022, and U.S. Patent Application No. 17/894,942, filed on September 23, 2021. Claims priority to Provisional Patent Application No. 63/247,744, and U.S. Provisional Patent Application No. 63/247,747, filed September 23, 2021, which applications are hereby incorporated by reference in their entirety.

The present invention relates generally to electronic devices, and more particularly to electronic devices having displays.

Electronic devices often include displays. For example, an electronic device may have a liquid crystal display in which liquid crystal display pixels are used to display images to a user. Liquid crystal displays often include light emitting diode backlight units to provide backlight illumination. Display efficiency can be adversely affected by inefficiencies in generating backlight illumination and transmitting backlight illumination through liquid crystal display structures. Liquid crystal display structures also exhibit limited contrast ratios. Organic light emitting diode displays that exhibit high contrast ratios have been developed, but these devices can consume more power than desired due to inefficiencies in their organic light emitting diodes. Additionally, it can be difficult to ensure that organic light emitting diodes achieve the desired lifetime.

The electronic device may include a display. The display may be formed by an array of light emitting diodes mounted on the surface of a display substrate. The light emitting diodes may be inorganic light emitting diodes formed from discrete crystalline semiconductor structures. An array of pixel control circuits can be used to control light emission from light emitting diodes. Each pixel control circuit can be used to supply drive signals to each set of light emitting diodes arranged in a passive matrix.

Each pixel control circuit may be configured to control one or more respective passive matrices. However, some of the passive matrices may be interrupted by boundaries to the display (eg, rounded corners of the active area). These interrupted pixel groups may be referred to as partial pixel cells. Some of the partial pixel cells may still have dedicated pixel control circuitry. Some of the partial pixel cells may not have dedicated pixel control circuitry due to their pixel control circuitry falling outside the target boundary for the display.

To control partial pixel cells, additional pixel control circuits may be included misaligned with respect to the remaining array of pixel control circuits. Alternatively, a donor pixel control circuit within a partial pixel cell can control pixels within a receptor partial pixel cell without pixel control circuitry. The anode contacts in the different rows can be electrically connected to cause the donor pixel control circuit to control the acceptor portion pixel cell.

To mitigate the size of the inactive area of the display, fanout signal lines for the display may be formed in the light-emitting active area of the display. Fanout signal lines may be formed between the row of pixel control circuits and the bottom edge of the light emitting active area. Signal lines may additionally be formed between the row of pixel control circuits and the side edge of the light emitting active area.

1 is a perspective view of an example electronic device with a display according to one embodiment.
2 is a schematic diagram of an example electronic device with a display according to one embodiment.
3 is a diagram of an example display according to one embodiment.
Figure 4 is a schematic diagram of an example passive matrix of light emitting diodes controlled by a pixel control circuit according to one embodiment.
Figure 5 is a top view of an example passive matrix of light emitting diodes with a grid of anode contacts and cathode contacts according to one embodiment.
Figure 6A is a schematic diagram of an example pixel control circuit controlling two passive matrices according to one embodiment.
Figure 6B is a schematic diagram of an example pixel control circuit controlling four passive matrices according to one embodiment.
Figure 7 is a top view of an example display with an active area border interrupting pixel cells with pixel control circuits according to one embodiment.
Figure 8 is a top view of an example display with additional pixel control circuits used to control partial pixel cells according to one embodiment.
9 is a top view of an example display with partial pixel cells controlled by neighboring pixel control circuitry, according to one embodiment.
10 is a top view of an example display showing how anode contacts in a donor passive matrix may be electrically connected to anode contacts in a receptor passive matrix according to one embodiment.
11 is a schematic diagram of an example display with pixel mapping circuitry according to one embodiment.
Figure 12 is a top view of an example display showing how a receptor passive matrix can be controlled by multiple donor pixel control circuits according to one embodiment.
13A is a top view of an example display with rounded corners and notches according to one embodiment.
13B is a top view of an example display with an aperture in the active area according to one embodiment.
Figure 14 is a top view of an example display with fan-out signal lines within an inactive area of the display according to one embodiment.
Figure 15 is a top view of an example display with fan-out signal lines within an active area of the display according to one embodiment.
Figure 16 is a cross-sectional side view of an example display with a fan-out signal line area within an active area according to one embodiment.
Figure 17 is a top view of an example display with peripheral signal lines within an active area of the display according to one embodiment.
FIG. 18A is a top view of an example display in which a first row of pixels within a display active area is aligned with the top of pixel cells controlled by a first row of pixel control circuits, according to one embodiment.
FIG. 18B is a top view of an example display where the first row of pixels within the display active area are not aligned with the top of the pixel cells controlled by the first row of pixel control circuits, according to one embodiment.
Figure 19 is a top view of an example display with pixel control circuits formed on different stamps according to one embodiment.

An exemplary electronic device of the type in which a display may be provided is shown in FIG. 1 . An electronic device, such as electronic device 10 of FIG. 1 , may be a computing device such as a laptop computer, a computer monitor, including an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, or a smaller device. , such as a wristwatch device, a pendant device, a headphone or earpiece device, an embedded device within glasses or other equipment worn on the user's head, or other wearable or small devices, televisions or other displays for video, and embedded computers. It is not a computer display, a gaming device, a navigation device, an embedded system such as a kiosk or system in which an electronic device with a display is mounted, equipment that implements the functionality of two or more of these devices, or other electronic equipment. You can. The configuration of device 10 shown in FIG. 1 (e.g., a portable device configuration where device 10 is a cellular phone, media player, wrist device, tablet computer, or other portable computing device) is shown as an example. If desired, other configurations for device 10 may be used.

Device 10 may have one or more displays, such as display 14, mounted on housing structures such as housing 12. The housing 12 of device 10, sometimes referred to as a case, may be made of plastic, glass, ceramic, carbon-fiber composites and other fiber-based composites, metal (e.g., machined aluminum, stainless steel, or other metals). ), other materials, or a combination of these materials. Device 10 may be formed using unibody construction, in which most or all of housing 12 is formed from a single structural element (e.g., a machined piece of metal or a molded plastic piece), or It may be formed from multiple housing structures (eg, outer housing structures mounted on inner frame elements or other inner housing structures).

Display 14 may be a touch-sensitive display that includes a touch sensor, or may be insensitive to touch. Touch sensors for display 14 may be formed from an array of capacitive touch sensor electrodes, a resistive touch array, touch sensor structures based on acoustic touch, optical touch or force-based touch technologies, or other suitable touch sensor components. You can. Touch sensor electrodes may be used to capture touch input from a user's finger or stylus and/or may be used to collect fingerprint data.

Display 14 may include an array of pixels that emit light, such as an array of light emitting diode pixels. Generally, display 14 may use light emitting diode display technology, liquid crystal display technology, such as organic light emitting diode display technology, plasma display technology, electrophoretic display technology, electrowetting display technology, or other types of display technologies. Configurations in which the display 14 is based on an array of light emitting diodes are sometimes described herein as an example. However, this is merely illustrative. Other types of display technologies may be included in device 10 if desired.

A schematic diagram of an electronic device, such as electronic device 10 of FIG. 1, is shown in FIG. 2. As shown in FIG. 2 , electronic device 10 may have control circuitry 16 . Control circuitry 16 may include storage and processing circuitry to support operation of device 10. The storage and processing circuitry may include hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (e.g., static memory), or dynamic random access memory), etc. Processing circuitry within control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, voice codec chips, application-specific integrated circuits, etc.

Input-output circuitry within device 10, such as input-output devices 18, may be used to provide data to device 10 and allow data to be provided from device 10 to external devices. Input-output devices 18 include buttons, joysticks, scrolling wheels, touch pads, fingerprint sensors, key pads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors. , light emitting diodes and other status indicators, data ports, etc. A user can control the operation of device 10 by supplying commands through input-output devices 18 and receive status information and information from device 10 using the output resources of input-output devices 18. Other outputs can be received. Input-output devices 18 may include one or more displays, such as display 14 of FIG. 1 .

Control circuitry 16 may be used to execute software on device 10, such as operating system code and applications. During operation of device 10 , software running on control circuitry 16 may display images on display 14 at input-output devices 18 .

As shown in the example diagram of FIG. 3 , display 14 may include layers such as substrate layer 24 . Layers such as substrate 24 may include glass layers, polymer layers, composite films including polymers and inorganic materials, metal foils, semiconductors such as silicon or other semiconductor materials, layers of a material such as sapphire (e.g. , crystalline transparent layers, ceramics, etc.), or other materials. Substrate 24 may be planar or may have other shapes (eg, concave shapes, convex shapes, shapes with planar and curved surface areas, etc.). The outline of the substrate 24 (e.g., when viewed from above along the Z-direction) may be circular, oval, rectangular, square, have a combination of straight and curved edges, or have other suitable shapes. . As shown in the rectangular substrate example of Figure 3, substrate 24 may have left and right vertical edges and top and bottom horizontal edges.

Display 14 may have an array of pixels 22 for displaying images for a user. Sets of one or more pixels 22 may be controlled using respective pixel control circuits 20 (sometimes referred to as driver circuits 20 or microdrives 20). Pixel control circuits 20 may be formed using integrated circuits (eg, silicon integrated circuits) and/or thin film transistor circuitry on substrate 24 . Thin film transistor circuitry may include thin film transistors formed from silicon (e.g., polysilicon thin film transistors or amorphous silicon transistors) and/or semiconductor oxides (e.g., indium gallium zinc oxide transistors or other semiconductor oxide thin film transistors). Based on this, it may include thin film transistors. Semiconductor oxide transistors, such as indium gallium zinc oxide transistors, can exhibit low leakage current, and thus configurations for the display 14 where lowering power consumption (e.g., by lowering the refresh rate for the pixels of the display) is desirable. can be advantageous. If desired, configurations for display 14 may be used in which pixel control circuits 20 are formed from a silicon integrated circuit and a set of thin film semiconductor oxide transistors, respectively.

Pixels 22 may be structured in an array (eg, an array with rows and columns). Pixel control circuits 20 may be structured as an associated array (eg, an array with rows and columns). As shown in FIG. 3 , pixel control circuits 20 may be interspersed among the array of pixels 22 . Pixels 22 and pixel control circuits 20 may be structured in arrays with rectangular outlines or may have outlines of other suitable shapes. Each array may have any suitable number of rows and columns (eg, 10 or more, 100 or more, or 1000 or more).

Each pixel 22 may be formed from a light emitting component, such as a light emitting diode. If desired, each pixel may include a pair of light emitting diodes or another suitable number of light emitting diodes for redundancy. In this type of configuration, a pair of light emitting diodes within each pixel may (as an example) be driven in parallel. If one of the light emitting diodes fails, the other light emitting diode will still produce light. Alternatively or additionally, multiple pixel control circuits may be configured to control each pixel. If one of the pixel control circuits fails, the other pixel control circuit will still control the pixel.

Display driver circuitry, such as display driver circuitry 28, may be coupled to conductive paths, such as metal traces, on substrate 24 using solder or conductive adhesive. Display driver circuitry 28 may include communication circuitry for communicating with system control circuitry via path 26. Path 26 may be formed from traces on a flexible printed circuit or other cable, or may be formed using other signal path structures within device 10. Control circuitry may be located on the main logic board within the electronic device in which display 14 is being used. During operation, control circuitry on the logic board (e.g., control circuitry 16 of FIG. 1) may supply information about the images to be displayed on display 14 to circuitry, such as display driver circuitry 28. To display images on display pixels 22, display driver circuitry 28 may supply corresponding image data, control signals, and/or power supply signals to signal lines S. The signal lines provide corresponding image data, control signals, and power to the pixel control circuits 20. Based on the received power, image data, and control signals, pixel control circuits 20 instruct each subset of pixels 22 to generate light at desired intensity levels.

Signal lines S may carry analog and/or digital control signals (eg scan signals, emission transistor control signals, clock signals, digital control data, power supply signals, etc.). In some cases, a signal line may be coupled to each row of pixel control circuits 20. In some cases, a signal line may be coupled to each row of pixel control circuits 20. Each pixel control circuit 20 may be coupled to one or more signal lines. Circuitry 28 is located on the top edge of display 14 (as in Figure 3), on the bottom edge of display 14, on the top and left edges of display 14, on the top, left side of the display. , and on the right edges, or any other desired location(s) within display 14.

Display control circuitry, such as circuitry 28, may be implemented using one or more integrated circuits (e.g., display driver integrated circuits, such as timing controller integrated circuits and associated source driver circuits and/or gate driver circuits). Alternatively, it may be implemented using a thin film transistor circuit implemented on the substrate 24.

Pixels 22 may be organic light emitting diode pixels or liquid crystal display pixels. Alternatively, pixels 22 may be formed of individual inorganic light emitting diodes (sometimes referred to as microLEDs). Pixels 22 may include light emitting diodes of different colors (eg, red, green, blue). Corresponding signal lines can be used to carry red, green, and blue data. If desired, pixel arrays of different colors can be used (e.g., four color arrays, arrays containing white pixels, three pixel configurations with pixels other than red, green, and blue pixels, etc.) . To create different colors, the light emitting diodes of pixels 22 are made of different materials systems (e.g., AlGaAs for the red diodes, GaN multiple quantum well diodes with different quantum well configurations for the green and blue diodes, respectively). ) and may be formed using different phosphorescent materials or different quantum dot materials to produce red, blue, and/or green light emission, or formed using other techniques or combinations of these techniques. It can be. The light emitting diodes of pixels 22 may radiate upward (i.e., pixels 22 may use a top emitting design), or may radiate downward through substrate 24 (i.e., pixels 22 may use a top emitting design). 22 may use a bottom discharge design). Light emitting diodes can (as examples) have a thickness of about 0.5 to 10 microns and a lateral dimension of 2 microns to 100 microns. If desired, light emitting diodes having different thicknesses (e.g., less than 2 microns, more than 2 microns, etc.) and different lateral dimensions (e.g., less than 10 microns, less than 20 microns, more than 3 microns, more than 15 microns, etc.) can also be used. You can.

If desired, digital control signals can be provided to circuits 20 (on signal lines S), which can then generate corresponding analog light emission drive signals based on the digital control signals. During operation of display 14, each pixel control circuit 20 outputs a signal to a corresponding set of pixels 22 based on control signals received by that pixel control circuit from display driver circuitry 28. can supply them.

As an example, each pixel control circuit 20 may control a respective local passive matrix 30 of LED pixels 22. Figure 4 is a schematic diagram of a local passive matrix 30 of LED pixels 22. As shown in Figure 4, the anode of each LED 22 is coupled to a respective anode contact line A (sometimes referred to as anode contact A or anode line A). The LEDs 22 of each row in the passive matrix are connected to a common anode contact (A). The cathode of each LED 22 is coupled to a respective cathode contact line C (sometimes referred to as cathode contact C or cathode line C). Each row of LEDs 22 in the passive matrix is connected to a common cathode contact (C).

The pixel control circuit 20 can control the current and voltage provided to each anode line (A). Pixel control circuit 20 may also control the voltage provided to each cathode contact line (C). In this way, pixel control circuit 20 controls the current through each light emitting diode 22, which controls the intensity of light emitted by each light emitting diode. During operation of the passive matrix, pixel control circuitry 20 can scan pixels 22 row by row at high speed to cause each LED 22 to emit light at a desired brightness level. That is, each pixel in the first row is updated to the desired brightness level, then each pixel in the second row is updated to the desired brightness level, and so on.

Pixel control circuit 20 may have first output terminals 32 coupled to anode contact lines (A) and second output terminals 34 coupled to cathode contact lines (C). Pixel control circuit 20 may have, as an example, one output terminal 32 per anode contact line and one output terminal 34 per cathode contact line. Accordingly, using a passive matrix as in Figure 4, the pixel control circuit 20 can control 64 light emitting diodes (e.g., using only 16 outputs (8 anode output terminals and 8 cathode output terminals)). can be controlled (on an 8 x 8 grid).

Figure 5 is a top view of passive matrix 30 showing how pixel control circuit 20 may be electrically connected to respective anode contacts (A) and cathode contacts (C). In the example of Figure 5, the local passive matrix of LEDs is an 8 x 8 array. Therefore, there are eight anode contacts (A) and eight cathode contacts (C) arranged in an overlapping grid. The anode contacts extend orthogonally to the cathode contacts, and each overlap position between the anode and cathode contacts defines a respective LED pixel 22.

As shown in Figure 5, the display may include routing lines, such as routing lines 36 and 38, to electrically connect the output terminals of the pixel control circuit 20 to the anode and cathode contacts. Specifically, a plurality of routing lines 36 are included to connect the output terminals 32 of the pixel control circuit 20 to the respective anode contacts A. A plurality of routing lines 38 are included to connect the output terminals 34 of the pixel control circuit 20 to the respective cathode contacts C. Including routing lines 36 and 38 allows the footprint and position of pixel control circuit 20 to be selected independently from the positions of the anode and cathode contacts. As an example, routing lines 36 and 38 may be formed by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias passing through one or more layers of substrate 24. there is.

Each pixel control circuit 20 can control a single passive matrix of LED pixels or multiple passive matrices of LED pixels. FIG. 6A is a schematic diagram showing how an example pixel control circuit 20 may control the first and second passive matrices 30 of LEDs 22 . FIG. 6B is a schematic diagram showing how an example pixel control circuit 20 may control the first, second, third, and fourth passive matrices 30 of LEDs 22. In general, each pixel control circuit 20 can control any desired number of LED passive matrices 30 (eg, 1, 2, 3, 4, more than 4, etc.). Each passive matrix 30 can be configured with any desired number of rows and columns of LEDs (e.g., more than 1, more than 3, more than 6, more than 10, then more than 20, more than 50, more than 6). less than, less than 10, then less than 20, less than 50, etc.).

Ultimately, each pixel control circuit 20 may be configured to control a respective subset of LED pixels. Each subset of LED pixels controlled by a respective pixel control circuit may be referred to as a pixel cell, passive matrix cell, etc. Each pixel cell may be comprised of one or more individual passive matrices, as shown and discussed in connection with FIGS. 4-6.

7 is a top view of an example display having a plurality of pixel control circuits 20 and corresponding pixel cells 40. Each pixel cell may include an array of LED pixels (eg, microLEDs) arranged in one or more passive matrices. Each pixel control circuit 20 applies signals to the anode contacts A and cathode contacts C of the passive matrices within its respective pixel cell 40 to control the pixels within its respective pixel cell 40. The light emitted can be controlled by.

This pixel control scheme can be influenced by the geometry of the display's emissive area. For example, consider an example where each pixel control circuit is configured to control an m x n cell of pixels (having m rows and n columns). If a pixel control circuit has an associated m x n cell of pixels to control, the pixel control circuit may be said to be controlling a full pixel cell. The pixel control circuits are distributed across the display so that most of the pixel control circuits can have an associated full m x n cell of pixels to control. However, the geometry of the display may cause some pixel control circuits to have only partial pixel cells. That is, the pixel control circuit may control fewer pixels than it is capable of. Conversely, some LED pixels may not have an associated pixel control circuitry (the geometry of the display allows individual pixel control circuitry for those LED pixels to be omitted).

The light-emitting active area of the display may have a footprint with rounded corners, for example. Figure 7 shows how the active area of the display follows a border 42 that is rounded at the corners of the display. Boundary 42 (sometimes referred to as spline 42) may be a target boundary for the display. Light-emitting LED pixels 22 are included and omitted to approximate the curvature of border 42 at the rounded corners.

Figure 7 shows how target boundary 42 traverses through some of pixel cells 40. This causes some of the pixel cells to become partial pixel cells, as previously described. For example, the first pixel control circuit 20-1 controls full pixel cells 40-1, while the second pixel circuit 20-2 controls partial pixel cells 40-2. Partial pixel cell 40-2 is interrupted by target boundary 42. Accordingly, pixels outside of boundary 42 within pixel cell 40-2 may be omitted from the display.

Additionally, pixel control circuits outside the target boundary may be omitted from the display. In the example of Figure 7, three pixel control circuits, including pixel control circuit 20-3, are positioned outside the target boundary 42. Including these pixel control circuits can increase the size of the non-emissive inactive area of display 14. Accordingly, to reduce the size of the non-emissive inactive area, these pixel control circuits (indicated by dashed lines) can be omitted from the display. This causes the substrate 24 to be cut to have approximately the same shape as the target boundary 42, with only a small non-emissive inactive area existing between the edge of the emissive active area and the edge of the substrate.

Omitting these pixel control circuits can create partial pixel cells that do not have dedicated pixel control circuitry. Figure 7 shows how the partial pixel cell 40-3 does not have a dedicated pixel control circuit (since its corresponding pixel control circuit 20-3 is positioned outside the target boundary and is therefore omitted). . Similarly, partial pixel cell 40-4 does not have dedicated pixel control circuitry (since its corresponding pixel control circuitry is positioned outside the target boundary and is therefore omitted).

Display 14 may include additional components to ensure that partial pixel cells with cutoff pixel control circuits are driven and emit a desired amount of light during operation.

As shown in Figure 8, a first option for controlling these partial pixel cells is to include additional pixel control circuits. Partial pixel cell 40-3 may include additional pixel control circuitry 20-A1 that is shifted within target boundary 42. Accordingly, there is sufficient space available on the display substrate 24 to include additional pixel control circuitry 20-A1. Partial pixel cell 40-4 may include additional pixel control circuitry 20-A2 that is shifted within target boundary 42. Accordingly, there is sufficient space available on the display substrate 24 to include additional pixel control circuitry 20-A2.

In the central portion of the display, the pixel control circuits may have a pitch 44 in the X-direction and a pitch 46 in the Y-direction. Pitches 44 and 46 extend across the display such that the pixel control circuits (which may be formed by integrated circuits) are arranged in evenly spaced rows and columns (as shown in FIGS. 7 and 8). It can be uniform. However, the additional pixel control circuits 20-A1 and 20-A2 are misaligned with respect to surrounding rows and/or columns. That is, most of the pixel control circuits 20 are arranged in rows and columns. The pixel control circuit 20-A1 is shifted in the X-direction with respect to the pixel control circuit columns. The pixel control circuit 20-A1 is shifted in the Y-direction with respect to the pixel control circuit rows.

As shown in Figure 8, the spacing between pixel control circuit 20-A1 and its adjacent pixel control circuits is smaller than pitches 44 and 46. Similarly, the spacing between pixel control circuit 20-A2 and its adjacent pixel control circuits is less than pitches 44 and 46. Accordingly, the positions of the additional pixel control circuits are modified relative to the pattern of the remainder of the pixel control circuits to ensure that every partial pixel cell has a corresponding pixel control circuit.

Figure 9 shows an option for controlling partial pixel cells without additional pixel control circuits. As shown in Figure 9, the pixel driver circuit of a neighboring partial pixel cell can be used to drive the pixels of the partial pixel cell. As an example, each pixel control circuit drives a 16 x 16 grid of pixels (arranged in one or more passive matrices). Accordingly, the pixel control circuit has output terminals for a 16 x 16 grid of pixels and logic and control circuitry for driving the 16 x 16 grid of pixels. However, partial pixel cells within a display may contain less than a full 16 x 16 grid of pixels.

Consider a pixel cell 40-1 that includes a pixel control circuit 20-1 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-1 is interrupted by border 42 and is therefore a partial pixel cell. A partial pixel cell may, for example, contain only 150 pixels (instead of the 256 pixels of a full 16 x 16 pixel cell). Accordingly, the pixel control circuit 20-1 has only 150 pixels to control instead of the full 256 pixels. Accordingly, the pixel control circuit 20-1 is underutilized by 106 pixels. That is, the pixel control circuit 20-1 has the ability to control 106 additional pixels due to omitted pixels within its pixel cell. Pixels, such as pixels X1, outside the target boundary will typically be driven by the pixel control circuit 20-1. However, pixels within area X1 are omitted from the display because they are outside border 42.

Meanwhile, the partial pixel cell 40-3 includes pixels within area X2 but does not have a dedicated pixel control circuit. Instead of including additional pixel control circuitry as in Figure 8, the pixels within area X2 may be driven by the underutilized neighboring pixel control circuit 20-1. Partial pixel cell 40-3 may include fewer than 106 pixels in area X2 (eg, fewer pixels than the underutilization of pixel control circuit 20-1). Accordingly, pixel control circuit 20-1 has the ability to control all pixels within area X2 in addition to pixels within its own partial pixel cells.

Using this type of approach allows the number of pixel control circuits in the display to be reduced while maintaining a small inactive border area, when underutilized pixel control circuits are used to control pixels that do not otherwise have dedicated pixel control circuitry. there is.

As another example of this concept, consider pixel cell 40-2 including pixel control circuit 20-2 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-2 is interrupted by border 42 and is therefore a partial pixel cell. Accordingly, the pixel control circuit 20-2 is underutilized. That is, the pixel control circuit 20-2 has the ability to control additional pixels due to omitted pixels within its pixel cell. Pixels outside the target boundary, such as Y1, will typically be driven by pixel control circuit 20-2. However, pixels within area Y1 are omitted from the display because they are outside border 42.

Meanwhile, the partial pixel cell 40-4 includes pixels within area Y2 but does not have a dedicated pixel control circuit. Instead of including additional pixel control circuitry as in Figure 8, the pixels within area Y2 can be driven by the underutilized neighboring pixel control circuit 20-2. Partial pixel cell 40-4 may contain fewer pixels than the underutilized amount of pixel control circuit 20-2. Accordingly, pixel control circuit 20-2 has the ability to control all pixels within area Y2 in addition to pixels within its own partial pixel cells.

10 is a top view of an example display showing how pixels within a pixel cell can be controlled by pixel control circuitry in a different neighboring pixel cell. In the example of Figure 10, each pixel control circuit is configured to control four passive matrices (similar to those shown in Figure 6B). In this example, each passive matrix is an 8 x 8 grid (eg, similar to that shown in Figure 5). In the central part of the display, each pixel control circuit can control four 8 x 8 passive matrices.

Along border 42 (see FIG. 9), one or more 8 x 8 passive matrices may be suspended. The result may be a partially passive matrix containing less than 8 full rows and/or less than 8 full columns. Figure 10 shows that, adjacent to the border of the display, there is a first partial passive matrix 30-1 (comprising 8 pixels) and a second partial passive matrix 30-2 (comprising 31 pixels). Show how. Partial passive matrix 30-1 may be a portion of pixel cell 40-1 (see Figure 9) that includes dedicated pixel control circuitry 20-1. Partial passive matrix 30-2 is a portion of pixel cells 40-3 (see Figure 9) that does not contain dedicated pixel control circuitry. Each partial passive matrix contains light-emitting pixels 22 . Figure 10 also shows the footprint of the omitted pixels 22'. The omitted pixels 22' will complete an 8 x 8 passive matrix for each one of the passive matrices 30-1 and 30-2. However, the boundaries of the display cause pixels 22' to be omitted.

The pixel control circuit 20-1 of FIG. 10 can control the passive matrices 30-3, 30-4, and 30-5 in addition to the partial passive matrix 30-1. One or both of the passive matrices 30-3 and 30-4 may be partially passive matrices. Passive matrix 30-5 may be a full passive matrix (having a full 8 x 8 grid of emitting pixels).

Pixel control circuit 20-1 has eight anode outputs 1A to 8A (e.g., output terminals 32 in FIG. 5) and eight cathode outputs configured to drive passive matrix 30-1. 1C to 8C) (e.g., output terminals 34 in FIG. 5). However, the passive matrix 30-1 is a partially passive matrix. Accordingly, the output terminals of the pixel control circuit 20-1 can drive the partial passive matrix 30-2 from neighboring pixel cells in addition to the partial passive matrix 30-1.

As shown in Figure 10, cathode outputs 1C to 6C in pixel control circuit 20-1 are electrically connected to cathode contacts C in partial passive matrix 30-2. Cathode outputs 7C to 8C in pixel control circuit 20-1 are electrically connected to cathode contacts in partial passive matrix 30-1. Each cathode output terminal in the pixel control circuit 20-1 may be electrically connected to a corresponding cathode contact point by a respective signal routing line 38. As an example, signal routing lines 38 may be formed by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias passing through one or more layers of substrate 24. . To access the cathode contacts C in the partial passive matrix 30-2, some of the signal routing lines 38 (e.g., for output terminals 1C to 6C) are connected to the pixel cell 40-1. ) from the interior (including the passive matrices 30-1, 30-3, 30-4, and 30-5) through the periphery of the pixel cell 40-1 to the exterior of the pixel cell 40-1. Can be routed up to

As shown in Figure 10, anode outputs 1A to 5A in pixel control circuit 20-1 are electrically connected to anode contacts A in partial passive matrix 30-1. Anode outputs 6A to 8A in pixel control circuit 20-1 are electrically connected to anode contacts in partial passive matrix 30-2. Each anode output terminal in the pixel control circuit 20-1 may be electrically connected to a corresponding anode contact by a respective signal routing line 36. As an example, signal routing lines 36 may be formed by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias passing through one or more layers of substrate 24. . To access the anode contacts A in the partial passive matrix 30-2, some of the signal routing lines 36 (e.g., for output terminals 6A-8A) are connected to the pixel cell 40-1. ) from the interior (including the passive matrices 30-1, 30-3, 30-4, and 30-5) through the periphery of the pixel cell 40-1 to the exterior of the pixel cell 40-1. Can be routed up to

In the example of Figure 10, some of the pixels in partial pixel matrix 30-1 share an anode contact with some of the pixels in partial pixel matrix 30-2. Accordingly, interconnect routing lines 50 may be electrically included in an anode contact in matrix 30-1 together with an anode contact in matrix 30-2. As an example, interconnect routing lines 50 may be formed by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias passing through one or more layers of substrate 24. there is. Each interconnect routing line electrically connects two individual anode contacts. For example, the first anode contact overlaps the first and second pixels on the leftmost column in pixel matrix 30-1. The second anode contact overlaps one pixel on the rightmost column in pixel matrix 30-2. An interconnection routing line electrically connects these two anode contacts. As another example, the right-most anode contact in passive matrix 30-1 overlaps one pixel. The fifth anode contact in passive matrix 30-2 (from left to right) overlaps four pixels. An interconnection routing line electrically connects these two anode contacts.

As shown in Figure 10, pixels within area X2 of passive matrix 30-2 correspond to corresponding omitted pixels within area X1 of passive matrix 30-1. The arrangement of the electrical connections between pixel control circuit 20-1, passive matrix 30-1, and passive matrix 30-2 is such that each pixel in area can be selected to have the same pixel. In this way, the pixel control circuit can provide output signals when the pixels in area X1 were actually present. Based on the electrical connections to the pixel control circuit 20-1, pixel 1 in area X2 corresponds to pixel 1' in area X1. That is, pixel 1 in area X2 is driven by the pixel control circuit as if it were at the row 1, column 1 position in passive matrix 30-1. However, when the pixel control circuit 20-1 outputs control signals to control the light emitted by the pixel at the row 1, column 1 position, the pixel 1 in the area X2 actually emits light. . Based on the electrical connections to the pixel control circuit 20-1, pixel 2 in area X2 corresponds to pixel 2' in area X1. That is, pixel 2 in area X2 is driven by the pixel control circuit as if it were at the row 1, column 8 position in passive matrix 30-1. However, when the pixel control circuit 20-1 outputs control signals to control the light emitted by the pixel at the row 1, column 8 position, the pixel 2 in the area X2 actually emits light. . Based on the electrical connections to the pixel control circuit 20-1, pixel 3 in area X2 corresponds to pixel 3' in area X1. That is, pixel 3 in area X2 is driven by the pixel control circuit as if it were at the row 6, column 8 position in passive matrix 30-1. However, when the pixel control circuit 20-1 outputs control signals to control the light emitted by the pixel at the row 6, column 8 position, the pixel 3 in the area X2 actually emits light. . Based on the electrical connections to the pixel control circuit 20-1, pixel 4 in area X2 corresponds to pixel 4' in area X1. That is, pixel 4 in area X2 is driven by the pixel control circuit as if it were at the row 4, column 4 position in passive matrix 30-1. However, when the pixel control circuit 20-1 outputs control signals to control the light emitted by the pixel at the row 4, column 4 position, the pixel 1 in the area X2 actually emits light. .

Accordingly, the driving method and logic within the pixel control circuit 20-1 do not need to be modified for other pixel control circuits within the display. The pixel control circuit 20-1 outputs signals in the same manner as other pixel control circuits in the display. However, because of the modified electrical connections, the pixel control circuit 20-1 controls the partially passive matrix 30-1 and the partially passive matrix 30-2 in a driving manner.

Typically (e.g., to control a full passive matrix as in Figure 5), each anode contact in the passive matrix overlaps a pixel in a given row of one of the pixels in the overall display. 10 , in contrast, anode contacts overlapping pixels in separate rows of pixels in the display may be electrically connected. Because the anode contacts are electrically connected, the passive matrix behaves electrically as if the pixels were in the same row (as in Figure 5). However, because of the interconnection between the anode contacts, pixels from the same "column" (electrically) of the passive matrix are physically split between the two columns of the display.

In Figure 10, the anode contacts (e.g., for output terminals 1A to 5A) are split between multiple physical positions, and each cathode contact is not split between different positions. However, if desired, the cathode contacts may be split between different locations (and electrically connected to interconnect routing lines) in the same manner as the anode contacts of Figure 10.

In Figure 10, there is a horizontal mirroring of the pixels in area X2 and their corresponding pixels in area X1. That is, the omitted pixel 1' on the leftmost side of the manual matrix 30-1 is mapped to the actual pixel on the rightmost side of the manual matrix 30-2, and the omitted pixel 1' on the rightmost side of the passive matrix 30-1 The pixel 2' is mapped to the actual pixel on the leftmost side of the passive matrix 30-2, and so on. Using horizontal mirroring in this manner can be advantageous in minimizing the complexity of interconnect routing between passive matrices 30-1 and 30-2.

It is merely illustrative that the example pixel control circuit 20-1 of FIG. 10 provides signals to anode contacts in passive matrix 30-2 via anode contacts in passive matrix 30-1. Instead, the opposite arrangement may be used, with pixel control circuit 20-1 providing signals to the anode contacts in passive matrix 30-1 via the anode contacts in passive matrix 30-2.

The electronic device may include pixel mapping circuitry configured to map target pixel brightness values to corresponding pixels controlled by pixel control circuits. 11 is a schematic diagram of an example display in which pixel mapping circuitry 52 is included in display driver circuitry 28. Display driver circuitry 28 may receive pixel data (e.g., from a graphics processing unit or other device component) and output corresponding mapped pixel data to pixel control circuits 20 on the display panel for display. there is.

The pixel mapping circuit 52 may receive pixel data corresponding to a target image to be displayed on the display. That is, the received pixel data may include target brightness values for physical locations across the display. Pixel mapping circuitry 52 maps these target brightness values to specific instructions for each pixel control circuit 20.

As an example, consider pixels 1 and 1' from Figure 10. Pixel mapping circuitry 52 may receive a target brightness value for pixel 1. The pixel mapping circuit may map this target brightness value to the pixel 1' controlled by the pixel control circuit 20-1. Then, when the mapped pixel data is used by the pixel control circuit 20-1 to operate the pixels, the pixel control circuit 20-1 provides outputs to operate the pixel 1' at the desired brightness. . However, due to the electrical layout of the passive matrices 30-1 and 30-2, pixel 1 will emit light at the desired brightness. This type of mapping can be performed for each pixel within the display as needed.

9 and 10, the pixel control circuitry of one neighboring pixel cell being used to control all remaining pixels within a given partial pixel cell is illustrative only. Generally, pixels within a partial pixel cell can be controlled by one or more pixel control circuits from neighboring pixel cells. Figure 12 is a diagram of a partial pixel cell controlled by multiple neighboring pixel control circuits.

Partial pixel cell 40-3 includes a first subset of pixels in area X2 and a second subset of pixels in area Y2, but does not have dedicated pixel control circuitry. The pixel cell 40-1 includes a pixel control circuit 20-1 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-1 is interrupted by border 42 and is therefore a partial pixel cell. Pixels, such as pixels X1, outside the target boundary will typically be driven by the pixel control circuit 20-1. However, pixels within area X1 are omitted from the display because they are outside border 42. Pixels in area X2 may be driven by an underutilized neighboring pixel control circuit 20-1.

The pixel cell 40-2 includes a pixel control circuit 20-2 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-2 is interrupted by border 42 and is therefore a partial pixel cell. Pixels, such as pixels Y1, outside the target boundary will typically be driven by pixel control circuit 20-2. However, pixels within area Y1 are omitted from the display because they are outside border 42. Pixels in area Y2 may be driven by an underutilized neighboring pixel control circuit 20-2.

Using this type of approach, a number of underutilized pixel control circuits are used to control the pixels within a single partial pixel cell 40-3. These examples are illustrative only. In general, any fractional pixel cell (sometimes referred to as a receptor) without dedicated pixel control circuitry receives pixel control from any desired number of neighboring pixel cells (sometimes referred to as donor pixel cells with donor pixel control circuits). Can be controlled by circuits.

So far, an example has been described where the target boundary for the display has rounded corners. Rounded corners may result in partial pixel cells using any of the driving techniques discussed with respect to FIGS. 8-12. However, other display layouts may also result in partial pixel cells using any of the driving techniques discussed with respect to FIGS. 8-12.

Figure 13A is a top view of a display with a light emitting active area (AA) having a footprint with rounded corners 54. The upper right corner of the display (as viewed from above) is shown in Figure 13A. However, if desired, all four corners of the active area can be rounded corners. Rounded corners 54 may result in partial pixel cells using any of the driving techniques discussed with respect to FIGS. 8-12. Additionally, a notch 56 is formed along the upper edge of the active area. Notch 56 may cause border 42 to have a curvature in one or more portions of region 58 that defines the notch. The presence of notch 56 may also result in partial pixel cells (e.g., within region 58) using any of the actuation techniques discussed with respect to FIGS. 8-12.

FIG. 13B is a top view of a display with a light emitting active area (AA) having an aperture (60). As an example, the aperture may be a physical hole within the display panel. The aperture is laterally surrounded by a luminescent active area (AA). Aperture 60 may result in partial pixel cells (e.g., adjacent the border of aperture 60) using any of the actuation techniques discussed with respect to FIGS. 8-12.

In general, a display having a footprint of any arbitrary shape (e.g., having a border with one or more curved portions and/or one or more linear portions) has a fractional pixel cell that does not have dedicated pixel control circuits. may result in When the display design results in partial pixel cells without dedicated pixel control circuits, any of the drive techniques discussed in conjunction with Figures 8-12 (regardless of the exact shape of the light-emitting active area) can be used.

In addition to providing modified pixel data to pixel control circuits 20 using pixel mapping circuitry 52, display driver circuitry 28 may perform black painting on omitted pixels in the display. Consider the example of Figure 10 in which some of the omitted pixels 22' in passive matrix 30-1 are mapped to physical pixels in passive matrix 30-2. Other omitted pixels 22'in passive matrix 30-1 (e.g., omitted pixels 22'outside area X1) are not mapped to any physical pixels within the display. Because there are no pixels at these locations, light cannot be emitted at these locations. Accordingly, in some arrangements these omitted pixels may not receive a target brightness level (and may correspondingly have a random target brightness level or dummy brightness level assigned during control operations). However, pixel control circuit 20-1 can still be configured to generate control signals for a full 8 x 8 passive matrix (even if some of the pixels in the passive matrix are physically omitted). When random and/or non-zero target brightness values are used for omitted pixels, pixels in the active area are Even if it is not intended to be turned on, it may turn on unwantedly.

To prevent unwanted light emissions from occurring, display driver circuitry 28 may assign a zero gray level to each omitted pixel within the display. A zero gray level may correspond to a physical light emitting diode that is turned off during operation (eg, when light is not emitted by the pixel and the pixel appears black). This process may be referred to as black painting. During black painting, each omitted pixel is assigned a zero gray level. Then, when corrected pixel data (with zero gray levels for omitted pixels) is provided to the pixel control circuits 20, unwanted light emission is mitigated. The black painting process may optionally be performed by pixel mapping circuitry 52.

It should be noted that the footprint of the active area of the display may be selected to reduce the number of fractional pixel cells within the display and/or the number of fractional pixel cells within the display without dedicated pixel control circuits. As an example, small modifications to the radius of curvature of the rounded corners of a display can result in a significant reduction in the number of acceptor pixel cells that require corresponding donor pixel cells. Similarly, small modifications to the total number of rows and columns within the active area can result in a significant reduction in the number of acceptor pixel cells that require corresponding donor pixel cells. In general, the size and shape of the active area of the display can be selected to optimize the number and arrangement of fractional pixel cells within the display, if desired. The position of the grid of pixel control circuits can also be centrally positioned (in both the

Various signal lines (eg, data signal lines, global signal lines, and power supply lines) may be included in the display to operate the pixel control circuits 20 and light emitting diodes 22. Figure 14 is a top view of an example display with fanout signal lines used to provide the necessary signals from the display driver circuitry to the signal lines for the display. As shown in FIG. 14 , the display may include a light emitting active area (AA) containing pixel control circuits 20 arranged in an array of rows and columns. As previously shown and discussed, each pixel control circuit controls one or more passive matrices of light emitting diodes.

As shown in FIG. 14, the display driver circuit 28 may be formed on the panel tail 24T. The panel tail 24T may be formed by an extension of the substrate 24. The extensions of substrate 24 may optionally be flexible/bendable. Panel tail 24T may be electrically connected to flexible printed circuitry or other components within electronic device 10. Display driver circuitry 28 may be formed on panel tail 24T, may be formed on flexible printed circuitry electrically connected to panel tail 24T, or may be formed at another desired location within device 10. It can be. In one example arrangement, panel tail 24T may be bent (e.g., bent 180 degrees) to electrically connect to a printed circuit board beneath display 14.

Display driver circuitry 28 may provide pixel control circuits 20 with various signals used to operate the array of light emitting diodes within display 14. However, the width of display driver circuitry 28 (and tail 24T) is less than the width of the active area of the display. Accordingly, a fanout signal line region 62 is included in the display to provide signals to all pixel control circuits as needed. Fanout signal lines within area 62 may be used to spread signals from display driver circuitry 28 to all areas of display 14 (e.g., the full width of the active area).

In the example of Figure 14, fan-out signal line area 62 is formed on panel 24T outside the light emitting active area AA. Figure 14 similarly shows how peripheral signal lines (eg, power supply lines) may be formed outside the active area in areas 64, 66, and 68. Area 64 extends along the right edge of the active area (outside the active area), area 66 extends along the top edge of the active area (outside the active area), and area 68 extends along the right edge of the active area (outside the active area). It extends along the left edge (outside the active area). The display can include any desired components, such as power supply lines, within these areas.

In Figure 14, areas 62, 64, 66, and 68 are all positioned outside the light emitting active area (AA) of the display. Accordingly, substrate 24 should have a non-emissive passive region large enough to accommodate regions 62, 64, 66, and 68. Alternatively, regions 62, 64, 66, and/or 68 may be positioned within the light emitting active area to reduce the size of the non-light emitting passive area.

Figure 15 is a top view of an example display with a fan-out signal line area within an active area of the display. As shown in Figure 15, fan-out signal line area 62 at least partially overlaps active area AA. Signal lines in the fan-out area 62 may be formed between and/or below the light emitting diodes in the active area AA, as shown in more detail in FIG. 16.

To increase the amount of fanout signal line area 62 that can be shifted into the active area (thereby reducing size requirements for the inactive area), pixel control circuits 20 are positioned within the active area. The gap between the edge of the active area and the pixel control circuits can be maximized. As shown in Figure 15, the row of pixel control circuits closest to the bottom edge of the active area (this is the edge adjacent to the display driver circuitry and therefore the fanout signal line area) is located between the pixel control circuits and the bottom edge of the active area. It is positioned with a gap (70) of Gap 70 may contain an entire row of light emitting diodes from a passive matrix controlled by a pixel control circuit. Consider the previous example where each pixel control circuit controls four 8 x 8 passive matrices of light emitting diodes. Accordingly, the gap 70 may be equal to the pitch of the eight light emitting diodes to ensure that eight rows of light emitting diodes are sandwiched between the pixel control circuits and the lower edge of the active area. This ensures that the bottom row of pixel control circuits can still fully control all light emitting diodes along the bottom edge of the active area while also maximizing the space within the active area to accommodate the fanout signal line area 62. .

In addition to forming a fanout signal line region 62 at least partially in the active region, one or more peripheral signal lines (e.g., power supply lines) may be formed within the active region in regions 64, 66, and 68. You can. 15, region 64 extends along the right edge of the active area (inside the active region), region 66 extends along the top edge of the active region (inside the active region), and region 68 extends along the left edge of the active area (inside the active area). The display can include any desired components, such as power supply lines, within these areas.

Additionally, one or more peripheral signal lines (eg, power supply lines) may be formed within the active area within the rounded corners of the display. Figure 15 shows rounded corner areas 80-1, 80-2, 80-3, and 80-4. In Figure 15, area 80-1 extends along the lower left corner of the active area (inside the active area) between areas 68 and 62, and area 80-2 extends between areas 64 and 62. ), and region 80-3 extends along the upper left corner of the active region (inside the active region) between regions 68 and 66. Extended, region 80-4 extends along the upper right corner of the active region (inside the active region) between regions 66 and 64. The display can include any desired components, such as power supply lines, within these areas.

Figure 16 is a cross-sectional side view of an example display with a fan-out signal line area 62 at least partially overlapping the display active area. 16 shows pixel control circuit 20 mounted on substrate 24. As an example, pixel control circuitry 20 may be attached to substrate 24 using a layer of adhesive. A common adhesive layer may attach multiple pixel control circuits to substrate 24. Additional dielectric layers 72-0, 72-1, 72-2, 72-3, 72-4, 72-5, and 72-6 are formed on substrate 24 and may optionally be referred to as substrate layers. You can. A plurality of metal layers including metal layers M0, M1, M2, M3, and M4 are also formed on the substrate between the dielectric layers. Various vias 74 may be included to electrically connect the different metal layers within the display.

Specifically, dielectric layer 72-0 is formed on substrate 24 (coplanar with pixel control circuit 20). Dielectric layer 72-0 may be referred to as a planarization layer. The metal layer M0 is formed on the dielectric layer 72-0. The dielectric layer 72-1 is formed on the metal layer M0. Metal layer M1 is formed on dielectric layer 72-1. The dielectric layer 72-2 is formed on the metal layer M1. Metal layer M2 is formed on dielectric layer 72-2. The dielectric layer 72-3 is formed on the metal layer M2. Metal layer M3 is formed on dielectric layer 72-3. The dielectric layer 72-4 is formed on the metal layer M3. A metal layer M4 is formed on the dielectric layer 72-4. The dielectric layer 72-5 is formed on the metal layer M4.

In the active area AA, the metal layer M4 may form anode contacts A for the passive matrices of light emitting diodes controlled by the pixel control circuits 20. Light-emitting diodes 22 are formed between anode contacts A and corresponding cathode contacts C. A planarization layer 72-6 may be formed on the cathode contacts C.

In signal fan-out region 62, metal layers M0 and M1 may be patterned to form fan-out signal lines for conveying power and analog signals. For example, metal layers M0 and M1 may include positive power supply lines and negative power supply lines. In signal fanout region 62, metal layers M2 and M3 may be patterned to form global signal lines for the display. Global signal lines may be used to convey clock signals to pixel control circuits, as an example. In signal fanout area 62, metal layer M4 may be patterned to form data signal lines for the display. The data signal lines may be used to carry display data that is used by pixel control circuits to operate the light emitting diodes at target brightness values (and thus display the target image). Signal lines formed using the metal layer M4 may be digital signal lines that transmit digital signals.

A metal layer (M4) is used to form anode contacts (A) in the active region. Accordingly, the metal layer M4 is simply patterned to form fan-out lines outside the light emitting active area AA. The fan-out signal lines formed using the metal layer M4 do not overlap the light emitting active area. In contrast, metal layers M2 and M3 are patterned to form fan-out lines in both the active and non-active areas of the display. Similarly, metal layers M0 and M1 are patterned to form fan-out lines in both the active and non-active areas of the display.

Fanout signal lines within region 62 may be electrically connected to additional signal lines in the active area of the display carrying signals throughout the display (e.g., to pixel control circuits). The fanout signal lines may be electrically connected to signal lines that are patterned using the same metal layer as in the fanout area, or to signal lines that are patterned using a different metal layer than in the fanout area ( and electrically connected using one or more biases).

Figure 17 is a top view of an example display with peripheral signal lines formed inside the active area. As shown in Figure 17, signal lines, such as power supply lines 76, are connected to pixel control circuits 20 (e.g., the rightmost row of pixel control circuits extending in the Y-direction) and the right edge of the active area. It may be formed along the edge of the active area inside the active area in the area 64 therebetween. Additional signal lines, such as global signal lines 78, may be formed along the edges of the active area within the active area in area 64. In this example pixel control circuitry 20 (e.g., rightmost row of pixel control circuits extending in the Y-direction) is sandwiched between global signal lines 78 and power supply lines 76. Generally, the signal lines are in region 64 (as shown in FIG. 17), in region 66, in region 68, in region 80-1, in region 80-2, At 80-3, and/or at area 80-4, it may be included at the edge of the active area.

To maximize the amount of space along the left and right edges of the active area to accommodate signal lines, such as power supply lines, the array of pixel control circuits may be centered relative to the left and right edges of the active area. there is. This provides an equal amount of space on both the left and right edges of the active area to accommodate the signal lines.

The examples of panel tails 24T (with corresponding fanout signal line areas 62) formed along the bottom edge of the display in FIGS. 14 and 15 are illustrative only. In general, the panel tail and display driver circuitry can be formed along any desired edge(s) of the display. Regardless of the position of the display driver circuitry and panel tail, a fanout signal line region may be included adjacent to the display driver circuitry and panel tail, and other edges of the display may include peripheral signal lines.

As previously shown in connection with FIGS. 7-9 , target boundary 42 may intersect through some of the pixel cells 40 . This causes some of the pixel cells to become partial pixel cells. Pixels outside of border 42 within pixel cell 40-2 may be omitted from the display. Additionally, pixel control circuits outside the target boundary may be omitted from the display. To alleviate these problems, additional pixel control circuits can be included to control the partial pixel cells (as in Figure 8), or the pixel driver circuit of a neighboring partial pixel cell can be used to drive the pixels of the partial pixel cell. There is (as in Figure 9).

Instead of or in addition to using the techniques of FIGS. 8 and/or 9, the first pixel row may be selectively shifted relative to the first row of pixel control circuits, if desired. FIG. 18A is a top view of an example display in which the first row of pixels within the display active area are aligned with the top of the pixel cells controlled by the first row of pixel control circuits 20. The number of pixel rows within distance 102 in Figure 18A is equal to half the total number of pixel rows within each cell 40.

Consider an example where each pixel control circuit controls four 8 x 8 passive matrices, for a total of 16 rows and 16 columns of pixels. In this case, distance 102 in Figure 18A is 8 rows of pixels. Accordingly, the first row of pixel control circuits does not have partial pixel cells outside the rounded corner areas. The top of the control area of the first (top) row of pixel control circuits is aligned with the top row of pixels in the active area.

In contrast, in FIG. 18B, the first row of pixels within the display active area are not aligned with the top of the pixel cells controlled by the first row of pixel control circuits 20. The number of pixel rows within distance 104 in Figure 18A is less than half the total number of pixel rows within each cell 40.

Consider an example where each pixel control circuit controls four 8 x 8 passive matrices, for a total of 16 rows and 16 columns of pixels. In this case, distance 104 in Figure 18A is 6 rows (eg, 7 or fewer) of pixels. Accordingly, the first row of pixel control circuits has partial pixel cells within both of the rounded corner areas and along the entire top edge of the active area (outside the rounded corner areas). The top of the control area of the first row of pixel control circuits is shifted relative to the top row of pixels in the active area.

Adjusting the position of the active area relative to the pixel control circuits (as in Figure 18b) can reduce the overall number of pixels (within partial pixel cells in the rounded corner area) that require mapping (and thus Figures 8 and /or reduce the need for the solutions of Figure 9).

During manufacturing, pixel control circuits can be transferred by a mass transfer array (MTA) from several individual stamps to form pixel control circuits for the entire display. Individual stamps of pixel control circuits can be manufactured separately and then combined to form a single integrated array of pixel control circuits. In the example of FIG. 19 , six different stamps (labeled 1, 2, 3, 4, 5, and 6) form the pixel control circuits for display 14. The size and overlap of each stamp can be chosen to mitigate the overall number of pixels (within partial pixel cells within rounded corner regions) that require mapping.

As shown in FIG. 19 , a vertical offset 106 (e.g., for topmost stamps 1 and 2) and/or a horizontal offset 108 (e.g., for rightmost stamps 2, 4, and 6) ) can be used to optimize the number of pixels that require mapping. This may result in a horizontal pitch 110 that, for most of the pixel control circuits, is less than the pitch 112 between pixel control circuits of different adjacent stamps (e.g., between stamps 1 and 2 in FIG. 19). . Similarly, the total vertical pitch 114, for most of the pixel control circuits, is less than the pitch 116 between pixel control circuits of different adjacent stamps (e.g., between stamps 1 and 3 in FIG. 19). It can be small.

According to one embodiment, there is display driver circuitry, an array of light emitting diodes arranged in rows and columns and an array of control circuits, each of which controls at least one passive matrix of light emitting diodes based on signals from the display driver circuitry. configured to control, wherein the first control circuit provides signals to the plurality of anode contacts, each anode contact of the plurality of anode contacts overlaps the plurality of light emitting diodes in each single row, and the second control circuit provides signals to the plurality of anode contacts. provides a signal to a first anode contact overlapping the at least one light emitting diode in the first row, and the first anode contact provides an electrical signal to a second anode contact overlapping the at least one light emitting diode in a second row different from the first row. An electronic device is provided, comprising:

According to another embodiment, the array of control circuits is interspersed with an array of light emitting diodes.

According to another embodiment, the first control circuit provides signals to a plurality of cathode contacts, each cathode contact of the plurality of cathode contacts overlapping a plurality of light emitting diodes in each single row, and a plurality of anodes. The contacts and the plurality of anode contacts are orthogonal, and each light emitting diode is positioned at an overlap point between the plurality of anode contacts and the plurality of anode contacts.

According to another embodiment, the first control circuit provides controls of a first passive matrix of light emitting diodes arranged in a first number of rows and a second number of columns.

According to another embodiment, the first control circuit provides controls of a second passive matrix of light emitting diodes arranged in a third number of rows and a fourth number of columns, the third number being different from the first number.

According to another embodiment, the first control circuit provides controls of a second passive matrix of light emitting diodes arranged in a third number of rows and a fourth number of columns, the fourth number being different from the second number.

According to another embodiment, the second control circuit provides a signal to a third anode contact overlapping at least one light emitting diode in the third row, the third anode contact being a fourth anode contact in a fourth row different from the third row. is electrically connected to

According to another embodiment, the first and second anode contacts overlap different numbers of light emitting diodes.

According to another embodiment, the third and fourth anode contacts overlap different numbers of light emitting diodes.

According to another embodiment, the first anode contact is electrically connected to the second anode contact by an interconnect routing line extending down at least some of the light emitting diodes in the array of light emitting diodes.

According to another embodiment, the third control circuit provides a signal to a third anode contact overlapping at least one light emitting diode in the third row, the third anode contact being a fourth anode contact in a fourth row different from the third row. is electrically connected to, and the second and fourth rows are adjacent.

According to one embodiment, a display driver circuitry, an array of light emitting diodes arranged in rows and columns in a light emitting area and an array of control circuits, each of which controls at least one of the light emitting diodes based on signals from the display driver circuitry. configured to control the passive matrix, the first control circuit having outputs configured to control pixel brightness values at a grid of positions including positions outside the light-emitting area, and the display driver circuitry at positions outside the light-emitting area. An electronic device is provided, comprising: configured to set pixel brightness values of to a zero gray level.

According to another embodiment, the passive matrix controlled by the first control circuit includes a plurality of anode contacts, and a plurality of cathode contacts extending orthogonal to the plurality of cathode contacts, wherein the plurality of anode contacts are connected to the first number. A first anode contact overlapping with a number of light emitting diodes and a second anode contact overlapping with a second number of light emitting diodes less than the first number.

According to another embodiment, the array of control circuits has a first row of control circuits, each control circuit in the first row of control circuits having a pixel brightness value at a grid of positions including positions outside the light emitting area. The first row of rows in the light emitting area is shifted relative to the upper edge of the grid of positions of the first row of control circuits.

According to another embodiment, an array of control circuits is formed on a plurality of individual stamps including first, second, and third stamps, wherein the first and second control circuits on the first stamp have a first horizontal pitch. and the third and fourth control circuits on the first and second stamps are each separated by a second horizontal pitch that is less than the first horizontal pitch, and the fifth and sixth control circuits on the first stamp are respectively separated by a second horizontal pitch that is smaller than the first horizontal pitch. separated by a vertical pitch, and the seventh and eighth control circuits on the first and third stamps are each separated by a second vertical pitch that is less than the first vertical pitch.

According to one embodiment, display driver circuitry, an array of light emitting diodes arranged in a light emitting area, and an array of control circuits, each of the control circuits controlling at least one passive matrix of light emitting diodes based on signals from the display driver circuitry. An electronic device is provided, including fanout signal lines coupled to the display driver circuitry and receiving signals from the display driver circuitry, the fanout signal lines at least partially overlapping the light emitting area.

According to another embodiment, the fanout signal lines include a first patterned metal layer, a second patterned metal layer formed on the first patterned metal layer, and a third pattern formed on the second patterned metal layer. a first and second patterned metal layer comprising a patterned metal layer, a fourth patterned metal layer formed on the third patterned metal layer, and a fifth patterned metal layer formed on the fourth patterned metal layer; Fanout signal lines formed from the patterned metal layers carry power supply signals, fanout signal lines formed from the third and fourth patterned metal layers carry global signals, and fanout signal lines formed from the third and fourth patterned metal layers carry global signals and from the fifth patterned metal layer. The fanout signal lines formed carry data signals, the fifth patterned metal layer having portions forming anode contacts for the passive matrices of light emitting diodes, and the fan formed from the first and second patterned metal layers. The out signal lines at least partially overlap the light-emitting area, and the fan-out signal lines formed from the third and fourth patterned metal layers at least partially overlap the light-emitting area, and the fan-out signal lines formed from the fifth patterned metal layer. The signal lines do not overlap the light emitting area.

According to one embodiment, a display driver circuitry, an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges, an array of control circuits arranged in rows and columns - the control circuits respectively. configured to control the at least one passive matrix of light emitting diodes based on signals from the display driver circuitry, and fanout signal lines coupled to the display driver circuitry and receiving signals from the display driver circuitry—fanout signal lines. formed between a row of control circuits and a first edge of an array of light emitting diodes.

According to another embodiment, each passive matrix includes a given number of rows of light emitting diodes, the given number of rows of light emitting diodes interposed between the row of control circuits and a first edge of the array of light emitting diodes.

According to one embodiment, a display driver circuitry, an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges, an array of control circuits arranged in rows and columns - the control circuits respectively. is configured to control the at least one passive matrix of light emitting diodes based on signals from the display driver circuitry, the array of control circuits being centered relative to the third and fourth opposing edges - and at least the third An electronic device is provided comprising power supply lines extending along an edge, the power supply lines being overlapped by an array of light emitting diodes.

The foregoing is merely illustrative, and various modifications may be made by those skilled in the art without departing from the scope and technical spirit of the described embodiments. The above-described embodiments can be implemented individually or in any combination.

Claims (20)

As an electronic device,
display driver circuitry;
an array of light emitting diodes arranged in rows and columns; and
an array of control circuits, each of the control circuits configured to control at least one passive matrix of light emitting diodes based on signals from the display driver circuitry, wherein a first control circuit sends signals to a plurality of anode contacts; Provided, each anode contact of the plurality of anode contacts overlaps a plurality of light emitting diodes in each single row, and the second control circuit includes a first anode contact overlapping with at least one light emitting diode in the first row. and providing a signal to the first anode contact, wherein the first anode contact is electrically connected to a second anode contact overlapping at least one light emitting diode in a second row different from the first row. The electronic device of claim 1, wherein the array of control circuits is interspersed with the array of light emitting diodes. 2. The method of claim 1, wherein the first control circuit provides signals to a plurality of cathode contacts, each cathode contact of the plurality of cathode contacts overlapping a plurality of light emitting diodes in each single row, An electronic device, wherein a plurality of anode contacts and the plurality of anode contacts are orthogonal, and each light emitting diode is positioned at an overlap between the plurality of anode contacts and the plurality of anode contacts. The electronic device of claim 1, wherein the first control circuit provides controls of a first passive matrix of light emitting diodes arranged in a first number of rows and a second number of columns. 5. The method of claim 4, wherein the first control circuit provides controls of a second passive matrix of light emitting diodes arranged in a third number of rows and a fourth number of columns, the third number being different from the first number. , electronic devices. 5. The method of claim 4, wherein the first control circuit provides controls of a second passive matrix of light emitting diodes arranged in a third number of rows and a fourth number of columns, the fourth number being different from the second number. , electronic devices. 2. The method of claim 1, wherein the second control circuit provides a signal to a third anode contact overlapping at least one light emitting diode in a third row, and the third anode contact is connected to a third anode contact in a fourth row different from the third row. 4 An electronic device electrically connected to an anode contact. 8. The electronic device of claim 7, wherein the first and second anode contacts overlap different numbers of light emitting diodes. 8. The electronic device of claim 7, wherein the third and fourth anode contacts overlap different numbers of light emitting diodes. The electronic device of claim 1, wherein the first anode contact is electrically connected to the second anode contact by an interconnect routing line extending below at least some of the light emitting diodes in the array of light emitting diodes. 2. The method of claim 1, wherein the third control circuit provides a signal to a third anode contact overlapping at least one light emitting diode in the third row, and the third anode contact is connected to a fourth anode contact in a fourth row different from the third row. electrically connected to an anode contact, wherein the second and fourth rows are adjacent. As an electronic device,
display driver circuitry;
an array of light emitting diodes arranged in rows and columns in the light emitting area; and
an array of control circuits, each of the control circuits configured to control at least one passive matrix of light emitting diodes based on signals from the display driver circuitry, wherein a first control circuit controls positions outside the light emitting area outputs configured to control pixel brightness values in a grid of locations comprising, wherein the display driver circuitry is configured to set the pixel brightness values at locations outside the emitting area to a zero gray level. Electronic devices. 13. The method of claim 12, wherein the passive matrix controlled by the first control circuit includes a plurality of anode contacts, and the plurality of cathode contacts extending orthogonally to the plurality of cathode contacts, wherein the plurality of anode contacts The electronic device includes a first anode contact overlapping a first number of light emitting diodes and a second anode contact overlapping a second number of light emitting diodes less than the first number. 13. The method of claim 12, wherein the array of control circuits has a first row of control circuits, each control circuit in the first row of control circuits having a position in a grid of positions including positions outside the light emitting area. An electronic device with outputs configured to control pixel brightness values, wherein a first of the rows in the light-emitting area is shifted relative to an upper edge of the grid of positions of the first row of control circuits. 13. The method of claim 12, wherein the array of control circuits is formed on a plurality of individual stamps including first, second, and third stamps, and wherein the first and second control circuits on the first stamp are the first stamps. separated by a horizontal pitch, the third and fourth control circuits on the first and second stamps are each separated by a second horizontal pitch less than the first horizontal pitch, and the fifth and fourth control circuits on the first stamp are each separated by a second horizontal pitch less than the first horizontal pitch. 6 control circuits are separated by a first vertical pitch, and 7th and 8th control circuits on the first and third stamps are each separated by a second vertical pitch that is less than the first vertical pitch. As an electronic device,
display driver circuitry;
An array of light emitting diodes arranged in a light emitting area;
an array of control circuits, each of the control circuits configured to control at least one passive matrix of light emitting diodes based on signals from the display driver circuitry; and
The electronic device comprising fanout signal lines coupled to the display driver circuitry and receiving the signals from the display driver circuitry, the fanout signal lines at least partially overlapping the light emitting area. 17. The method of claim 16, wherein the fanout signal lines are formed on a first patterned metal layer, a second patterned metal layer formed on the first patterned metal layer, and a second patterned metal layer formed on the second patterned metal layer. a third patterned metal layer, a fourth patterned metal layer formed on the third patterned metal layer, and a fifth patterned metal layer formed on the fourth patterned metal layer, Fan-out signal lines formed from the first and second patterned metal layers carry power supply signals, fan-out signal lines formed from the third and fourth patterned metal layers carry global signals, and Fanout signal lines formed from a fifth patterned metal layer carry data signals, the fifth patterned metal layer having portions forming anode contacts to the passive matrices of light emitting diodes, The fan-out signal lines formed from the first and second patterned metal layers at least partially overlap the light-emitting area, and the fan-out signal lines formed from the third and fourth patterned metal layers overlap the light-emitting area. and wherein the fanout signal lines formed from the fifth patterned metal layer do not overlap the light emitting area. As an electronic device,
display driver circuitry;
an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges;
an array of control circuits arranged in rows and columns, each of the control circuits configured to control at least one passive matrix of light emitting diodes based on signals from the display driver circuitry; and
fanout signal lines coupled to the display driver circuitry and receiving the signals from the display driver circuitry, the fanout signal lines being formed between a row of control circuits and the first edge of the array of light emitting diodes. An electronic device that does. 19. The method of claim 18, wherein each passive matrix includes a given number of rows of light emitting diodes, the given number of rows of light emitting diodes interposed between the row of control circuits and the first edge of the array of light emitting diodes. An interposed electronic device. As an electronic device,
display driver circuitry;
an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges;
an array of control circuits arranged in rows and columns, each of the control circuits being configured to control at least one passive matrix of light emitting diodes based on signals from the display driver circuitry, the array of control circuits being configured to: centered relative to the third and fourth opposing edges -; and
An electronic device comprising power supply lines extending at least along the third edge, the power supply lines being overlapped by the array of light emitting diodes.