KR20230001275A - Variable resistance memory device including a plurality of stacked memory cells - Google Patents

Abstract

The present invention relates to a variable resistance memory device. In accordance with the present embodiment, the variable resistance memory device includes: a bank layer located in an upper part of a semiconductor substrate, and comprising a plurality of mats including a plurality of stacked memory cells; and a control circuit layer located between the semiconductor substrate and the bank layer, and including a plurality of control circuit areas partitioned in a shape corresponding to the plurality of mats. The plurality of stacked memory cells includes a plurality of stacked word lines, and a plurality of stacked bit lines cross-arranged between the plurality of stacked word lines. A word line selection unit formed to control the plurality of stacked word lines is placed in some of the plurality of control circuit areas, and a bit line selection part formed to control the plurality of bit lines can be placed in the rest thereof. A control circuit area in which the word line selection unit is placed and a control circuit area in which the bit line selection unit is placed can be repetitively arranged by turns with each other.

Description

Resistance variable memory device including a plurality of stacked memory cells

The present invention relates to a resistance change memory device, and more particularly, to a resistance change memory device including a plurality of stacked memory cells.

In accordance with demands for high-capacity and low-power memory devices, research on next-generation memory devices that are non-volatile and do not require periodic refresh is being conducted. As such a next-generation memory device, phase changeable RAM (PCRAM), nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (ReRAM) small, etc.

Among next-generation memory devices, a PCRAM is currently formed in a cross-point array structure by including a storage element at an intersection of a word line and a bit line. Such a cross point array structure may have an advantage of being able to stack a memory cell array of a second layer or more.

Embodiments of the present invention provide a resistance variable memory device capable of stacking memory cells without limiting the number of stacking memory cells.

A resistance variable memory device according to an embodiment of the present invention is located on a semiconductor substrate, and is located between a bank layer composed of a plurality of mats including a plurality of stacked memory cells, and located between the semiconductor substrate and the bank layer. , a control circuit layer including a plurality of control circuit regions partitioned in a form corresponding to the plurality of mats. The plurality of stacked memory cells include a plurality of stacked word lines and a plurality of stacked bit lines intersecting between the plurality of stacked word lines. A word line selector configured to control the plurality of stacked word lines is disposed in a portion of the plurality of control circuit regions, and a bit line selector configured to control the plurality of bit lines is disposed in the remaining portion, and the word line selector is configured to control the plurality of bit lines. The control circuit area where the selector is disposed and the control circuit area where the bit line selector is disposed are alternately and repeatedly arranged.

Each of the plurality of mats is limited to a plurality of row areas and a plurality of column areas crossing the rows, and the plurality of stacked word lines extend for each row, and one The plurality of stacked bit lines extend for each column, and the plurality of stacked word lines are separated by a length unit equal to a length between a pair of word line selectors disposed adjacently along the row direction to stack a plurality of word lines structure, and the plurality of stacked bit lines may be separated by a unit of length between a pair of bit line selectors disposed adjacently along the column direction to be defined as a plurality of bit line stacked structures.

The word line selector may include a word line select switch provided for each row region of the control circuit region where the word line selector is located. The word line select switch is simultaneously connected to the word line stack structure disposed on both sides of the switch, and the word line select switch is connected to odd-numbered (or even-numbered) word lines of the word line stack structure on one side and the other side of the word line select switch. Even-numbered (or odd-numbered) word lines of the word line stack structure may be simultaneously connected.

The bit line stack structure is configured so that one selected from one end and the other end of a lowermost bit line among the stacked bit lines is electrically connected to the bit line selector positioned thereunder.

In the bit line stacked structures as many as the number of stacked bit lines continuously arranged in the column direction, the bit lines positioned on different layers are connected to each other.

A resistance variable memory device according to an embodiment of the present invention includes a control circuit layer including a plurality of control circuit regions divided in a matrix form along first and second directions intersecting each other on a semiconductor substrate; and the control circuit layer. A resistance variable memory device including a bank layer disposed thereon and including a plurality of memory cells, the plurality of memory cells comprising: a plurality of first electrode lines and a plurality of first electrode lines arranged to cross the plurality of first electrode lines; It includes two electrode lines, and a resistance layer respectively positioned at an intersection of the plurality of first electrode lines and the plurality of second electrode lines. The plurality of control circuit regions include a plurality of first control circuit regions in which a first electrode line selector for selecting the first electrode line is disposed, and a second electrode line selector for selecting the plurality of second electrode lines. It includes second control circuit regions. The first control circuit area and the second control circuit area are alternately disposed along the first and second directions.

In the first electrode line stack structure and the second electrode line stack structure, when the memory cell is selected, the first electrode line stack structure includes at least one of the first electrodes that do not face each other with the second electrode line interposed therebetween. A first voltage is applied to a line, and the second electrode line stack structure is configured such that a second voltage having a difference between the first voltage and a threshold voltage is applied to a selected one of a plurality of stacked second electrode lines. .

In addition, a resistance variable memory device according to an embodiment of the present invention includes a plurality of word line stack structures formed by stacking n word lines along each row, and n−1 number of word lines along a column crossing each row. a plurality of bit line stack structures in which bit lines are stacked, word line select switches respectively disposed in lower regions of both end portions of the word line stack structure; and bit line select switches respectively disposed in lower regions of both ends of the bit line stack structure. When a selected one of the word line select switches is enabled, a first voltage may be applied to at least one word line among the word line stacked structures connected to the enabled word line select switch. When a selected one of the bit line select switches is enabled, a total of n-1 bit line stacks sequentially arranged in the column direction including the bit line stack structure connected to the enabled bit line select switch. A second voltage having a difference between the first voltage and a threshold voltage may be provided to selected bit lines of the structure.

The n−1 bit line stacked structures connected to the enabled bit line select switch may be sequentially connected from the lowest bit line to the bit lines of the n−1 layer in a stepwise manner.

A resistance layer may be provided at each intersection of the word line stack structure and the bit line stack structure to define memory cells.

A control circuit area where the word line select switches are formed and a control circuit area where the bit line select switches are formed may be alternately arranged along the row direction and the column direction.

In a bank including stacked memory cells, word line selection units and bit line selection units are alternately arranged for each mat. In addition, the word line stack structure prevents word lines stacked adjacent to each other from being selected at the same time, while bit lines of the bit line structure disposed adjacent to each other are connected in a stepwise manner with bit lines of different levels, Only one memory cell can be effectively selected.

Accordingly, even when word lines and bit lines of four or more layers are stacked, one memory cell can be effectively selected. Furthermore, the integration density of the resistance variable memory device may be improved.

1 is a block diagram showing a semiconductor system according to an exemplary embodiment of the present invention.
2 is a perspective view schematically illustrating a resistance variable memory device according to an exemplary embodiment.
3 is a plan view of a bank according to an embodiment of the present invention.
4 is a plan view of a control circuit layer according to an embodiment of the present invention.
5 is a view schematically showing a mat according to an embodiment of the present invention.
6A and 6B are equivalent circuit diagrams of a memory cell according to an embodiment of the present invention.
is a circuit diagram for explaining a principle of selecting a memory cell according to an exemplary embodiment of the present invention.
7 is a schematic diagram for explaining the relationship between word lines and bit lines implementing six decks according to an embodiment of the present invention.
8A and 8B are schematic circuit diagrams for explaining the relationship between word lines and bit lines implementing six decks according to an embodiment of the present invention.
9 is a diagram schematically illustrating a connection relationship between word lines arranged on a plurality of mats and word line selectors arranged in a control circuit area according to an embodiment of the present invention.
10 is an equivalent circuit diagram of part “C” of FIG. 9 .
11 is a cross-sectional view of a main part of a resistance variable memory device cut in a direction parallel to a word line according to an exemplary embodiment of the present invention.
12 is a diagram schematically illustrating a connection relationship between bit lines arranged on a plurality of mats and a bit line selection unit arranged in a control circuit area according to an embodiment of the present invention.
FIG. 13 is an equivalent circuit diagram of part “E” in FIG. 12 .
14 is a main cross-sectional view of a resistance variable memory device cut in a direction parallel to a bit line according to an exemplary embodiment of the present invention.
15 is a cross-sectional view of a resistance variable memory device cut along a bit line direction according to another embodiment of the present invention.
16 is a diagram for explaining a process of selecting memory cells of a specific mat according to an embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of explanation. Like reference numbers designate like elements throughout the specification.

1 is a block diagram showing a semiconductor system according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a semiconductor system 10 may include a processor 1000 , a controller 1100 and a memory device 100 .

Processor 1000 may be interfaced with controller 1100 by bus 1110 . The processor 1000 may provide a memory access request (such as a read request or a write request: not shown) including memory addresses and data to the controller 1100 . Also, the processor 1000 may receive read data from the controller 1100 .

The controller 1100 transmits commands (CMD, eg, read commands and write commands), addresses (ADD), data (DATA), and control commands (CTRL) for memory operations of the memory device 100 to the memory device 100. ) can be provided. Signals output from the controller 1100 may be generated through the requests provided from the processor 1000 .

The memory device 100 may include, for example, a non-volatile memory device. In this embodiment, the memory device 100 will be described as an example of a resistance change memory device. However, it is not limited thereto.

2 is a perspective view schematically illustrating a resistance variable memory device according to an exemplary embodiment. 3 is a plan view of a bank according to an embodiment of the present invention.

Referring to FIG. 2 , the memory device 100 may include a semiconductor substrate 110, a control circuit layer 120, and a bank layer BA.

The semiconductor substrate 110 may include a semiconductor material such as a silicon substrate or gallium arsenide. However, it is not limited thereto, and a silicon on insulator (SOI) substrate and various compound semiconductor substrates may be used here.

A control circuit layer 120 may be formed on the semiconductor substrate 110 . The control circuit layer 120 may include circuits that control the operation of the bank layer BA. The control circuit layer 120 may generate various control signals capable of driving memory cells constituting the bank layer BA by using commands received from the controller 1100 . The control circuit layer 120 may include various circuits such as, for example, a word line selector, a bit line selector, a voltage generator circuit, and a sense amplifier.

The bank layer BA may include a plurality of banks. In this figure, the bank layer BA shows some of a plurality of banks. As shown in FIG. 3, each of the banks may be divided into a plurality of mats arranged in a matrix form. The mat MAT may include a plurality of word lines and a plurality of bit lines that generally extend without interruption. A generic mat like this has been interpreted as a group of memories controlled by a group of control circuits. However, in current memory devices, word lines (word lines extended without interruption) and bit lines (bit lines extended without interruption) may be extended in units of at least one, for example, two mats, for control efficiency. The word line and the bit line of this embodiment will be described as an example in which they occupy three mats, but have lengths corresponding to the width (or length) of two mat units.

In addition, each of the mats (MAT) of the present embodiment may include a plurality of memory cells by further including a resistive layer at each intersection between the plurality of word lines and the plurality of bit lines. The mat (MAT) of this embodiment may be configured in a form in which the plurality of memory cells are stacked. In this embodiment, memory cells of one layer (or one level) may be referred to as a deck (deck: D), and a MAT or bank layer of this embodiment is a plurality of decks of at least four layers, for example Six layers of decks D1 to D6 may be included. In order to form the plurality of decks D1 to D6 as described above, the word lines and bit lines may be alternately stacked along rows and columns.

In some cases, the mat (MAT) may also be called a tile (tile). As another example, U.S. Patent Application filed on September 25, 2019 by the inventor of the present invention. Application No. 16/582,861 and filed on November 2, 2020, U.S. As described in Application No. 17/087,080, the tile may correspond to a part of a mat, that is, a sub-mat. The U.S. Application No. 16/582,861 and filed on November 2, 2020, U.S. Application Ser. No. 17/087,080 in its entirety is incorporated herein by reference.

4 is a plan view of a control circuit layer according to an embodiment of the present invention.

Referring to FIG. 4 , the control circuit layer 120 may be positioned below the bank layer BA, as described above. The control circuit layer 120 may be divided into a plurality of control circuit regions 120-01 to 120-xy to correspond to respective mats MAT01 to MATxy. As an example, a first mat MAT1 may be positioned above the first control circuit area 120-01.

In general, each of the control circuit regions 120-01 to 120-xy may include various circuits such as a word line selector, a bit line selector, a voltage generator circuit, and a sense amplifier, but in this embodiment and the drawings, description For convenience, only the word line selector WLSW and the bit line selector BLSW for selecting a memory cell will be described. In this embodiment, the word line selector WLSW and the bit line selector BLSW may be understood as a word line select switch array (or row switch array) and a bit line select switch array (or column switch array). will be.

In each of the control circuit regions 120-01 to 120-xy, for example, one selected from among a word line selector WLSW and a bit line selector BLSW may be located. The word line selector WLSW of this embodiment may be interpreted as a word line decoder or word line decoder, and the bit line selector BLSW may be interpreted as a bit line decoder or bit line decoder.

As an example, when the word line selector WLSW is disposed in the twelfth control circuit area 120-12, the second, eleventh, thirteenth and A bit line selector BLSW may be disposed in the twenty-second control circuit regions 120-02, 120-11, 120-13, and 120-22. On the other hand, when the bit line selector BLSW is disposed in the thirteenth control circuit area 120-13, the third, twelfth, fourteenth, and twenty-third A word line selector WLSW may be disposed in the control circuit regions 120-03, 120-12, 120-14, and 120-23.

That is, the word line selector WLSW and the bit line selector BLSW may be alternately arranged in the control circuit regions 120-01 to 120-xy arranged in the x and y directions of the drawing.

Also, the word line selector WLSW may include word line select switches formed for each row constituting the mat MAT. The row may represent an area where word lines are arranged. In addition, in the present embodiment, word lines extending along rows of the bank layer BA may be interpreted as a structure in which a plurality of word lines are stacked, and they are separated based on the word line selector WLSW, It may be called a word line stack structure, a unit word line stack structure, or an individual word line stack structure. Accordingly, a unit word line stack structure may have a length equal to between a pair of adjacent word line selectors in the row direction.

Similarly, the bit line selector BLSW may include a bit line select switch formed for each column. In this embodiment, the column may be an area where the bit line is arranged. In the present embodiment, a bit line extending along a column of the bank layer BA may be interpreted as a plurality of stacked bit lines, and the plurality of stacked bit lines correspond to the bit line selector BLSW ), it may be referred to as a bit line stack structure, a unit bit line stack structure, or an individual bit line stack structure.

5 is a plan view schematically showing a mat according to an embodiment of the present invention.

Referring to FIG. 5 , the mat MAT may include a plurality of word lines WL1 to WL4 and a plurality of bit lines BL1 to BL4. The plurality of word lines WL1 to WL4 and the plurality of bit lines BL1 to BL4 may be arranged to cross each other. Memory cells MC are formed at intersections of the plurality of word lines WL1 to WL4 and the plurality of bit lines BL1 to BL4, respectively. The memory cell MC may include a word line WL, a bit line BL, and a resistive layer (not shown) positioned therebetween. In this embodiment, 4 word lines and 4 bit lines are shown for convenience of drawing, but hundreds of word lines and hundreds of bit lines may be extended in one MAT.

The plurality of word lines WL1 to WL4 may be arranged in parallel at regular intervals along the x direction of the drawing, and the plurality of bit lines BL1 to BL4 may be arranged at regular intervals along the y direction of the drawing. can be arranged in parallel with

As will be described in detail in later drawings, in order to form a stacked deck D in the mat of the present embodiment, a plurality of word lines WL1 to WL4 and a plurality of bit lines BL1 to BL4 are alternately stacked with each other. can be placed. In addition, a resistive layer may be disposed at an intersection of the plurality of word lines WL1 to WL4 and the plurality of bit lines BL1 to BL4, respectively.

Hereinafter, in this embodiment, word lines having substantially the same length and stacked to overlap each other will be referred to as a word line stack structure, and similarly, bit lines having substantially the same length and stacked to overlap each other will be referred to as a bit line stack structure. will be named

6A and 6B are equivalent circuit diagrams of a memory cell according to an embodiment of the present invention.

Referring to FIG. 6A , the memory cell MCa includes a bit line BL, a word line WL, a selection element SE-SW connected between the bit line BL and the word line WL, and a variable A resistor Rv1 may be included. The selection element SE-SW may include various selection elements such as, for example, a diode and a MOS transistor.

The variable resistor Rv1 may include, for example, a chalcogenide-based compound, a transition metal compound, a ferroelectric, or a ferromagnetic material. However, the variable resistance of the present invention is not limited to the above materials. Looking more closely, the variable resistor Rv1 may include a metal oxide. Metal oxides include, for example, oxides of transition metals such as nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zq) oxide, tungsten (W) oxide, cobalt (Co) oxide, STO (SrTiO) ), perovskite-based materials such as PCMO (PrCaMnO), and the like. Also, the variable resistor Rv1 may include a phase change material. The phase change material may be, for example, a chalcogenide-based material such as GST (Ge-Sb-Te). Such a variable resistance element may exhibit characteristics of switching between different resistance states by being stabilized in one of a crystalline state and an amorphous state by heat. Also, the variable resistor Rv1 may include a structure in which a tunnel barrier layer is interposed between two magnetic layers. The magnetic layer may be formed of a material such as NiFeCo or CoFe, and the tunnel barrier layer may be formed of a material such as Al ₂ O ₃ . The variable resistor Rv1 may exhibit characteristics of switching between different resistance states according to the magnetization direction of the magnetic layer. For example, the variable resistor Rv1 may be in a low resistance state when the magnetization directions of the two magnetic layers are parallel, and may be in a high resistance state when the magnetization directions of the two magnetic layers are antiparallel.

For example, when a predetermined signal is applied to the word line WL and a set or reset voltage is applied to the bit line BL crossing the word line WL, the selection element SE-SW is turned on. Therefore, the set or reset current may be applied to the variable resistor Rv1. Accordingly, the resistance value of the variable resistor Rv1 is varied, so that a memory operation can be performed.

Also, as shown in FIG. 6B , the memory cell MCb may include a bit line BL, a word line WL, and a variable resistor Rv2. When the voltage difference between the bit line BL and the word line WL is greater than or equal to the threshold voltage Vth, current is conducted in the variable resistor Rv2, and the resistance value of the variable resistor Rv2 is changed. can The resistance value may be varied in a set or reset state by a current applied to the variable resistor Rv2.

The variable resistor Rv2 performing the switching function as described above may include, for example, an ovonic threshold switch (OTS) layer as a resistance layer. The OTS layer may include a chalcogenide composition comprising any one of the chalcogenide alloy systems described above. The OTS layer is, for example, Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, One of Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se can include

The memory cell structure shown in FIGS. 6A and 6B may be referred to as a cross point array structure.

7 is a circuit diagram illustrating a principle of selecting a memory cell according to an exemplary embodiment of the present invention. For reference, the memory cell of FIG. 7 adopts the memory cell structure of FIG. 6B.

Before explaining the principle of selecting a memory cell, the word line WL and the bit line BL may be configured in a hierarchical manner, as known in the art. That is, in the hierarchical method, a plurality of local bit lines (or a plurality of local word lines) may be connected to one global bit line (or one global word line), and one local bit line (or one local word line) It is a structure in which a plurality of bit lines (or a plurality of word lines) are connected to. The bit lines and word lines arranged hierarchically in this way select one word line and one bit line through a decoding circuit including a word line selection unit and a bit line selection unit located in the control circuit region 120 . You can choose.

As is known, the global bit line GBL and the global word line GWL may be selectively supplied with a first voltage V1 (or second voltage) and a second voltage V2 (or first voltage). The first voltage V1 and the second voltage V2 may have a voltage difference sufficient to change physical properties of the resistance layer Rv. For example, when the first voltage V1 has a higher level than the second voltage V2, the first voltage V1 may correspond to a set voltage, a reset voltage, and a read voltage.

Global word line select switches (not shown) may be connected between the global word line GWL and the plurality of local word lines. The global word line selection switch may select a specific local word line LWL in response to a global word line selection signal.

Global bit line selection switches (not shown) may be respectively connected between the global bit line GBL and the plurality of local bit lines. The global bit line selection switch may select a specific local bit line LBL in response to a global bit line selection signal.

Local bit line selection switches TBL1 to TBL4 may be connected between the specific local bit line LBL and the plurality of bit lines BL1 to BL4, respectively, and the specific local word line LWL and the plurality of word lines. Local word line select switches TWL1 to TWL4 may be respectively connected between (WL1 to WL4). In the drawings and embodiments, the hierarchical structure between the global bit line (GBL) and the local bit line (LBL) and the hierarchical structure between the global word line (GWL) and the local word line (LWL) are known to those skilled in the art. Therefore, the detailed structure is omitted. For convenience, a structure in which only four local bit line select switches TBL1 to TBL4 and four local word line select switches TWL1 to TWL4 are connected to the global bit line GBL and the global word line GWL is shown.

The decoding circuitry (not shown) may generate the global word line selection signal (not shown) and the global bit line selection signal (not shown). In addition, the decoding circuit unit (not shown) includes word line selection signals SELW1 to SELW4 enabling one of the local word line selection switches TWL1 to TWL4 and local bit line selection switches TBL1 to TBL4. Bit line selection signals SELB1 to SELB4 enabling one can be generated. The global word line selection signal, the global bit line selection signal, the word line selection signals SELW1 to SELW4, and the bit line selection signals SELB1 to SELB4 are configured according to an address ADD provided from the controller 1100. It can be generated by decoding circuitry.

By the enabled bit line selection signals SELBL1 to SELB4 and the enabled word line selection signals SELW1 to SELW4, specific local bit line selection switches TBL1 to TBL4 and four local word line selection switches TWL1 to SELW4 are selected. When TWL4) is turned on, a first voltage and a second voltage are applied to the bit lines BL and word lines WL connected to the specific local bit line selection switches TBL1 to TBL4 and the four local word line selection switches TWL1 to TWL4. 2 voltages can be delivered respectively. Accordingly, a memory operation may be performed on the memory cell MC between the bit line BL and the word line WL.

In this embodiment, the local bit line select switches TBL1 to TBL4 may include, for example, PMOS transistors, and although not shown in the drawings, the global bit line select switches may also include PMOS transistors. Meanwhile, the local word line select switches TWL1 to TWL4 may include, for example, NMOS transistors, and although not shown, the global word line select switches may also include NMOS transistors.

The local bit line selection switches TBL1 to TBL4 and/or global bit line selection switches (not shown) may be disposed in the bit line selection unit BLSW of FIG. 3 . The local word line selection switches TWL1 to TWL4 and/or global word line selection switches (not shown) may be formed in the word line selection unit WLSW of FIG. 3 .

8A and 8B are schematic circuit diagrams for explaining the relationship between word lines and bit lines implementing six decks according to an embodiment of the present invention. Fig. 8A is a circuit diagram in parallel with word lines, and Fig. 8B is a circuit diagram in parallel with bit lines.

8A and 8B, the six decks D1 to D6 may include word lines WL_L1 to WL_L4 of the first to fourth layers and bit lines BL_L1 to BL_L3 of the first to third layers. can

The word lines WL_L1 to WL_L4 of the first to fourth layers may extend along the x-direction of the drawing and may be stacked along the z-axis direction of the drawing. The bit lines BL_L1 to BL_L3 of the first to third layers may extend along the y-direction of the drawing and may be stacked along the z-axis direction of the drawing.

A bit line BL_L1 of the first layer may be disposed between the word line WL_L1 of the first layer and the word line WL_L2 of the second layer. A first variable resistance layer Rv1 may be interposed between the word line WL_L1 of the first layer and the bit line BL_L1 of the first layer to form the first deck D1. A second variable resistance layer Rv2 may be interposed between the bit line BL_L1 of the first layer and the word line WL_L2 of the second layer to form the second deck D2. A bit line BL_L2 of the second layer may be disposed between the word line WL_L2 of the second layer and the word line WL_L3 of the third layer. A third variable resistance layer Rv3 may be interposed between the word lines WL_L2 of the second layer and the bit lines BL_L2 of the second layer to form the third deck D3.

In this way, word lines and bit lines may be alternately stacked, and resistance layers Rv1 to Rv6 are interposed at the intersections of the word lines WL_L1 to WL_L4 and the bit lines BL_L1 to BL_L3, respectively, so that 4 More than one layer, for example, six layers of stacked decks D1 to D6 may be formed. In particular, word lines (WL_L2, WL_L2, WL_L3) and the bit lines BL_L1 to BL_L3 may be commonly applied to adjacent stacked decks. In other words, adjacent stacked decks may share either word lines or bit lines.

For example, the bit line BL_L1 of the first layer is commonly applied to the first deck D1 and the second deck D2, and the word line WL_L1 of the second layer is applied to the second deck D2 and D2. It may be commonly applied to the third deck D3. Since word lines and bit lines are commonly applied to two decks in this way, to form 6-layer decks D1 to D6, substantially 4 stacked word lines and 3 stacked bit lines are required. .

In this drawing, one memory cell is described for one deck as an example for convenience of explanation, but a plurality of memory cells may be connected to one deck.

9 is a diagram schematically illustrating a connection relationship between word lines arranged on a plurality of mats and word line selectors arranged in a control circuit area according to an embodiment of the present invention. For reference, FIG. 9 shows a mat portion corresponding to A1 in FIG. 3 and a control circuit area corresponding to A2 in FIG. 4 on the same plane for convenience of description. Also, in this figure, the bit line selector BLSW and the bit lines BL1 to BLn are omitted, and the 21st to 23rd mat parts MAT21 to MAT23 and the 21st to 23rd mat parts MAT21 to MAT23 of FIGS. 3 and 4 are omitted. 23 Control circuit areas 120-21 to 120-23 will be described as an example.

Referring to FIG. 9 , the word line selector WLSW may be disposed in the control circuit regions 120-21 and 120-23 below the 21st mat MAT21 and the 23rd mat MAT23. The word line selector WLSW may be disposed in the first central portion CAx of the twenty-first control circuit area 120-21 and the twenty-third control circuit area 120-23. The first center CAx may correspond to a central region of the x-axis length of the twenty-first and twenty-third control circuit regions 120-21 and 120-23. The word line selector WLSW may include word line select switches TWL1 to TWLm located in each row.

The plurality of word lines WL1 to WLm extending in the row direction corresponding to the x direction of the drawing are separated based on the word line selectors WLSW_21 and WLSW_23, and can be divided into a plurality of word line stacked structures. . A length of the word line stack structure may correspond to a length between a pair of adjacent word line selectors WLSW_21 and WLSW_23 in the row direction.

The stacked word lines constituting the word line stack structures WL1 to WLm arranged between the word line selectors WLSW_21 and WLSW_23 are selected from among the 21st and 23rd word line selectors WLSW_21 and WLSW_23. can be connected with A connection structure between the stacked word lines and the word line selector will be described in more detail below.

As described above, the word line selection switches TWL1 to TWLm formed in the 21st and 23rd control circuit regions 120-21 and 120-23 include, for example, word line selection signals SELW1_21 to SELWm_21, It may be an NMOS transistor turned on in response to SELW1_23 to SELWm_23). The word line selection signals SELW1_21 to SELWm_21 and SELW1_23 to SELWm_23 may be generated in a decoding circuit unit based on address commands (not shown) provided from a controller (not shown). Word lines electrically connected to the turned-on word line select switches TWL1 to TWLm may receive a voltage applied to the global word line GWL.

10 is an equivalent circuit diagram of part “C” of FIG. 9 .

Referring to FIG. 10 , first word line select switches TWL1_21 and TWL1_23 may be positioned in the first row of the twenty-first control circuit region 120 - 21 and the twenty-third control circuit region 120 - 23 . As described above, the first word line stack structure is connected between the adjacent first word line select switches TWL1_21 and TWL1_23. In this embodiment, the word line stacked structure located in the first row between the 21st and 23rd mats is arbitrarily named a 21st first word line stacked structure (21st WL1 st) by assigning a mat number of the starting point. will be.

A plurality of word lines, eg, first word lines WL1_L1 to WL1_L4 of the first to fourth layers may be stacked in the 21st first word line stack structure 21th WL1 st.

The first word line select switch TWL1_21 positioned in the twenty-first control circuit region 120 - 21 may include an NMOS transistor including a gate, a source, and a drain. The gate may receive a word line selection signal SELW1_21. The source may be substantially electrically connected to the global word line GWL. The drain is selected from a first word line stacked structure (hereinafter, a 19th first word line stacked structure: 21st WL1 st) extending in the -x direction (left direction) with the first word line select switch TWL1_21 as a center. and a first word line stacked structure (hereinafter referred to as a 21st first word line stacked structure: 21st WL1 st) extending in the +x direction (right direction) centered on the first word line select switch TWL1_21. It can be electrically connected to a part that is.

As an example, the other ends of the even-numbered word lines of the 19th first word line stack structure 21th WL1 st, that is, the word lines WL1_L2 and WL1_L4 of the second and fourth layers may be connected to the first word line It may be connected in common with the drain of the selection switch TWL1_21. At the same time, one end of the odd-numbered word lines of the 21st first word line stacked structure 21th WL1 st, that is, the word lines WL1_L1 and WL1_L3 of the first and third layers may also be connected to the first word line select switch. It can be commonly connected to the drain of (TWL1_21).

In this embodiment, one end may mean, for example, an end located on the left side of the drawing, and the other end may mean, for example, an end located on the right side of the drawing.

The first word line select switch TWL1_23 formed in the twenty-third control circuit region 120-23 has a gate receiving the word line select signal SELW1_23 and a source electrically connected to a substantially global word line GWL. can include In addition, the drain of the first word line select switch TWL1_23 is connected to the even-numbered word lines WL1_L2 and WL1_L4 not connected to the first word line select switch TWL1_21 of the 21st first word line stack structure 21th WL1 st. ) and one end of the odd-numbered word lines WL1_L1 and WL1_L3 of the 23rd first word line stack structure 23th WL1 st.

For example, when the twenty-first word line selection signal SELW1_21 is enabled, the first word line selection switch TWL1_21 of the twenty-first control circuit region 120-21 is turned on. Accordingly, word lines WL1_L2 and WL1_L4 of even-numbered layers of the 19th first word line stack structure 19th WL1 st and word lines WL1_L1 of odd-numbered layers of the 21st word line stack structure 19th WL1 st A global word line voltage may be transferred to WL1_L3).

Meanwhile, when the twenty-third word line selection signal SELW1_23 is enabled, the first word line selection switch TWL1_23 of the twenty-third control circuit region 120-23 is turned on. Accordingly, even-numbered word lines WL_L2 and WL_L4 of the 21st unit first word line stack structure 21th WL1 st and odd-numbered word lines WL1_L1, The global word line voltage may be transferred to WL_L3).

11 is a cross-sectional view of a main part of a resistance variable memory device cut in a direction parallel to a word line according to an exemplary embodiment of the present invention.

Referring to FIG. 11 , a semiconductor substrate 110 is prepared. The semiconductor substrate 110 includes, for example, a plurality of mats MAT21 to MAT23 and control circuit regions 120 - 21 , 120 - 22 , and 120 - 23 corresponding to the plurality of mats MAT21 to MAT23 . may be limited.

In a predetermined portion of the semiconductor substrate 110 corresponding to the twenty-first control circuit region 120-21 and the twenty-third control circuit region 120-23, NMOS transistors are known as word line select switches TWL1_21 and TWL1_23. formed in a way

Although not shown in detail in the drawings, during the step of forming the word line select switches TWL1_21 and TWL1_23, NMOS transistors constituting other control circuit regions may be formed at the same time.

A first insulating layer 115 is deposited on the semiconductor substrate 110 on which the word line select switches TWL1_21 and TWL1_23 are formed. First contact plugs CP21 and CP23 may be formed in the first insulating layer 115 to electrically contact the drains of the word line select switches TWL1_21 and TWL1_23. Although not shown in the drawings, gates of the word line select switches TWL1_21 and TWL1_23 may be electrically connected to wires (not shown) transmitting the first word line select signals SELW1_21 and SELW1_23. Also, sources of the first word line select switches TWL1_21 and TWL1_23 may be electrically connected to the global word line GWL via a local word line (not shown) and a global word line select switch (not shown). . Accordingly, the control circuit layer 120 may be formed on the semiconductor substrate 110 .

A first word line WL1_L1 of a first layer is formed on the first insulating layer 115 . As described above, the unit first word line WL1_L1 of the first layer may be patterned to have a length equal to the distance between adjacent word line select switches TWL1_21 and TWL1_23. As described above, the first word lines WL1 of the first layer are arranged to pass through the three mats MAT21, MAT22, and MAT23 in the drawing, but the 21st word line select switch TWL is formed Since the mat MAT21 and the 23rd mat MAT23 occupy only about 50% of the area, the length of the word line can be substantially defined as the x-axis length of the two mats.

After forming the first word line WL1_L1 of the first layer, forming a resistive layer Rv1, forming bit lines BL1_L1 to BLn_L1, forming a resistive layer Rv2, and By repeating the step of forming one word line at least three times, at least six or more decks D1 to D6 can be formed. Although not shown in detail in the drawings, insulating films (not shown) are formed on both sides of the word lines constituting the word line stack structure WL1, on both sides of the resistance layer Rv, and on both sides of the bit lines BL, so that memory cells are connected to each other. can be insulated from each other.

At this time, the drain of the first weed line select switch TWL1_21 located in the twenty-first control circuit region 120-21 is connected to the 19th first word line stacked structure 19th WL st through a contact plug CP21. The other end of the first word lines WL1_L2 and WL1_L4 of the second and fourth layers and the first word lines WL1_L1 of the first and third layers of the 21st first word line stack structure 21th WL1 st It may be electrically connected to one end of WL1_L3 through the via plug VP.

Meanwhile, the drain of the first word line select switch TWL1_23 located in the twenty-third control circuit region 120-23 is a 21st word line stacked structure through a contact plug CP23 and a via plug VP. The other end of the first word lines WL1_L2 and WL1_L4 of the second and fourth layers of (21st WL1 st) and the first and third layers of the 23rd first word line stack structure (23th WL1 st) It may be electrically connected to one end of one word line (WL1_L1, WL1_L3).

Accordingly, when the first word line select switch TWL1_21 of the twenty-first control circuit region 120-21 is turned on, the second and fourth layers of the twenty-first word line stacked structure 21th WL1 st are turned on. Global word line voltages may be provided to the first word lines WL_L2 and WL_L4 and the first word lines WL1_L1 and WL1_L3 of the first and third layers of the 23rd first word line stack structure 23th WL1 st. there is.

Meanwhile, when the first unit with line select switch TWL1_23 formed in the twenty-third control circuit region 120-23 is turned on, the second layer and the fourth layer of the 21st word line stacked structure 22nd WL1 st are turned on. The global word line voltage is provided to the first word lines WL1_L2 and WL1_L4 of the first layer and the first word lines WL_L1 and WL_L3 of the first and third layers of the 23rd first word line stack structure 23th WL st. It can be.

In addition, although the word lines WL1_L1, WL1_L2, WL1_L3, and WL1_L4 constituting the word line stacked structure WL1 st of the present embodiment have substantially the same length, as shown in FIG. 11, the word line select switch TWL21, TWL23) and the stacked word lines WL1_L1, WL1_L2, WL1_L3, and WL1_L4 may be easily connected, so that a portion of the word line connected to the corresponding word line selection switch may be drawn out toward the corresponding word line selection switch by a predetermined length. there is.

12 is a diagram schematically illustrating a connection relationship between bit lines arranged on a plurality of mats and a bit line selection unit arranged in a control circuit area according to an embodiment of the present invention.

For reference, FIG. 12 shows a portion B1 of FIG. 3 and a portion B2 of FIG. 4 formed on different planes on the same plane for convenience of explanation, and the word line selector WLSW and word lines WL1 to WLm are shown. The city for is omitted. In addition, FIG. 12 will explain the 13th, 23rd, and 33rd mat portions (MAT13, MAT23, MAT33 and control circuit areas corresponding thereto) sequentially arranged in the y-direction of FIGS. 3 and 4 as an example.

Referring to FIG. 12 , bit line selectors BLSW13 and BLSW33 may be disposed in the control circuit regions 120 - 13 and 120 - 33 below the 13th mat MAT13 and the 33rd mat MAT33 . The bit line selectors BLSW13 and BLSW33 may be disposed in the second central portion CAy of the thirteenth control circuit area 120 - 13 and the thirty third control circuit area 120 - 33 . The second center CAy may correspond to a center area of the y-axis length of the thirteenth and thirty-third control circuit areas 120-21 and 120-23. A bit line selector ( BLSW) may be provided. The bit line selector BLSW may include bit line select switches TBL1 to TBLm for each column in which each bit line is located.

In addition, the bit lines BL1 to BLm formed for each column may be separated based on the bit line selectors BLSW_13 and BLSW_33. At this time, since each of the bit lines BL1 to BLm is composed of stacked bit lines, they may be separated into a plurality of bit line stacked structures by the bit line selector BLSW. A length of the bit line stack structure may correspond to a length between a pair of bit line selectors BLSW_13 and BLSW_33 adjacent in the column direction.

The number of stacked bit lines constituting the bit line stack structure may be smaller than the number of stacked word lines constituting the word line stack structure.

As described above, the bit line select switches TBL1 to TBLn may be, for example, PMOS transistors turned on in response to bit line select signals SELB1_13 to SELBn_13, SELB1_23 to SELBn_23, and SELB1_33 to SELBn_33. The bit line selection signals SELB1_13 to SELBn_13, SELB1_23 to SELBn_23, and SELB1_33 to SELBn_33 may be generated by the decoding circuit unit based on an address command (not shown) provided from a controller (not shown). The bit lines BL1 to BLn electrically connected to the turned-on bit line select switches TBL1 to TBLn may receive the voltage transferred to the global bit line GBL. Although the figure selectively shows the 13th mat MAT13, the 23rd mat MAT23, and the 33rd mat MAT33 arranged side by side in the y direction, the mats MAT13, MAT23, and MAT33 are arranged side by side. If the 43rd mat, the 53rd mat and the 63rd mat are arranged side by side, they will be arranged according to the same rules as the 13th mat (MAT13), the 23rd mat (MAT23) and the 33rd mat (MAT33).

FIG. 13 is an equivalent circuit diagram of part “E” in FIG. 12 .

Referring to FIG. 13 , the 13th control circuit area 120-13 under the 13th mat MAT13 and the 33rd control circuit area 120-33 under the 33rd mat MAT33 have a first bit line selection switch. As (TBL1_13, TBL1_33), PMOS transistors may be connected for each column. The first bit line select switch TBL1_13 of the thirteenth control circuit region 120 - 13 may include a gate, a source, and a drain. The gate may receive the bit line select signal SELB1_13. The source may be electrically connected to the global bit line GBL. Although not shown, a local bit line selection switch (not shown) and a local bit line (not shown) may be connected between the global bit line GBL and the first bit line selection switch TBL1_13. . The drain is one selected from among first bit line stacked structures (hereinafter referred to as first bit line stacked structures: 3rd BL1 st) extending in the -y direction centered on the first bit line select switch TBL1_13 (eg For example, a first bit line stacked structure extending in the +y direction centered on the first bit line of the first layer: BL1_L1 and the first bit line select switch TBL1_13 (hereinafter referred to as a 13th first bit line stack) Structure: 13th BL1 st) may be connected to a selected one (eg, the first bit line of the second layer: BL1_L2).

The first bit line selection switch TBL1_33 of the thirty-third control circuit region 120 - 33 may also include a gate, source, and drain. The gate may receive the bit line select signal SELB1_33. The source may be electrically connected to the global bit line GBL. The drain is a 13th bit line stacked structure extending in the -y direction centered on the first bit line select switch TBL1_33: 13th BL1 st) (eg, the first layer of the first layer). A first bit line stacked structure (hereinafter referred to as a 33rd first bit line stacked structure: 33th BL st) extending in the +y direction centered on the bit line BL1_L1 and the first bit line select switch TBL1_33. (eg, the first bit line of the second layer: BL1_L2). In this case, one end is connected to the first bit line select switch TBL1_13 to the thirteenth control circuit region 120-13. The other end of the first bit line BL1_L2 of the second layer of the 13th first bit line stacked structure 13th BL1 st is the first bit line of the third layer of the 33rd first bit line stacked structure 13th BL1 st. It may be electrically connected to one end of the bit line BL1_L2.

Although not shown in the drawing, the 23rd control circuit area 120-23 between the 13th control circuit area 120-13 and the 33rd control circuit area 120-33 includes a bit line selector BLSW. Instead of not including it, a word line selector WLSW may be included.

As an example, when the first bit line select switch TBL1_13 of the thirteenth control circuit region 120 - 13 is turned on, the first bit line of the first layer of the third first bit line stack structure 13th BL1 st (BL1_L1), the second layer first bit line BL1_L2 of the 13th first bit line stack structure 13th BL1 st and the first bit of the third layer of the 33rd first bit line stack structure 33th BL1 st A global bit line voltage GBL is applied to the line BL1_L3. Meanwhile, although not shown in FIG. 13, word lines (not shown) may be arranged in multiple layers along each row on the 13th, 23rd, and 33rd mats MAT13, MAT23, and MAT33. In addition, a voltage difference is generated in a memory cell at a portion crossing a selected word line receiving a global word line voltage in the corresponding mat, so that a memory operation can be performed.

Accordingly, one bit line selection switch may control bit line stacked structures disposed adjacent to each other in the same column direction as many as the number of stacked bit lines. In particular, adjacent bit line stacked structures controlled by the one bit line selection switch may be sequentially connected in a stair form layer by layer. As a result, since one bit line is selected from one bit line stacked structure in response to the bit line select signal SELB1, there is no restriction on the number of stacked bit lines, so that unlimited memory cells can be stacked.

14 is a main cross-sectional view of a resistance variable memory device cut in a direction parallel to a bit line according to an exemplary embodiment of the present invention.

14 shows a 13th mat (MAT13), a 23rd mat (MAT23), a 33rd mat (MAT33), a 43rd mat (MAT43), a 53rd mat (MAT53), and a 63rd mat arranged side by side along the y direction of the drawing. A cross-sectional view of the resistance change memory device shown by cutting along a direction parallel to the first bit line in the mat MAT63 and the seventy-third mat MAT73. The 13th mat (MAT13), 23rd mat (MAT23), 33rd mat (MAT33), 43rd mat (MAT43), 53rd mat (MAT53), 63rd mat (MAT63) and 73rd mat (MAT73) Although they actually have the same size, in order to highlight the characteristic components of the present invention, the main parts are enlarged and shown.

Referring to FIG. 14 , a semiconductor substrate 110 in which an area where a plurality of mats are to be formed is limited is prepared. For example, the 13th mat (MAT13), the 23rd mat (MAT23), the 33rd mat (MAT33), the 43rd mat (MAT43), the 53rd mat (MAT53), the 63rd mat (MAT63) and the 73rd mat. In order to form a PMOS transistor in a predetermined portion of (MAT73), a separate n-well region (not shown) may be formed, and the global selection switch may also be formed in the n-well region. The 13th mat (MAT13), 23rd mat (MAT23), 33rd mat (MAT33), 43rd mat (MAT43), 53rd mat (MAT53), 63rd mat (MAT63) and 73rd mat (MAT73) A PMOS transistor is formed in the n-well region in a known manner to form bit line select switches TBL1_13, TBL1_33, TBL1_53.... The bit line select switches TBL1_13, TBL1_33, TBL1_53... are positioned on the same plane as the word line select switches TWL1_21 and TWL1_23, but may be formed through different processes.

A first insulating layer 115 is deposited on the semiconductor substrate 110 on which the bit line select switches TBL1_13, TBL1_33, TBL1_53... and the word line select switches (not shown) are formed. First contact plugs CP13 , CP33 , and CP53 electrically contacting drains of the bit line select switches TBL1_13 , TBL1_33 , and TBL1_53 may be formed in the first insulating layer 115 by a known method. In addition, although not shown in detail in this drawing, the gates of the bit line select switches TBL1_13, TBL1_33, and TBL1_53 are electrically connected to conductive wires (not shown) transmitting the first bit line select signals SELB1_13, SELB1_33, and SELB1_53. can be connected to Sources of the bit line select switches TBL1_13, TBL1_33, and TBL1_53 may be electrically connected to the global bit line GBL via a local bit line (not shown) and a global bit line select switch (not shown). Accordingly, the bit line select switch TBL is formed on the semiconductor substrate 110 together with the word line select switch TWL, so that the control circuit layer 120 including each control circuit region can be configured. there is.

First word lines WL1_L1 to WLm_L1 of the first layer may be formed on the first insulating layer 115 to correspond to each row. The first word lines WL1_L1 to WLm_L1 may be spaced apart at regular intervals and may extend by a predetermined length in the x direction (eg, row direction) of the drawing.

A resistive layer Rv is formed on the first to mth word lines WL1_L1 to WLm_L1, respectively. The resistive layer Rv may be formed to have a line width smaller than or equal to that of the first to m th word lines WL1_L1 to WLm_L1. A plurality of first bit lines BL1_L1 of the first layer may be formed to cross the first to mth word lines WL1_L1 to WLm_L1. As described above, each of the first bit lines BL1_L1 of the first layer may be positioned between two adjacent bit line select switches TBL1_13, TBL1_33, and TBL1_53. Each of the first bit lines BL1_L1 may have one end and the other end in the longitudinal direction (y-axis direction). In this case, one end of the first bit line BL1_L1 may be electrically connected to the bit line selection switches TBL1_13, TBL1_33, and TBL1_53 positioned below it. Accordingly, a first deck D1 including the first layer word line WL1_L1, the resistive layer Rv1, and the first layer bit line BL1_L1 is formed.

In addition, before forming the first bit line BL1_L1 of the first layer, contact plugs CP13, CP33, CP53) can be formed. One end (or the other end) of the first bit lines BL1_L1 of the first layer may be electrically connected to the bit line selection switch through the contact plugs CP13 , CP33 , and CP53 .

Meanwhile, the resistive layer Rv is formed on the first bit line BL1_L1 of the first layer, and the word line of the second layer ( WL1_L2 to WLm_L2) may be formed to constitute the second deck D2.

In this way, the plurality of deck layers D1 to D6 may be formed by alternately stacking the word lines WL1 to WLm, the resistance layer Rv, and the bit line BL1.

In this embodiment, like the word line stack structure, the number of the bit line stack structure is assigned by giving the mat number of the starting point of the bit line stack structure, but the corresponding number may be variable.

For example, one end of the first bit line BL1_L1 of the first layer of the 13th first bit line stack structure 13th BL1 st is connected to the 13th control circuit region 120-13 by the contact plug CP13. ) and electrically connected to the bit line selection switch (TBL1_13) located at Meanwhile, the other end of the first bit line BL1_L1 of the first layer of the thirteenth first bit line stack structure 13th BL1 st has a 33rd first bit line continuously arranged in the same column direction by a via plug VP. It may be electrically connected to one end of the first bit line BL1_L2 of the second layer of the bit line stack structure 33th BL1 st. The other end of the first bit line BL1_L2 of the second layer of the 33rd first bit line stacked structure 33th BL1 st is the third layer of the 53rd first bit line stacked structure 53th BL1 st. One end of the 1-bit line BL1_L3 may be electrically connected by a via plug.

As a result, the bit line select switch TBL is connected to the bit line of the 11th layer of the bit line stack structure positioned thereon, and the bits of the bit line stack structure adjacent to each other in the same column direction by the number of stacked bit lines. It is connected in the form of lines and stairs.

15 is a main cross-sectional view of a resistance variable memory device cut in a direction parallel to a bit line according to another embodiment of the present invention. 15 is mostly similar to the configuration of FIG. 14, but may be partially different in terms of connection between the bit line selection switch and the bit lines.

Referring to FIG. 15 , the word lines WL1 to WLm, the resistive layer Rv, and the bit lines BL1 to BLn may be stacked and arranged in the same manner as in FIG. 14 .

The other end of the first bit line BL1_L1 of the first layer of the 13th first bit line stacked structure 13th BL1 st and the first layer of the second layer of the 33rd first bit line stacked structure 33th BL1 st. One end of the bit line BL_L2 may be connected to the drain of the bit line select switch TBL1_33 positioned in the 33rd control circuit region 120-33 by the contact plug CP33 and the via plug VP. In addition, the other end of the first bit line BL1_L2 of the second layer of the 13th first bit line stacked structure 13th BL1 st is the third layer of the 33rd first bit line stacked structure 33th BL1 st. One end of the first bit line BL_L3 may be electrically connected by a via plug.

Similarly, the drain of the first bit line select switch TBL1_53 of the 53rd control circuit region 120-53 is also the first bit line BL1_Ll of the first layer of the 33rd first bit line stacked structure 33th BL1 st. The other end of and one end of the first bit line BL1_L2 of the second layer of the 53rd first bit line stack structure 53th BL1 st may also be electrically connected by the contact plug CP53 and the via plug VP. there is. The other end of the first bit line BL1_L2 of the second layer of the 53rd first bit line stack structure 53th BL1 st is the first bit of the third layer of the 73rd first bit line stack structure 73rd BL1 st. One end of the line BL1_L3 may be electrically connected to the via plug VP.

Such a structure may also be connected to the stacked bit lines of an adjacent bit line stack structure in a stepped form.

Further, in this embodiment, the plurality of stacked bit lines constituting one bit line stack structure have substantially the same length and overlap, but as shown in FIGS. 14 and 15, the bit line select switch and the direct, The indirectly contacted portion may be drawn out by a predetermined length to facilitate contact.

16 is a diagram for explaining a process of selecting memory cells of a specific mat according to an embodiment of the present invention. In this embodiment, a process of selecting the memory cell MCab_D6 of the first mat MAT01 will be described. In the drawing, 120p corresponds to a plan view showing a part of the control circuit area, and MATs_x is a cross-sectional structure of the first to fourth mats (MAT01 to MAT04) shown by cutting in the direction of the a-th word line located in the a-th row of the mat indicates schematically. In addition, Mats_y is the 1st, 11th, 21st, 31st, 41st, and 51st mats (MAT01, MAT11, MAT21, MAT31, MAT41, MAT51 ) indicates the schematic cross-sectional structure of In addition, in this embodiment, for convenience, the word line selector WLSW is located in the first control circuit area 120-01, and the control circuit adjacent to the first control circuit area 120-01 in the x and y directions A bit line selector (BLSW) is located in the regions 120-02 and 120-11, and a control circuit area in which the word line selector (WLSW) is disposed and a control circuit area in which the bit line selector (BLSW) are arranged It will be explained on the premise that they are alternately arranged alternately. Also, one word line stack structure may be formed by stacking four layers of word lines, and one bit line stack structure may be formed by stacking three layers of bit lines.

Referring to FIG. 16 , in order to select the memory cell MCab_D6 located on the sixth deck D6 of the first mat MAT01, the fourth layer of the third word line stack structure 3rd WLa st The position a th word line WLa_L4 and the b th bit line BLb_L3 of the third layer of the first b th bit line stack structure 51st BLb st should be selected.

As described in FIG. 11, the a-th word line WLa_L4 of the fourth layer of the third a-th word line stack structure 3rd WLa st is connected to a third control circuit through a via plug VP and a contact plug. It may be connected to the word line selector WLSW located in the region 120-03. Preferably, the a-th word line WLa_L4 positioned in the fourth layer of the third a-word line stacked structure 3rd WLa st is a word line selector located in the third control circuit region 120-03 ( WLSW) may be electrically connected to a word line selection switch (not shown) located in the a-th row. Accordingly, the global word line voltage is transferred to the a-th word line WLa_L4 located in the fourth layer of the third a-th word line stack structure 3rd WLa st. In this case, the a word line WLa_L3 of the third layer facing the a word line WLa_L4 of the fourth layer of the third word line stack structure 3rd WLa st is the first control circuit region ( 120-01), they are not enabled at the same time because they are controlled by the word line selector.

Meanwhile, in order to select the b-th bit line BLb_L3 located in the third layer of the 1-th b-th bit line stack structure 1st BLb st, the first b-th bit line stack structure 1st BLb st Starting from the bit line selector BLSW of the 11th control circuit region 120-11 connected to the bit line BLb_L1 of the layer, as many as the stacked number of bit lines are sequentially arranged in the column direction (for example, 3 The bit line select switch located in the b-th column of the bit line selector BLSW of the 51st control circuit region 120-51 (corresponding to the th) is enabled. Then, the b-th bit line BLb_L1 of the first layer of the fifth bit line stack structure 5th BLb st and the b-th bit line of the second layer of the third and second bit line stack structure 3rd BLb st The global bit line voltage is transferred to the b-th bit line BLb_L3 positioned in the third layer of the first b-th bit line stack structure 1st BLb st via BLb_L2.

Accordingly, the a-th word line WLa_L4 located in the fourth layer of the third a-th word line stack structure 3rd WLa st and the third layer of the first b-th bit line stack structure 51st BLb st The resistance layer between the b bit lines BLb_L3 is varied, and a memory operation is performed.

The b-th bit line BLb_L1 of the first layer of the fifth b-th bit line stack structure 5th BLb st and the b-th bit line of the second layer of the third b-th bit line stack structure 3rd BLb st BLb_L2) and the b-th bit line BLb_L3 of the third layer of the first b-th bit line stack structure 1st BLb st, the global bit line voltage is applied, and the third a-th word line stack structure 3rd WLa st Global word line voltages on the word lines WLa_L2 and WLa_L4 of the 4th and 2nd layers and the 1st and 3rd layer word lines WLa_L1 and WLa_L3 of the 5th word line stack structure 5th WLa st Even if all of these are applied, substantially the b-th bit line BLb_L3 of the third layer of the third b-th bit line stack structure 1st BLb st and the fourth layer of the third a-th word line stack structure 3rd WLa st Since an intersection occurs between the word lines WLa_L4 of the layer, only the memory cell MCab_D6 corresponding to the intersection is selected.

In this figure, the connection structure between the bit line stacked structure and the bit line selector has been described using the example of FIG. 14 , but the same effect can be achieved by applying the example of FIG. 15 .

According to the present embodiment, in a bank including stacked memory cells, word line selection units and bit line selection units are alternately disposed for each mat. In addition, the word line stack structure prevents word lines stacked adjacent to each other from being selected at the same time, while bit lines of the bit line structure disposed adjacent to each other are connected in a stepwise manner with bit lines of different levels, Only one memory cell can be effectively selected.

Accordingly, even if a plurality of word lines and bit lines of six or more layers are stacked, one memory cell can be effectively selected. Furthermore, the integration density of the resistance variable memory device may be improved.

In addition, although it is shown in this embodiment that a global word line signal or a global bit line signal is provided to a selected word line and a selected bit line by one switch in FIGS. 9, 10, 12, and 13, this is For convenience only, it is obvious to those skilled in the art that the global word line switch and the global bit line switch are connected in a general hierarchical connection structure as illustrated in FIG. 7 .

Although the present invention has been described in detail with preferred embodiments, the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

10: semiconductor system 1000: processor
1100: controller 100: memory device
110: semiconductor substrate 120: control circuit layer

Claims (22)

a bank layer positioned on a semiconductor substrate and composed of a plurality of mats including a plurality of stacked memory cells; and
a control circuit layer positioned between the semiconductor substrate and the bank layer and including a plurality of control circuit regions partitioned in a form corresponding to the plurality of mats;
The plurality of stacked memory cells include a plurality of stacked word lines and a plurality of stacked bit lines intersecting between the plurality of stacked word lines,
A word line selector configured to control the plurality of stacked word lines is disposed in a portion of the plurality of control circuit regions, and a bit line selector configured to control the plurality of bit lines is disposed in the remaining portion, and the word line selector is configured to control the plurality of bit lines. A resistance variable memory device, wherein a control circuit area in which the selector is disposed and a control circuit area in which the bit line selector is disposed are alternately and repeatedly arranged. According to claim 1,
Each of the plurality of mats is limited to a plurality of row areas and a plurality of column areas crossing the rows, and the plurality of stacked word lines extend for each row, and one The stacked plurality of bit lines are extended for each column of
The plurality of stacked word lines are separated in units of length between a pair of word line selectors disposed adjacently along the row direction to be defined as a plurality of word line stacked structures;
The resistance change memory device of claim 1 , wherein the stacked plurality of bit lines are separated by a unit of length between a pair of bit line selectors disposed adjacently along the column direction and limited to a plurality of bit line stacked structures. According to claim 2,
The plurality of stacked memory cells may further include a resistive layer interposed at each intersection of the alternately stacked word line and the bit line. According to claim 2,
Word lines of an odd (or even) layer of the word line stack structure are electrically connected to the word line selector located below one side of the word line stack structure, and the even (or odd) layer of the word line stack structure Word lines of the th) layer are electrically connected to the word line selector located on the other side of the word line stack structure. According to claim 2,
The resistance variable memory device of claim 1 , wherein the word line selector includes a word line select switch provided for each row region of the control circuit region where the word line selector is located. In the fifth,
The word line select switch is simultaneously connected to the word line stack structure disposed on both sides of the switch,
The word line select switch is simultaneously connected to odd (or even) word lines of one word line stack structure and even (or odd) word lines of the other word line stack structure. According to claim 6,
wherein the word line select switch is configured to transfer a first driving voltage to the word line connected to the word line select switch in response to an enabled word line select signal. According to claim 2,
The bit line stack structure is a resistance variable memory configured such that one end selected from one end and the other end of a lowermost bit line among the stacked bit lines is electrically connected to the bit line selector positioned thereunder. Device. According to claim 2,
The resistance change memory device of claim 1 , wherein the bit lines positioned on different layers are connected to each other in the number of bit line stacked structures as many as the number of stacked bit lines continuously arranged in the column direction. According to claim 8,
One end of a bit line of an arbitrary a-th layer (where a is a natural number of 2 or more) among the plurality of stacked bit lines constituting the bit line stack structure is located adjacent to the same column and is located adjacent to the previous ( or later) the resistance variable memory device electrically connected to the other end of the bit line of the a-1th layer of the bit line stack structure. According to claim 9,
When the bit line stack structure is configured by stacking a+1 bit lines, the other end of the bit line of the a-th layer is located after (or before) the bit line stack structure adjacent to the same column. A resistance variable memory device electrically connected to one end of a bit line of an a+1 th layer of the bit line stack structure located thereon. A control circuit layer including a plurality of control circuit regions divided in a matrix form along first and second directions crossing each other on a semiconductor substrate, and a bank layer positioned on the control circuit layer and including a plurality of memory cells A resistance change memory device comprising a,
The plurality of memory cells include a plurality of first electrode lines, a plurality of second electrode lines arranged to cross the plurality of first electrode lines, and an intersection of the plurality of first electrode lines and the plurality of second electrode lines. Including a resistive layer respectively located in the portion,
The plurality of control circuit regions include a plurality of first control circuit regions in which a first electrode line selector for selecting the first electrode line is disposed, and a second electrode line selector for selecting the plurality of second electrode lines. Including second control circuit regions that become,
The resistance change memory device of claim 1 , wherein the first control circuit region and the second control circuit region are alternately disposed along the first and second directions. According to claim 12,
In the bank layer, the plurality of first electrode lines and the plurality of second electrode lines are alternately stacked a plurality of times, and the resistance layer is an intersection of the alternately stacked first electrode lines and the second electrode lines. Resistance change memory devices located in each of the units. According to claim 13,
The stacked first electrode lines are separated to have a length equal to between a pair of first electrode line selectors adjacent in the first direction and separated into unit first electrode line stacked structures,
The first electrode line stacked adjacently among the stacked first electrode lines constituting the unit first electrode line stack structure is configured to be controlled by a first electrode line selector different from each other. 15. The method of claim 14,
The first electrode line selector positioned at the lower end of one side of the unit first electrode line stack structure is an odd-numbered (or even-numbered) first electrode line among the stacked first electrode lines constituting the individual first electrode line stack structure. It is connected to one end of the electrode lines,
The first electrode line selector positioned at the lower end of the other side of the unit first electrode line stack structure is an even-numbered (or odd-numbered) first of the stacked first electrode lines constituting the unit first electrode line stack structure. A resistance change memory device electrically connected to the other ends of the electrode lines. According to claim 13,
The stacked second electrode lines are separated to have a length equal to between a pair of second electrode line selectors adjacent in the second direction and separated into unit second electrode line stacked structures,
One end selected from among one end and the other end of the second electrode line positioned at the lowermost of the unit second electrode line stack structures is the second electrode line selector positioned below the selected end, and electrically connected and electrically connected to one end of a second electrode line of a second layer of the unit second electrode line stack structure neighboring in the second direction with the remaining unselected end portion electrically connected to the resistance change memory device. 17. The method of claim 16,
When the unit second electrode line stack structure is formed by stacking n−1 second electrode lines, as many as n−1 units continuously arranged in the second direction from the selected unit second electrode line stack structure. The resistance change memory device of claim 1 , wherein the second electrode lines are connected to each other in a stepped form up to the second electrode line stacked structure. 15. The method of claim 14,
In the first electrode line stack structure and the second electrode line stack structure, when the memory cell is selected, the first electrode line stack structure includes at least one of the first electrodes that do not face each other with the second electrode line interposed therebetween. A first voltage is applied to a line, and the second electrode line stack structure is configured such that a second voltage having a difference between the first voltage and a threshold voltage is applied to a selected one of a plurality of stacked second electrode lines. Resistance change memory device. a plurality of word line stack structures formed by stacking n word lines along each row;
a plurality of bit line stack structures in which n−1 bit lines are stacked along columns crossing each row;
word line select switches disposed in lower regions of both end portions of the word line stack structure, respectively; and
bit line selection switches respectively disposed in lower regions of both ends of the bit line stack structure;
When a selected one of the word line select switches is enabled, a first voltage is applied to at least one word line among the word line stacked structures connected to the enabled word line select switch;
When a selected one of the bit line select switches is enabled, a total of n-1 bit line stacks sequentially arranged in the column direction including the bit line stack structure connected to the enabled bit line select switch. A resistive change memory device configured to provide a second voltage having a threshold voltage difference from the first voltage to selected bit lines of a structure. According to claim 19,
The resistance change memory device of claim 1 , wherein the n−1 bit line stacked structures connected to the enabled bit line select switch are sequentially connected from the lowest bit line to the bit lines of the n−1 layer in a stepwise manner. According to claim 19,
A resistive variable memory device comprising a resistive layer provided at each intersection of the word line stack structure and the bit line stack structure to define memory cells. According to claim 19,
A control circuit area in which the word line select switches are formed and a control circuit area in which the bit line select switches are formed are alternately arranged along the row direction and the column direction.

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